JPS58115681A - Bit line driving circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To increase a bit line current during writing and to increase a writing speed by allowing PNP type transistors (TR) to switch bit lines of a semiconductor memory equipped with memory cells having the PNP type load TRs. CONSTITUTION:In a bit line driving circuit BDR, a selection signal VA is at a level (L) when bit lines B0 and B1 are not selected and a TRTD0 turns on to obtain an output (N) from the driving circuit BDR, thereby turning off the PNP type TRs TB0 and TB1. When the bit lines B0 and B1 are selected, the selection signal goes up to the level (H) and the base potential of the TRTD0 drops. Therefore, the emitter potential of the TRTD0 also drops and bit line selection TRs TB0 and TB1 turn on. In the driving circuit BDR, when a control signal R/W is at (H), i.e. during reading, the output level is higher than when the control signal R/W is at (L), i.e. during writing. Therefore, a bit line current is greater during the writing than during the reading to the contrary.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a bit line drive circuit for a semiconductor memory, and more particularly, to a bit line drive circuit for a semiconductor memory in which switching between pin and p1ts is performed by a front-shadow transistor. Regarding drive circuits.

(2) Technical background In general, Pi? - In a semicircular memory, memory cells constituted by bipolar transistors are arranged at each intersection of a plurality of word lines and bit lines, and a bit line selection drive circuit is provided for each column. In semiconductor memories such as those described above, lower power consumption and higher speed are required as elements become more highly integrated, and accordingly, lower power consumption and higher speed are also sought in bit line drive circuits.

(3) Prior art and problems Conventionally, in order to reduce power consumption and increase speed in semiconductor memories as described above, PNP
A semiconductor memory has been proposed that uses a memory cell having an N-fish transistor and increases the bit line current during writing. The semiconductor memory in Figure 1 is
For example, this is disclosed in %lIA No. 56-047428, in which a memory cell having a PNP load transistor is used, and the standby current is small, and the bit current during writing is By increasing K, the writing speed is increased.

However, in the semiconductor memory shown in FIG. 1, it is necessary to provide a relatively complicated circuit to increase the pit line current during writing, and furthermore, it is necessary to provide an NP circuit for pit line selection drive.
Since N-type transistors are used, no power reduction is performed in the pit line drive circuit.

Conventionally, in order to reduce power consumption in a semiconductor memory, it has been proposed to use layered transistors for pit line selection drive as shown in FIG. A semiconductor memory as shown in FIG. 2, for example, is
No. 42029. In the semiconductor memory shown in FIG. 2, the memory cell has a word 41W and a bit line B (disposed at each intersection of 1+81, y)lNB.
opBt is connected to the emitter and rear end of the layered transistor Tm@*Tll via resistors R and sRl, respectively.

The output of the line drive circuit BDR' is connected to the PNP transistor Tm1)pTll. In the semiconductor memory shown in FIG. 2, the above-mentioned patent application No. 56-0420
As shown in No. 29, the power margin of the pit line selection circuit can be increased, and the power consumption of the pit line drive circuit can be reduced.

By the way, in the semiconductor memory shown in FIG. 2, the bit line selective current cannot be increased during writing;
Therefore, as a memory cell, as shown in FIG.
) type load transistor is used, there is a problem that the writing speed cannot be increased.

(4) Object of the Invention In view of the problems of the conventional semiconductor memory described above, the main object of the present invention is to change the selection of pit lines applied to a semiconductor memory having a memory cell having a PNPN (fish-shaped) tunnel transistor. Based on the idea of using a PNP transistor to perform this, the pit line drive is capable of increasing the bit line current during writing, speeding up the writing speed change, and expanding the power supply operating range of the pit line selection circuit. The purpose is to provide circuits.

(5) Structure of the Invention In the present invention, in a semiconductor memory in which a pit line to which a memory cell having a PNPN fish-shaped transistor is connected is selectively switched, a pit line current at the time of selection is written. A pit line driving circuit for a semiconductor memory is provided, which is characterized in that the pit line driving circuit is configured to drive the pit line at different times and at the time of reading.

(6) Examples of the invention 1 is a diagram illustrating a semiconductor memory as an embodiment of the present invention.

A line drive circuit is shown in FIG.

In the semiconductor memory shown in FIG. 3, the memory cell type is a multi-emitter transistor TC14C! and a PNP type load transistor TC1*T04.

Each first emitter of the multi-emitter transistor TC1eTC1 is connected to a pit line B, , B, and each second emitter,
are commonly connected to the sink current source XH via the holding line W-. The respective emitters of the PNP type load transistors TC1eTC4 are commonly connected to the word @W. The structure, operation, etc. of the memory cell MC shown in FIG.
-047428.

The bit line BOeB1 is connected to the terminals of the PNP transistor T4 via current limiting resistors R and R1. Transistor T win/eTll
The base KFi is connected to the output of the line drive circuit BDH, and the collector is connected to the power supply voltage V1. Biyt
[n.sBl and Fi, and a group transistor T1.
The emitter and ri of eTMl are connected, and the transistor T8.
The collector circuit of eTll is connected to the input of the sense amplifier circuit 8A. A control voltage V., vl is supplied to the pace of the transistor T-.eTll.

In the beat line drive circuit #2, the transistor TD.
The emitter of is connected to the output terminal via the diode D, and the output terminal is also connected to the power supply voltage Vz IKm via the resistor IL.
H* ) 5 NZ' Sfi T B @ O
4- is connected to one collector of the transistor pair TD1eTI1m. Transistor vs. T! 11. Tl
The emitter of l1 is connected to the current source rD@, and the collector is connected directly to the emitter of transistor TDm via a resistor R. Transistor vs. TDI #TDI
A bit selection signal vA is applied to one of the paces, and an intermediate voltage is applied to the other. The collector output of one of the transistors TDA and TDll is connected to the base of the transistor T'os. Transistor pair TD4tTDl
The emitter is connected to a current source IDI, and the collector is connected to a reference voltage via a resistor R4*RI. t'y//
A read/write control signal M is applied to the base of one TD6 of the /star pair, and an intermediate voltage is applied to the base of the other TD4.

In the bit line drive circuit BDR, bit lines B・e
When Bl is not selected, the selection signal is rLJ, the transistor TDO is turned on, and the output of the drive circuit BDH is rHJ. Next, the layered transistors Tl, Tl
l is turned off. Furthermore, when the bit line Be*Bl is selected, the selection signal is rHJ, and the transistor TDI
The base potential of I decreases, therefore, the potential of the transistor TD
・The emitter potential also decreases, and the bit line selection transistor T■. yTll turns on. In this case, the transistor T
The current flowing through lfl eTll increases as the output voltage of the drive circuit BDH becomes lower. By the way, in the drive circuit BDR of FIG. 3, the output level when the control signal W is rHJ, that is, when reading is higher than the output level when the control signal R/W is rLJ, that is, when writing. Therefore, the bit line current is conversely larger during writing than during reading.

As mentioned above, in the semiconductor memory shown in FIG. 3, it is possible to increase the bit line current during writing and speed up the writing operation by using the bit line drive circuit BDR in which bit lines are selected by layered transistors. can.

(7) Effects of the Invention According to the present invention, in a semiconductor memory in which a bit machine to which a memory cell having a PNP type load transistor is connected is selectively driven by a layered transistor, the bit line current during writing is reduced. By increasing the write speed, the writing speed can be increased, and the operating power supply range of the bit line selection circuit can be expanded.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a semiconductor memory using a memory cell having a conventional PNP type load transistor; Figure 2 is a circuit diagram of a semiconductor memory in which the bit line is driven by a conventional shaped transistor; FIG. 3 is a circuit diagram of a bit line drive circuit of a memory as an embodiment of the present invention.O (explanation of symbols) WDR: word line drive circuit, T: word line selection transistor, W, word line, W-: holding line, MC: memory cell, BO, B1: bit line, SA: sense ang circuit, WA: read/write control circuit, BDR', B
DR: Bit line drive circuit. Figure 1 Figure 2

Claims (1)

[Claims] In a semiconductor memory in which the selection and selection of a bit line to which a memory cell having a drive transistor of one conductivity type and a load transistor of the opposite conductivity type is connected is performed by a transistor of opposite conductivity type, the bit line current at the time of selection is A bit line drive circuit for a semiconductor memory, which is characterized by differentiating between input and output times.