JPH065080A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To rewrite all pieces of data in all memory cells in a short time by a method wherein all word lines are selection-operated by a drive control circuit, all bit lines are nonselection-operated and a bit line corresponding to a cell transistor which is to be set to an ON state is turned on by a current source circuit. CONSTITUTION:Individual word-line drive circuits 10 are simultaneously selection-operated forcibly by a drive control circuit 12 irrespectively of address data. In the same manner, individual bit-line drive circuits 11 are simultaneously nonselection-operated forcibly irrespectively of the address data. Individual bit-line pairs BL, the inverse of BL or transistors on the side of the inverse of BL are set to an ON state by a current source circuit 13 together with the control operation of the drive control circuit 12. Thereby, all pieces of data which have been written to all memory cells can be rewritten to preset arbitrary data in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Specifically, it relates to a static RAM.

In recent years, various types of static RAMs (hereinafter referred to as SRAMs) used for image processing and the like have been required in data writing and rewriting. Among them, there is a demand for a flash clear function for all the data stored in each static memory cell to be the same data (for example, clear). At this time, it is desired to perform flash clear at a higher speed.

[0003]

2. Description of the Related Art A conventional asynchronous RAM (hereinafter referred to as SRA)
The configuration of M) is shown in FIG. A large number of memory cells MC are connected between the pair of bit lines BL1, bar BL1, BL2, bar BL2 of the STRAM.
The corresponding word lines WL1 and WL2 and the hold line HL are connected to each. The memory cell MC is a PN composed of a pair of bipolar transistors T1 and T2 and a pair of multi-emitter transistors T3 and T4.
It is composed of a PN type saturated memory cell.

Word line selection circuits 1a and 1b are connected to the word lines WL1 and WL2, respectively. The word line selection circuits 1a and 1b operate based on a command signal from an X decoder driver circuit (not shown), The word lines WL1 and WL2 corresponding to the memory cell MC desired to be selected are selected.

In the word line selection circuits 1a and 1b, bipolar type NPN transistors T5 and T6 are connected in parallel, and the collectors of the transistors T5 and T6 are resistors R.
The power source Vcc is connected via the terminal 1. The emitters of the transistors T5 and T6 are connected to the constant current source Ia. A command signal from the X decoder driver circuit is input to the bases of the transistors T5 and T6. The collector of a bipolar NPN transistor T7 is connected to the power source Vcc, and the emitter of the transistor T7 has the transistors T5 and T5.
6 emitters. Therefore, the transistors T5 to T7 form an ECL circuit.
The reference voltage V is applied to the base of the transistor T7.
ref1 has been entered.

Further, the power source VCC is a bipolar type NP.
The collector of the N-transistor T8 is connected, and the base of the transistor T8 is connected to the collectors of the transistors T5 and T6. The emitter of the transistor T8 is connected to the word lines WL1 and WL2.

Each bit line BL1, bar BL1, BL
2, bit driver transistors Q1 and Q2 are connected to one end of the bar BL2. Each of the bit lines BL1,
The driver circuits 2 are connected to the bases of the bit driver transistors Q1 and Q2 of the bars BL1, BL2 and BL2, respectively. Each driver circuit 2 operates based on a command signal from a Y decoder driver circuit (not shown), and the bit line BL to be selected.
1, the bit driver transistors Q1 and Q2 corresponding to the bars BL1, BL2 and BL2 are turned on and the bit line B
L1, bar BL1, BL2, and bar BL2 are selected.

In the driver circuit 2, bipolar transistors T9 and T10 are connected in parallel, and the collectors of the transistors T9 and T10 are connected to a power source Vcc via resistors R2 and R3. Also, transistors T9 and T
The emitter of 10 is connected to the constant current power supply Ib. The collector of the bipolar NPN transistor T11 is connected between the resistors R2 and R3, and the transistor T1
The emitter of 1 is connected to the emitters of the transistors T9 and T10. Then, the transistor T11
The reference voltage Vref2 is input to the base of the. Therefore, the transistors T9 to T11 form an ECL circuit.

Further, the power source VCC is a bipolar type NP.
The collector of the N-transistor T12 is connected, and the base of the transistor T12 is connected to the collectors of the transistors T9 and T10. The base of a bipolar NPN transistor T13 is connected to the emitter of the transistor T12, and the collector of the transistor T13 is connected to the power source Vcc. The bases of the bit driver transistors Q1 and Q2 are connected to the emitter of the transistor T13.

The transistors T12 and T13
The constant current sources Ic and Id are connected to the emitter of.
A constant current source Ie is connected to the emitters of the bit driver transistors Q1 and Q2.

The bit lines BL1, bars BL1, BL
2, the emitters of transistors Q3 and Q4 are connected to bar BL2, respectively. These transistors Q3, Q
Reference numeral 4 controls the level of each bit line BL1, bar BL1, BL2, BL2 based on a control signal output from a read / write controller (not shown) based on a chip select signal, an inverted write enable signal and a data-in signal.

In the read operation, the read level (memory cell M
A control signal that is a voltage between C H level and L level) is output. In the write operation, the transistors Q3 and
In Q4, the transistor T3 of the memory cell MC
The transistor connected to the bit line on the side to be turned on of T4 is turned off, and on the contrary, the transistors T3 and T4 are turned on.
A control signal for turning on the transistor connected to the bit line on the off side is output.

In this STRAM, for example, when reading the data of the memory cell MC connected to the word line WL1 between the bit line BL1 and the bar BL1, the word line selection circuit 1a is instructed by the command signal from the X decoder / driver circuit.
Operates to select the word line WL1.

That is, the base potentials of the transistors T5 and T6 in the word line selection circuit 1a become lower than the reference voltage Vref1, and the transistors T5 and T6 are turned off. Then, the collectors of the transistors T5 and T6 are at H level.
Since it becomes the level, the base potential of the transistor T8 becomes H
The word line WL1 which becomes the level is selected. At this time,
The word line WL2 is not selected by the word line selection circuit 1b.

In addition, the driver circuit 2 operates according to a command signal from the Y decoder / driver circuit to operate the bit lines BL1,
The bar BL1 is selected. That is, the base potentials of the transistors T9 and T10 in the driver circuit 2 become lower than the reference voltage Vref2, and the transistors T9 and T10 are turned off. Then, the collectors of the transistors T9 and T10 become H level, and the base potential of the transistor T12 becomes H level. When the base potential of the transistor T12 becomes H level, the transistor T12
The base potential of 13 becomes H level, turning on the bit driver transistors Q1 and Q2. Therefore, the bit line BL1 and the bar BL1 are selected. At this time, the intermediate voltage between the H level and the L level of the memory cell MC is supplied to the bases of the transistors Q3 and Q4.

Therefore, the bit line BL1 of the memory cell MC
When the transistor T3 on the side is written in the ON state, the memory cell MC and the bit line B from the word line WL1.
The bit line BL1 becomes H level by the read current flowing through the transistor Q1 via L1. On the other hand, the bit line bar BL1 has a bit line bar B of the memory cell MC.
Since the transistor T4 on the L1 side is off, the transistor Q4 is turned on, and the read current flows from the transistor Q4 to the bit line bar BL1 through the transistor Q2.

At this time, the potential of the bit line BL1 is lower than the base potential of the H-bell of the transistor T3 of the memory cell MC by its base-emitter voltage, and conversely, the potential of the bit line bar BL1 is that of the transistor Q4. The potential is lower than the base potential at the intermediate potential by the base emitter voltage. As a result, the potential of the bit line BL1 becomes higher than the potential of the bit line bar BL1. That is, the bit line BL1 is at H level and the bit line bar BL1 is at L level. These signals are bit lines BL1, bar BL
It is output from 1.

On the other hand, for example, bit line BL1 and bar BL1
When data is written in the memory cell MC between them (in this case, the transistor T3 of the memory cell MC is turned on), the word line selection circuit 1a selects the memory cell MC based on the command signal from the X decoder driver circuit. The word line WL1 to be selected is selected and set to the H level. Also, Y
The driver circuit 2 turns on the bit driver transistors Q1 and Q2 based on a command signal from the decoder / driver circuit.

A control signal for turning off the transistor Q3 and turning on the transistor Q4 is output from a read / write controller (not shown). As a result, a current flows from the transistor T3 to the bit line BL1 and turns on the transistor T3. A current flows from the transistor Q4 to the bit line bar BL1.

[0020]

By the way, the above-mentioned SR
In AM, the word lines WL1 and WL2 and the bit lines BL1, bars BL1, BL2 and BL2 are selected one by one by the word line selection circuits 1a and 1b and the driver circuit 2. Data writing and reading are performed in the memory cells MC corresponding to the selected word lines WL1 and WL2 and bit lines BL1, bars BL1, BL2 and bars BL2. Therefore, when all the data written in all the memory cells MC are the same data (for example, clear), the selected word lines WL1, W
L2 level is not selected word line WL1, WL
Since it is higher than the level of 2, bit lines BL1, bars BL1, B from the unselected memory cells MC
It is difficult to draw a current to L2 and bar BL2. Therefore, it is impossible to write data to the unselected memory cells MC. Therefore, there is a problem that it takes a time corresponding to the number of all memory cells × write cycle time (ns).

The present invention has been made to solve the above problems, and an object of the present invention is to rewrite all data written in all memory cells into preset arbitrary data in a short time. It is to provide a semiconductor memory device capable of achieving the above.

[0022]

FIG. 1 is a diagram for explaining the principle of the present invention. Multiple word lines WL, multiple hold lines HL
A bipolar static memory cell MC is connected between the bit line pair BL and the plurality of bit lines BL. The word line drive circuit 1 is provided for each of the plurality of word lines WL.
0 is connected, and one word line WL is selected by the word line drive circuit 10. Also, the bit lines BL,
A bit line drive circuit 11 is connected to each bar BL, and one bit line pair BL, bar B is connected by this bit line drive circuit.
L is selected. And the selected word line WL
A specific bipolar static memory cell MC is selected on the basis of the bit line pair BL and bar BL.

Further, a drive control circuit 12 is connected to the word line drive circuit 10 and the bit line drive circuit 11, and the drive control circuit 12 forces the word line drive circuit 12 through the word line drive circuit 10 regardless of address data. The word line WL is selectively operated, and at the same time, all the bit lines BL and BL are forcibly deselected via the bit line drive circuit 11 regardless of the address data.

In addition to the control operation of the drive control circuit 12, the current source circuit 13 is provided on each bit line pair BL and bar BL, and is provided on each bit line BL and bar BL side of each bipolar static memory cell MC. The operation for turning on the cell transistor is performed.

[0025]

The drive control circuit 12 forcibly selects all the word lines WL regardless of the address data via the word line drive circuit 10 provided for each of the plurality of word lines WL. In addition, the drive circuit 12 forces all bit lines B through the bit line drive circuit 11 regardless of address data.
L and bar B are operated in a non-selective manner.

Along with the control operation of the drive control circuit 12, the current source circuit 13 causes the bit line B corresponding to the cell transistor to be turned on of each bipolar static memory cell MC provided for each bit line pair BL and bar BL.
L and BL are selected and all the cell transistors are turned on.

Therefore, all the bipolar static memory cells MC can be simultaneously rewritten with the same data, so that the data rewriting time can be shortened.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. Since the present embodiment has a new configuration requirement added to the conventional STRAM shown in FIG. 8, the same components are designated by the same reference numerals, and detailed description thereof will be omitted.

Each bit line BL1, bar BL1, BL2
A large number of memory cells MC are connected between the bars BL2, and each memory cell MC has a corresponding word line WL.
1, WL2 and hold line HL are connected. The memory cell MC includes a pair of bipolar transistors T
1, T2 and a pair of multi-emitter transistors T3 and T4, which is a PNPN saturated memory cell.

Transistors T3 and T4 in the memory cell MC provided between the bit line BL1 and the bar BL1.
Has a first emitter connected to the bit lines BL1 and BL1 and a second emitter connected to the hold line HL by being emitter-coupled to each other. Further, the third emitter of the transistor T3 is connected to the clear line CL1.

Similarly, the bit lines BL2 and bar BL2 are
Transistor T in memory cell MC provided between
The first emitters of T3 and T4 are bit line BL2 and bar BL
2 and the second emitters are emitter-coupled to each other and connected to the hold line HL. Further, the third emitter of the transistor T3 is a clear line C
It is connected to L2.

The emitters of the control transistors Q5 are connected to the emitters of the bit driver transistors Q1 connected to the bit lines BL1 and BL2, and the emitters of the transistors Q1 and Q5 are connected to the constant current source Ie. On the other hand, the emitters of the control transistors Q6 are connected to the emitters of the bit driver transistors Q2 connected to the bit lines BL1 and BL2, and the emitters of the transistors Q2 and Q6 are constant current sources Ie.
It is connected to the. The control transistors Q5 and Q
The collector of 6 is connected to the power supply Vcc.

A bipolar transistor T15 is connected in parallel with the transistors T5, T6 and T7 forming the word line driving circuits 1a and 1b. That is, the collector of the transistor T15 is connected to the power source Vcc, and the emitter is connected to the emitters of the transistors T5, T6 and T7.

Further, the emitters of the transistors Q7 and Q8 are connected to each of the hold lines HL to which the constant current source If is connected. And that transistor Q
The collectors of Q7 and Q7 are connected to the power supply Vcc.

The clear lines CL1 and CL2 are connected to the collectors of the transistors Q9 and Q10, and the emitters of the transistors Q9 and Q10 are connected to the constant current source Ig. The reference voltage Vref3 is input to the bases of the transistors Q9 and Q10. The emitter of the transistor Q9 is connected to the emitter of the transistor Q11, and the emitter of the transistor Q10 is connected to the emitter of the transistor Q12. still,
The collectors of the transistors Q11 and Q12 are connected to the power supply Vcc.

Then, each of the transistors Q5 to Q8,
The base potentials of Q11, Q12 and T15 are controlled by the drive control circuit 3. In other words, when it is desired that all the data written in the memory cells MC be the same (clear) or preset initial data, the drive control circuit 3 sets the base potentials of the transistors Q5 and Q6 to the bit driver transistor Q1. It is designed to be higher than the base potential of Q2. Further, the drive control circuit 3 raises the base potentials of the transistors Q7 and Q8,
The hold current flowing from the hold line HL to the constant current source If is suppressed (cut). Similarly, the drive control circuit 3 makes the base potential of the transistor T15 higher than the base potentials of the transistors T5 and T6. Further, the drive control circuit 3 includes a transistor Q1
The base potentials of 1 and Q12 are made lower than the base potentials of the transistors Q9 and Q10. That is, it is set to be lower than the reference voltage Vref3.

Next, the operation of the semiconductor memory device configured as described above will be described. When it is desired to rewrite all the memory cells MC to preset initial state data in a state where arbitrary data is written based on the transistors T1 to T4 of each memory cell MC,
The drive control circuit 3 includes transistors Q5 to Q8, Q11,
Control Q12 and transistor T15.

That is, the drive control circuit 3 includes the transistor T
The base potential of 15 is set higher than the base potentials of the transistors T5 and T6. Then, a large amount of current flows from the emitter of the transistor T15 to the constant current source Ia, and no current flows from the emitters of the transistors T5 and T6 to the constant current source Ia. Then, the collector potentials of the transistors T5 and T6 rise and the base potential of the transistor T8 becomes H level. (Higher than other base potentials) Therefore, by controlling the base potential of the transistor T15, all words are forcibly forced to the bases of the transistors T5 and T6 regardless of the control signal inputted from the X decoder driver circuit. Line WL is selected.

The drive control circuit 3 has a transistor Q.
The base potential of 5, 5 is set to the bit driver transistor Q
1, higher than the base potential of Q2. Then, a large amount of current flows from the emitters of the transistors Q5 and Q6 to the constant current source Ie, and no current flows from the emitters of the bit driver transistors Q1 and Q2. Therefore, the bit driver transistors Q1 and Q2 are turned off. Therefore, Y is added to the bases of the transistors T9 and T10 of the driver circuit 2.
Regardless of the control signal input from the decoder / driver circuit, all the bit lines BL1, BL1, BL1 are forcibly
2, the potential of the bar BL2 becomes non-selected.

Further, the drive control circuit 3 increases the base potentials of the transistors Q7 and Q8 to suppress the hold current flowing from the hold line HL to the constant current source If and flows from the emitters of the transistors Q7 and Q8 to the constant current source If. To do so.

In this state, the drive control circuit 3 changes the base potentials of the transistors Q11 and Q12 to the transistors Q9 and Q12.
The base potential of 10 is set lower than the reference voltage Vref3. Then, from the current flowing from the emitters of the transistors Q11 and Q12 to the constant current source Ig, the transistor Q9,
A larger amount of current flows from the emitter of Q10 to the constant current source Ig. Therefore, the potentials of the clear lines CL1 and CL2 become low.

Therefore, no current flows in the first and second emitters of the transistors T3 and T4 in the memory cell MC between the bit line BL1 and the bar BL1, and the transistor T4 is generated.
Is turned off. Then, since the current flows through the clear line CL1, the current flows from the third emitter of the transistor T3 to the clear line CL1, and the transistor T3 is turned on. Therefore, bit line BL1, bar BL
Transistor T3 in all memory cells MC between 1
Can be turned on and the transistor T4 can be turned off.

On the other hand, the first and the first transistors T3 and T4 in the memory cell MC between the bit line BL2 and bar BL2.
No current flows through the emitter of 2 and the transistor T3 is turned off. Then, since the current flows through the clear line CL2, a current flows through the clear line CL2 from the third emitter of the transistor T4, and the transistor T4
4 turns on. Therefore, it is possible to turn off the transistor T3 and turn on the transistor T4 in all the memory cells CM between the bit lines BL2 and BL2.

As a result, all the memory cells MC can be rewritten to the data in the preset initial state in an instant, and the data rewriting time can be shortened.

In the present embodiment, the drive control circuit 3 changes the base potential of the transistor T15 to the transistors T5 and T.
The transistor T8 is turned on by setting the potential higher than the base potential of the transistor T8, but as shown in FIG.
The base potential of 7, that is, the reference voltage Vref1 is further increased. With this configuration, when the drive control circuit 3 makes the base potential of the transistor T7, that is, the reference voltage Vref1 higher than the base potentials of the transistors T5 and T6,
The transistor T8 can be turned on regardless of whether the transistors T5 and T6 are turned on or off, and all the word lines W
L1 and WL2 can be selected. As a result, it is not necessary to provide the transistor T15, and the circuit can be simplified.

Further, the drive control circuit 3 uses the transistors Q5 and Q5.
Although the base potential of Q6 is made higher than the potentials of the transistors Q1 and Q2 to turn off the transistors Q1 and Q2, as shown in FIG. 4, the drive control circuit 3 causes the base potential of the transistors T9 and T10 to exceed the base potential of the transistor T9.
The base potential of 11, that is, the reference voltage Vref2 is further increased. With this configuration, the drive control circuit 3 causes the base potential of the transistor T7, that is, the reference voltage Vref2.
Is higher than the base potentials of the transistors T9 and T10, the transistors Q1 and Q2 can be turned off regardless of whether the transistors T9 and T10 are turned on or off, and all the bit lines BL1, BL1, BL2, and BL2 are unselected. Can be As a result, the transistor Q
Since it is not necessary to provide 5 and Q6, the circuit can be simplified.

Further, instead of the transistors Q9 and Q11 provided on the clear line CL1 and the transistors Q10 and Q12 provided on the clear line CL2, an N-channel type MOS transistor T13 can be used as shown in FIG. Is. When a current is applied to the clear lines CL1 and CL2, the drive control circuit 3 causes the N-channel MO
The gate of the S transistor T13 is set to the H level to turn on the N channel type MOS transistor T13. In this case, power consumption can be reduced as compared with the bipolar transistors Q9 to Q12.

FIG. 6 shows a semiconductor memory device constructed based on FIGS. 3 to 5. In addition, each memory cell MCa
The transistors T3 and T4 forming the MCd are provided with the first to third transistors provided in advance, and the clear lines CL1a, CL1b, CL2a and CL2b are provided.
Is provided. Then, in this case, the third emitter of the transistor T3 in the memory cell MCa is connected to the clear line CL1a, and the third emitter of the transistor T4 in the memory cell MCb is connected to the clear line CL2b.
Connected to. Further, the third emitter of the transistor T4 in the memory cell MCc is connected to the clear line CL1b, and the third emitter of the transistor T3 in the memory cell MCd is connected to the clear line CL1b.

Therefore, the word line WL, the bit line BL1,
The levels of the bars BL1, BL2, BL2 and the hold line HL are increased to clear the lines CL1a, CL1b, CL2.
If the levels of a and CL2b are lowered, the clear line CL1
The transistors T3 and T4 of the memory cells MCa to MCd connected to a, CL1b, CL2a and CL2b are turned on. As a result, any one of the third emitters of the transistors T3 and T4 in each of the memory cells MCa to MCd can be arbitrarily set to the clear lines CL1a, CL1b and CL2.
a and CL2b, the memory cells MCa to MCd
The initial state data of can be freely set.

Further, as shown in FIG. 7, the cell transistors T3 and T4 on the side where the bipolar static memory cell MC is turned on are multi-emitters having two emitters as in the conventional case. Then, one emitter is connected to the hold line HL and one emitter is connected to the bit driver transistors Q1 and Q2.
1, connect to bar BL2. Also, the bit lines BL1,
The clear lines CL1 and CL2 are connected to the bar BL2, and the MOS transistor Q13 is connected to the clear lines CL1 and CL2 as described above.

Then, the word line selection circuits 1a and 1b.
Selects the word lines WL1 and WL2, and the driver circuit 2 selects the bit driver transistors Q1 and Q2.
Is turned off. In this state, the MOS transistor Q
13 can be turned on to turn on the transistors T3 and T4 in the memory cell MC.

Therefore, the bit line B on the side to be turned on
By connecting the clear lines CL1 and CL2 to L1 and BL2, it is possible to use the bipolar transistors T3 and T4 which are multi-emitters having two emitters.

[0053]

As described in detail above, according to the present invention, there is an excellent effect that all the data written in all the memory cells can be rewritten to any preset data in a short time.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a semiconductor memory device according to the present invention.

FIG. 2 is an electric circuit diagram of a semiconductor memory device according to the present invention.

FIG. 3 is an electric circuit diagram showing another example of the semiconductor memory device of the present invention.

FIG. 4 is an electric circuit diagram showing another example of the semiconductor memory device of the present invention.

FIG. 5 is an electric circuit diagram showing another example of the semiconductor memory device of the present invention.

FIG. 6 is an electric circuit diagram showing another example of the semiconductor memory device of the present invention.

FIG. 7 is an electric circuit diagram showing another example of the semiconductor memory device of the present invention.

FIG. 8 is an electric circuit diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 10 word line drive circuit 11 bit line drive circuit 12 drive control circuit 13 constant current source circuit WL word line BL, bar BL bit line HL hold line MC memory cell

Claims (3)

[Claims] 1. A plurality of word lines (WL), a plurality of hold lines (HL) and a plurality of bit line pairs (BL, bar BL).
A bipolar static memory cell (MC) is connected between the two, and one of the word line drive circuits (10) provided for each word line (WL) is selected to select one word line (WL). In addition, one of the bit line driving circuits (11) provided for each bit line pair (BL, bar BL) is selected to select one bit line pair (BL, bar B).
L) is selected, and a specific bipolar static memory cell (MC) is selected based on the selected word line (WL) and bit line pair (BL, bar BL). A drive control circuit for forcibly selecting all the word line drive circuits (10) irrespective of address data and forcibly unselecting all the bit line drive circuits (11) irrespective of address data ( 12) and the cell transistor on the side of one bit line pair (BL or bar BL) of each bipolar static memory cell (MC) provided for each bit line pair (BL, bar BL) is connected to the drive control circuit (12). ), And a current source circuit (13) which is turned on together with the control operation of (1). 2. A bipolar static memory cell (M
The cell transistor on the side turned on in (C) is a multi-emitter transistor having three emitters,
One emitter on the bit line (BL or bar BL)
The two emitters are the flash clear line (CL
1, CL2), one emitter is a hold line (HL)
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to. 3. A bipolar static memory cell (M
The cell transistor on the side turned on in (C) is a multi-emitter transistor having two emitters,
One emitter is a hold line (HL), one emitter is a bit line (BL or bar BL) and a current source circuit (1
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the flash clear line (CL1, CL2) of 3).