JPH0628865A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accelerate the reading speed of cell data, in a static RAM in which a high speed operation is required. CONSTITUTION:This device is equipped with plural word lines WLWi, WLRi, WLWj, WLRj, plural pairs of bit lines WBL and WBLZ, and RBL and RBLZ, and plural cell MCi and MCj provided between each pertinent word line and each pertinent pair of bit lines. Each pair of bit lines is constituted of a pair of writing bit lines WBL and WBLZ, and a pair of reading bit lines RBL and RBLZ. Then, private writing access means and reading access means are provided between each pair of writing bit lines WBL and WBLZ and reading bit lines RBL and RBLZ, and each cell MCi and MCj.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, static RAM (SR
AM). In recent years, with the progress of semiconductor technology, speeding up of various devices has progressed, and the demand for speeding up in a semiconductor memory device has become stronger and stronger. Specifically, for example, S
In the RAM, the read speed of the cell data has a great influence on the overall operation speed, and therefore a further increase in the read operation is desired.

[0002]

2. Description of the Related Art In recent years, for example, in SRAMs, there has been a demand for further speeding up of cell data read operation. In particular, a technique for preventing read data and write data in the previous cycle (previous cycle) from affecting the data held in the cell is indispensable for speeding up the read operation.

FIG. 7 is a diagram showing a typical example of a cell structure in a conventional semiconductor memory device, showing the structure of an SRAM cell. Specifically, the cell MCa in FIG. 9A is composed of a pair of cross-connected N-type MOS transistors T1 and T2 and load resistors R1 and R2, and the cell MCb in FIG. 9B is cross-connected. And a pair of N-type MOS transistors T1 and T2 and P-type MOS transistors T3 and T4, and
The cell MCc in FIG. 1C is a pair of cross-connected N-type MOs.
S transistors T1 and T2 and TFT transistors T5 and T6
It is composed of.

As shown in FIGS. 6 (a) to 6 (c), the conventional S
The data holding nodes N1 and N2 of the RAM cells MCa to MCc are access transistors Tr controlled by the signal of the word line WL.
Connected to bit lines BL and BLZ via 1 and Tr2,
Writing (writing) and reading (reading) are performed by the bit lines BL and BLZ.

[0005]

As described above, in the conventional semiconductor memory device (SRAM), since the data holding node of the cell is connected to the bit line through the transistor, the write data and the read in the previous cycle are read. If data remains on the bit line, it may interfere with the cell data of the cycle and destroy the cell data. Therefore,
In the conventional semiconductor memory device, a bit line reset period is required so that write data or read data in the previous cycle does not remain in the bit line. However, the bit line reset period of the previous cycle data hinders high speed operation.

By the way, if the bit line reset is insufficient, there is a risk of destruction of cell data, so that a sufficient reset period is required. The ratio of the reset time is increasing. That is, in the semiconductor memory device, eliminating the reset period is a very effective means for realizing an ultra-high-speed cycle operation more than ever.

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the above-described conventional semiconductor memory device, and an object thereof is to increase the cell data read speed.

[0008]

According to the present invention, a plurality of word lines WL; WLW, WLR and a plurality of bit line pairs WBL, WBLZ, RB.
A semiconductor memory device comprising: L, RBLZ; and a plurality of cells MC; MCi, MCj provided between each word line and each bit line pair, wherein each bit line pair is for writing It is composed of a bit line pair WBL, WBLZ and a read bit line pair RBL, RBLZ, and a dedicated bit line pair WBL, WBLZ for each write bit line pair RBL, RBLZ and each cell MC for exclusive use. There is provided a semiconductor memory device characterized in that write access means Trw1, Trw2 and read access means Trr1, Trr2, Trr3, Trr4 are provided.

[0009]

According to the semiconductor memory device of the present invention, the bit line pair is independently constituted by the write bit line pair WBL, WBLZ and the read bit line pair RBL, RBLZ. Further, between the write bit line pair WBL, WBLZ and the read bit line pair RBL, RBLZ and the cells MC; MCi, MCj, dedicated write access means Trw1, Trw2 and read access means Trr1, Trr2, respectively. , Trr3, Trr4 are provided.

As a result, according to the semiconductor memory device of the present invention, the read data and the write data in the previous cycle do not affect the data held in the cell, and
By eliminating the reset period, the cell data read speed can be increased.

[0011]

Embodiments of the semiconductor memory device according to the present invention will be described below with reference to the drawings. 1 is a block circuit diagram showing an embodiment of a semiconductor memory device according to the present invention. In the figure, reference symbols MCi and MCj are SRAM memory cells (cells), WLWi and WLWj are write word lines, WLRi and WLRj are read word lines, WBL and WBLZ are write bit line pairs, and RBL, RBLZ indicates a read bit line pair.

As shown in FIG. 1, the cell MCi (MCj) has a write word line WLWi (WLWj), a read word line WLRi (WLRj), write bit lines WBL, WBLZ, and
The read bit line pair RBL, RBLZ is connected. The read bit line pair RBL, RBLZ is connected directly or via the gate transistors T3, T4 to the voltage amplification type sense amplifier SA1, and also directly or via the gate transistors T9, T10.
It is connected to the transistors T5, T6 (T7, T8) via.
Here, the transistors T3, T4, T7, T8, T9, T10 are N-type MO
S-transistor is shown, and transistors T5 and T6 are P-type MO
The S transistor is shown. Also, the transistors T5 and T
6 and T7 and T8 function as current sources. In this embodiment, the read bit line pair RB
When L and RBLZ are connected to the voltage amplification type sense amplifier SA1 via the gate transistors T3 and T4, for example, one sense amplifier SA1 can be shared by a plurality of read bit line pairs.

FIG. 2 is a circuit diagram showing a structural example of a cell in the semiconductor memory device of FIG. As shown in the figure,
The cell MC is connected to the write word line WLW and the write bit lines WBL and WBLZ via the two write transistors Trw1 and Trw2, and read through the four read transistors Trr1, Trr2, Trr3 and Trr4. Are connected to the read word line WLR and the read bit line pair RBL, RBLZ.

The gates of the write transistors Trw1 and Trw2 are connected to the write word line WLW, and the sources and drains are the write bit line pair WBL, WBLZ and the cell.
It is connected to two data holding nodes N1 and N2 of MC respectively. Further, the gates of the read transistors Trr1 and Trr2 are connected to the data holding nodes N1 and N2, the sources thereof are connected to the low potential power supply Vss, and the drains thereof are connected to the sources of the read transistors Trr3 and Trr4. Also,
The gates of the read transistors Trr3, Trr4 are connected to the read word line WLR, and the drains are connected to the read bit line pair RBL, RBLZ.

FIG. 3 is a circuit diagram showing a modification of FIG.
As shown in the figure, the cell MC includes a write word line WLW via two write transistors Trw1 and Trw2.
And a read word line WLR and a read bit line pair RB via two read transistors Trr1 and Trr2.
It is connected to L and RBLZ.

The gates of the write transistors Trw1 and Trw2 are connected to the write word line WLW, and the sources and drains are the write bit line pair WBL, WBLZ and the cell.
It is connected to two data holding nodes N1 and N2 of MC respectively. Further, the gates of the read transistors Trr1 and Trr2 are connected to the data holding nodes N1 and N2, the sources are connected to the word line WLR, and the drains are connected to the read bit line pair RBL, RBLZ).

As described with reference to FIGS. 2 and 3, according to the semiconductor memory device of this embodiment, the data holding nodes N1 and N2 of the cells are read bit line pair RBL, RB.
It is completely separated from LZ in terms of impedance and there is no interference from the bit line. As a result, ultra-high-speed reading is possible. Further, it becomes unnecessary to protect the data holding nodes N1 and N2 of the cell by the peripheral circuit, and the peripheral circuit can be simplified. And because the reset period is unnecessary,
The increase in the cycle can be eliminated. further,
By adding the logic of the write control signal to the write word line WLW, the influence of the write data in the previous cycle can be eliminated. Here, the cell MC is the one shown in FIG.
(a) configuration (MCa), but other configurations (MCb, MCc)
It goes without saying that it can be

FIG. 4 is a block circuit diagram showing another embodiment of the semiconductor memory device of the present invention, and FIG. 5 is a circuit diagram showing an example of a sense amplifier in the semiconductor memory device of FIG. As shown in FIG. 4, the voltage amplification type sense amplifier SA1 in FIG. 1 can be configured as a current amplification type sense amplifier SA2. This current amplification type sense amplifier SA2
Is a P-type MOS transistor T1 as shown in FIG.
01 to T106 and N-type MOS transistors T107 to T114. It is needless to say that an amplifier circuit having another circuit configuration can be applied to the semiconductor memory device of this embodiment.

FIG. 6 is a diagram showing another structural example of the cell in the semiconductor memory device of the present invention. In the cell structure example shown in the figure, the write word line WLWi and the read word line
WLRi is configured as a common word line WLi. In this way, write word line WLWi and read word line
If WLRi is used as the common word line WLi, it is slightly disadvantageous in terms of interference of signals supplied to the word line WL,
Since the number of word lines can be made to be a phenomenon, it is more advantageous than the one described above from the viewpoint of miniaturization and high integration.

[0020]

As described above in detail, according to the semiconductor memory device of the present invention, by providing the read bit line and the write bit line connected to the cell independently, the read data in the previous cycle and The write data does not affect the data held in the cell, and the reset period can be eliminated to increase the cell data read speed.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a structural example of a cell in the semiconductor memory device of FIG.

FIG. 3 is a circuit diagram showing a modified example of FIG.

FIG. 4 is a block circuit diagram showing another embodiment of the semiconductor memory device of the present invention.

5 is a circuit diagram showing an example of a sense amplifier in the semiconductor memory device of FIG.

FIG. 6 is a diagram showing another structural example of a cell in the semiconductor memory device of the present invention.

FIG. 7 is a diagram showing a typical example of a cell structure in a conventional semiconductor memory device.

[Explanation of symbols]

WL ... Word line WLW ... Write word line WLR ... Read word line WBL, WBLZ ... Write bit line pair RBL, RBLZ ... Read bit line pair MC ... Cell N1, N2 ... Data holding node Trw1, Trw2 ... Write Transistor (access means for writing) Trr1, Trr2, Trr3, Trr4… Transistor for reading (access means for reading) SA1… Voltage amplification type sense amplifier SA2… Current amplification type sense amplifier

Claims (7)

[Claims] 1. A plurality of word lines (WL; WLW, WLR), a plurality of bit line pairs (WBL, WBLZ, RBL, RBLZ), and each word line and each bit line pair. Multiple cells (MC; MC
i, MCj), wherein each bit line pair is a write bit line pair (WBL, WBLZ)
And a read bit line pair (RBL, RBLZ), and dedicated write access means (Trw1, Trw2) and read between the write bit line pair and read bit line pair and each cell. Access method (Trr1, Trr
2, Trr3, Trr4) is provided in the semiconductor memory device. 2. The write access means comprises two write transistors (Trw1, Trw2), the gate of each write transistor is connected to the word line (WL; WLW), and the source and drain are write Bit line pair (WBL, WBLZ) and two data holding nodes (N1, N2) of the cell (MC), respectively, and the read access means includes four read transistors (Trr1,
Trr2, Trr3, Trr4), the gates of the first and second read transistors (Trr1, Trr2) are connected to the data holding nodes (N1, N2), and the sources are connected to a low potential power source. The drains are connected to the sources of the third and fourth read transistors (Trr3, Trr4), and the gates of the third and fourth read transistors are connected to the word line (WL; WLR). The semiconductor memory device according to claim 1, wherein the drain is connected to the read bit line pair (RBL, RBLZ). 3. The write access means comprises two write transistors (Trw1, Trw2), the gate of each write transistor is connected to the word line (WL; WLW), and the source and drain are write Bit line pair (WBL, WBLZ) and two data holding nodes (N1, N2) of the cell (MC), respectively, and the read access means includes two read transistors (Trr1,
Trr2), and the two read transistors (Trr2)
The gate of (1, Trr2) is connected to the data holding node (N1, N2), the source is connected to the word line (WL; WLR), and the drain is connected to the read bit line pair (RBL, RBLZ). The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured as follows. 4. The plurality of word lines are composed of a write word line (WLW) and a read word line (WLR),
4. The semiconductor memory device according to claim 1, wherein the write access means and the read access means are independently controlled by signals of the write word line and the read word line. 5. The plurality of word lines are composed of a write word line (WLW) and a read word line (WLR),
4. The semiconductor memory device according to claim 1, wherein the write access means and the read access means are controlled simultaneously by signals of the write word line and the read word line. 6. The read bit line pair (RBL, RBLZ)
Is connected to the current source (T5, T6; T7, T8) directly or through the gate transistors (T9, T10), and the voltage amplification type sense amplifier (SA1) through the direct or gate transistors (T3, T4). ) Is connected to the semiconductor memory device according to claim 1. 7. The read bit line pair (RBL, RBLZ)
2. The semiconductor memory device according to claim 1, wherein is connected to the current amplification type sense amplifier (SA2) directly or through the gate transistors (T3, T4).