KR100436065B1 - Semiconductor memory device, especially detecting and amplifying voltage difference between a bit line and an inverted bit line - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to supply data stably and to reduce layout area by performing amplification using a minimum number of MOS transistors. CONSTITUTION: A memory cell(30) comprises NMOS transistors(NM31,NM32), and storage nodes(N31,N32) and NMOS transistors(NM33,NM34). An Y-decoder(40) comprises transmission gates(TRG41,TRG42). A precharge unit(50) precharges a bit line and an inverted bit line by an inverted equalization signal respectively. A sense amplifier unit(60) senses and amplifies a voltage difference between the bit line and the inverted bit line by a column selection signal.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of stably supplying data transmitted through bit lines and inverted bit lines.

In general, an SRAM cell consists of a memory flip-flop circuit and two switches. When a cell transistor is turned on by applying a pulse to a word line, data can be transferred between a pair of bit lines and a dummy line. Unlike the DRAM, as long as the power is applied, the flip-flop feedback effect allows the static data to be preserved without the refresh operation.

A column decoder of a general semiconductor memory device will be described with reference to FIG. 1.

Referring to FIG. 1, a column decoder of a general semiconductor memory device may include a precharge unit 10 for precharging the bit line BL and the inverting bit line / BL by the inversion equalization signal / EQ, respectively. Equalization means 20 for equalizing the bit line BL and the inverted bit line / BL by the inverted equalization signal / EQ, and is connected between the bit line BL and the inverted bit line / BL The memory cell 30 stores data by the word line enable signal WLEN and the Y-decoder 40 for writing and reading data of the memory cell 30 by the selection signal SL. Equipped.

The precharge unit 10 includes a first precharge means 11 for precharging the bit line BL and a second precharge means 12 for precharging the inverted bit line / BL. )

The first precharge means 11 is applied with an inverted equalization signal / EQ to a gate and is composed of a PMOS transistor PM11 connected between a power supply voltage and a bit line BL.

The second precharge means 12 is provided with a PMOS transistor PM12 connected between a power supply voltage and an inversion bit line / BL to which a inverted equalization signal / EQ is applied to a gate.

The equalizing means 20 is provided with a PMOS transistor PM21 connected between the bit line BL and the inverting bit line / BL to which the inverted equalization signal / EQ is applied to the gate.

In the memory cell 30, a word line enable signal WLEN is applied to a gate, a pass NMOS transistor NM31 connected between a bit line BL and a storage node N31, and a word line enable signal at a gate thereof. A WLEN is applied, a pass NMOS transistor NM32 connected between the inverting bit line / BL and the storage node N32, a gate is connected to the storage node N32, and a storage node N31 and ground. An NMOS transistor NM33 connected between the gate and the gate is connected to the storage node N31, and an NMOS transistor NM34 connected between the storage node N32 and ground.

The Y-decoder 40 is connected between the data bus line DBL and the bit line BL, the column select signal SL is applied to the N-type gate, and the inverted column select signal (/ SL is applied to the P-type gate. Is connected between the transmission gate TRG41 and the inversion data bus line / DBL and the inversion bit line / BL, and the column select signal SL is applied to the N-type gate, and the P-type gate And a transmission gate TRG42 to which an inverted column selection signal / SL is applied.

The operation of the conventional semiconductor memory device having the structure as described above is as follows.

When the inverted equalization signal / EQ in the low state is applied, the PMOS transistor PM11 of the first precharge means 11 is turned on to precharge the bit line BL, and also to the second precharge means. The PMOS transistor PM12 of (12) is turned on to precharge the inverting bit line / BL. At this time, the PMOS transistor PM21 of the equalizing means 20 is turned on to equalize the bit line BL and the inverting bit line / BL.

When the high word line enable signal WLEN is applied and the high column select signal SL is applied, the pass NMOS transistors NM31 and 32 of the memory cell 30 are turned on. In addition, the transmission gates TRG41 and TRG42 of the Y-decoder 40 are turned on, respectively.

Subsequently, data transferred through the data bus line DBL is sequentially stored in the storage node N31 through the transmission gate TRG41, the bit line BL, and the pass NMOS transistor NM31, and also the inverted data bus. Data transmitted through the line / DBL is sequentially stored in the storage node N32 through the transmission gate TRG42, the inverting bit line / BL, and the pass NMOS transistor NM32.

As such, data stored in the storage nodes N31 and N32 of the memory cell 30 are transferred to the bit line BL and the inverting bit line / BL, respectively, according to the read operation.

On the other hand, when the column selection signal SL in the low state is applied, the transmission gates TRG41 and TRG42 of the Y-decoder 40 are turned off, respectively, so that the write and resume operations of the memory cell 30 are stopped.

However, in the conventional semiconductor memory device as described above, the conventional Y-decoder using only transmission gates transmits data without loss, but the data level is distorted due to the negative parasitic effect in the highly integrated memory cell array. In particular, there was a difficulty in achieving a stable bit line level at high integration and low voltage operation.

Accordingly, the present invention is to solve the above problems, by detecting and amplifying the voltage difference between the bit line and the inverted bit line, it is possible to supply the data stably, and also to amplify using a minimum MOS transistor It is an object of the present invention to provide a semiconductor memory device capable of performing a function to reduce the area of the layout.

1 is a conventional semiconductor memory device.

2 is a semiconductor memory device according to an embodiment of the present invention.

3 is a characteristic diagram illustrating timing characteristics in the operation of FIG. 2;

4 is a semiconductor memory device according to another embodiment of the present invention.

Figure 5 is a characteristic diagram showing a comparison of the operation characteristics of the conventional SRAM and the SRAM according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30: memory cell 40: Y-decoder

50: precharge branch 60: detection amplifier

70: cross-coupled amplifier

According to an aspect of the present invention, a precharge unit for precharging the bit line and the inverted bit line by an inverted equalization signal, and is connected between the bit line and the inverted bit line, enables a word line. A semiconductor memory device comprising a plurality of memory cells for storing data by a signal and a Y-pass transistor for selecting the plurality of memory cells in response to a column selection signal, wherein the bit lines and And a sensing amplifier for sensing and amplifying the voltage difference between the inverting bit lines.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 5.

Referring to FIG. 2, the semiconductor memory device of the present invention, like FIG. 1, includes a memory cell including pass NMOS transistors NM31 and NM32, storage nodes N31 and N32, and NMOS transistors NM33 and NM34. 30 and a Y-decoder 40 composed of transmission gates TRG41 and TRG42.

Further, a precharge unit 50 for precharging the bit line BL and the inverting bit line / BL respectively by the inverted equalization signal / EQ, and the bit line by the column select signal SL And a sensing amplifier 60 for sensing and amplifying the voltage difference between the BL and the inverting bit line / BL.

The precharge unit 50 includes a first precharge means 51 for precharging the bit line BL and a second precharge means 52 for precharging the inverting bit line / BL. And equalization means 53 for equalizing the bit line BL and the inverted bit line / BL.

The first precharge means 51 is applied with an inverted equalization signal / EQ to a gate and is composed of a PMOS transistor PM51 connected between a power supply voltage and a bit line BL.

The second precharge means 52 is provided with an inverted equalization signal / EQ at its gate and includes a PMOS transistor PM52 connected between a power supply voltage and an inverted bit line / BL.

The equalizing means 53 is provided with a PMOS transistor PM53 connected between the bit line BL and the inverting bit line / BL, to which the inverted equalization signal / EQ is applied to the gate.

The sensing amplifier 60 detects and amplifies the output signal latch of the second CMOS inverter 62 and the voltage of the bit line BL, and the PMOS transistors PM61 to which voltages of the bit line BL are applied to the gates, respectively. And an inverting bit line at the gate for sensing and amplifying a voltage of the first signal inverter 61 and the inverting bit line / BL of the first CMOS inverter 61 and the NMOS transistor NM61, respectively. A second CMOS inverter 62 composed of a PMOS transistor PM62 and an NMOS transistor NM62 to which a voltage of (/ BL) is applied, and a first and second CMOS inverters by a column select signal SL applied to a gate. And an NMOS transistor NM63 for current source for driving (61, 62).

The operation of the semiconductor memory device of the present invention having the structure as described above is as follows.

Since the write and read operations of the present invention are the same as those described with reference to FIG. 1, the operations of the semiconductor memory device according to the exemplary embodiment of the present invention will be omitted.

When the inverted equalization signal / EQ in the low state is applied, the PMOS transistor PM51 of the first precharge means 51 is turned on to precharge the bit line BL, and also to the second precharge means. The PMOS transistor PM52 of 52 is turned on to precharge the inverting bit line / BL. At this time, the PMOS transistor PM53 of the equalizing means 53 is turned on to equalize the bit line BL and the inverting bit line / BL.

When the column selection signal SL in the high state is applied to store data in the storage nodes N31 and N32 of the memory cell 30 according to the write operation, and the current source NMOS transistor NM53 is turned on, According to the read operation, the first CMOS inverter 61 of the sense amplifier 60 detects the voltage of the storage node N31 transferred through the bit line BL, and senses the output signal of the second CMOS inverter 62. The second CMOS inverter 62 of the sense amplifier 60 detects the voltage of the storage node N32 transferred through the inversion bit line / BL and senses the voltage of the sense amplifier and the first CMOS inverter 61. Sense and amplify the output signal. At this time, the first and second CMOS inverters 61 and 62 output voltages at opposite levels.

Accordingly, the semiconductor memory device of the present invention senses the voltage difference between the bit line BL and the inverted bit line / BL during differential write and read operations, thereby differentially amplifies the data, thereby stably transferring data and writing speed. In addition, it is possible to improve the performance and to increase the access time by obtaining a large sensing gain during the read operation.

3 illustrates characteristics of timing according to time during the operation of FIG. 2.

In Fig. 3, (a1) is a timing characteristic of an address signal, (b1) is a timing characteristic of an inverted light enable signal, (c1) is a timing characteristic of an inverted output enable signal, and (d1) is a character of a word line enable signal. The timing characteristic (e1) is the timing characteristic of the column selection signal, (f1) is the timing characteristic of the inverted column selection signal, (g1) is the timing characteristic of the inverted equalization signal applied to the equalizing means 52, and (h1) is free. It is a timing characteristic of the inversion light signal applied to the charge unit 51.

A semiconductor memory device according to another exemplary embodiment of the present invention will be described with reference to FIG. 4.

Referring to FIG. 4, a sensing amplifier of a semiconductor memory device according to another exemplary embodiment of the present invention may include a differential amplifier in which a gate is commonly connected to an output terminal of an inverting bit line (/ BL) and a second NMOS transistor NM72 for differential amplification. A first NMOS transistor NM71, a differential amplification second NMOS transistor NM72 having a gate connected to the bit line BL, and an output terminal of the first NMOS transistor NM71 for differential amplification, and a column select signal ( SL is applied to the gate, and a cross-coupled sense amplifier (NM73) consisting of a current source NMOS transistor (NM73) connected between a common connected source of differential amplification first and second NMOS transistors (NM71, NM72) and ground. 70).

The operation of the semiconductor memory device of the present invention having the structure as described above is an operation for sensing and differentially amplifying the voltage difference between the bit line BL and the inverted bit line / BL. The same thing is omitted.

Accordingly, by implementing the sense amplifier 60 of the semiconductor memory device of the present invention as described above, the area of the layout can be reduced.

FIG. 5 shows a comparison of operating characteristics of a conventional semiconductor memory device and a semiconductor memory device of the present invention.

In Fig. 5, (a2) is an operating characteristic of the conventional bit line BL, (b2) is an operating characteristic of the conventional inverting bit line / BL, and (c2) is an operation of the bit line BL of the present invention. The characteristic (d2) is an operating characteristic of the inverting bit line / BL of the present invention.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the semiconductor memory device of the present invention senses the voltage difference between the bit line and the inverted bit line during write and read operations, and amplifies and differentially amplifies the data, thereby stably transferring data and improving the speed of the write. In addition, the large gain gain during read operation can lead to faster access times, and the use of a cross-coupled differential amplifier with only a small number of NMOS transistors reduces the area of the layout. .

Claims (2)

A plurality of memory cells connected between a bit line and an inverting bit line for precharging the bit line and the inverting bit line by an inverted equalization signal, and storing data by a word line enable signal; And a Y-pass transistor for selecting the plurality of memory cells in response to a column selection signal, the semiconductor memory device comprising: A sensing amplifier for sensing and amplifying a voltage difference between the bit line and the inverting bit line by the column selection signal A semiconductor memory device having a. The method of claim 1, wherein the sensing amplifier is A first CMOS inverter comprising a first PMOS transistor and a first NMOS transistor to which a voltage of the bit line is applied to a gate to sense an output signal latch of the second CMOS inverter and a voltage of the bit line; A second CMOS inverter comprising a second PMOS transistor and a second NMOS transistor to which a voltage of the inverting bit line is applied to a gate, respectively, for sensing and amplifying an output signal latch of the first CMOS inverter and a voltage of the inverting bit line; And Current source NMOS transistor for driving the first and second CMOS inverters by the column select signal applied to a gate Semiconductor memory device comprising a.

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