KR100291747B1 - Precharge equalizer circuit - Google Patents

Abstract

PURPOSE: A precharge equalizer circuit is provided to perform a precharge function and an equalization function by using an equalizing transistor and a sensing amplifier(sense-amp) active signal without using a precharge voltage source. CONSTITUTION: A precharge equalizer circuit includes a sense-amp(302) and a precharge part(Q38). The sense-amp(302) is driven by an active signal of two sense-amps, pulls up one between complement bit line and true bit lines to a power-supply voltage, and pulls down the other one to a base voltage. The precharge part(Q38) is connected to the bit lines, is driven by a precharge control signal, equalizes the true and complement bit lines, and precharges the true and complement bit lines with an equalized precharge voltage. The precharge control signal is enabled after an active signal of the sense-amp is enabled. A precharge time interval of the precharge is made by adding an activation time interval of the sense-amp and an activation time interval of the precharge part(Q38).

Description

Precharge Equalization Circuit

The present invention relates to a bit line equalization circuit for a memory device, and more particularly, to a bit line precharge equalization circuit capable of performing a precharge function without using a precharge voltage source.

In general, a bit line of a semiconductor memory device is precharged at a half voltage (Vcc / 2) in a standby mode, and operates in an operation mode, and then a bit line after data of a cell stored in the cell array is transferred to the bit line. Sensing and amplifying through a sense amplifier converts the bit lines to a constant supply voltage (Vcc) or ground voltage (Vss). After the data is output to the device, the device goes back to standby mode, and the bit lines that were in the supply voltage (Vcc) or ground voltage (Vss) state are again precharged to half voltage (Vcc / 2).

1 is a block diagram illustrating a conventional DRAM bit line precharge equalization circuit. Referring to FIG. 1, one memory cell 100 of a memory cell array is a switching device that connects a capacitor Cl to store information and the capacitor Cl to connect an external circuit with an external circuit. Pass transistor Q1. One end of the capacitor Cl is connected to ground. The pass transistor Q1 is connected to the authenticity and complementary bit lines BL and / BL. A plurality of memory cells are connected to the authentic and complementary bit lines BL and / BL and other plurality of bit lines. The sense amplifier 100 is connected to the true and complementary bit lines BL and / BL. The precharge voltage source 102, the power line 704, the precharge section 106 composed of two NMOS transistors Q2 and Q3, and the equalizer 108 composed of one NMOS transistor, The RAM precharge equalization circuit 10 is configured.

The precharge voltage source 102 generates a precharge voltage, that is, a half voltage (Vcc / 2) for precharging the bit line. The power line 104 transfers the precharge voltage Vcc / 2 generated by the precharge voltage source 102 to the NMOS transistors Q2 and Q3 of the precharge unit 106. The precharge unit 106 converts the authenticity and complementary bit lines BL and / BL from the power line 104 to the precharge voltage Vcc / 2 according to the bit line precharge control signal EQ. The equalizer 108 equalizes the authenticity and complementary bit lines BL and / BL. Capacitors C _BL and C _{/ BL} connected by dotted lines in FIG. 1 model parasitic capacitors of the true and complement bit lines BL and / BL, respectively.

FIG. 2 is a waveform diagram for explaining the operation of the precharge equalization circuit of FIG. The bit line precharge control signal EQ is commonly connected to the NMOS transistors Q2 and Q3 of the precharge unit 106 and the gate electrodes of the equalizing NMOS transistor 108, respectively. Q2 and Q3) and the operation of the equalizing NMOS transistor 108 are controlled. The sense amplifier activation signal SAE is connected to the sense amplifier 101 to control the activation of the sense amplifier 101. The first time interval T1 of the time points t0 to tl and the third time interval T3 of the time points t2 to t3 are sections in which the precharge control signal EQ has a low logic of the base voltage Vss, and the second of the time points t1 to t2. The time interval T2 is a section in which the precharge control signal EQ has a high logic of the power supply voltage Vcc.

The precharge voltage Vcc / 2 generated by the precharge voltage source 102 is supplied to the power line 104 and the precharge control signal EQ, which was the logic high of the base voltage Vss during the first time interval T1, is the time point tl. The transistors Q2 and Q3 and the equalization transistor 108 of the precharge unit 106 are turned on when the power supply voltage Vcc changes to a high logic. Accordingly, the authenticity and complementary bit lines BL and / BL are precharged to the voltage of half voltage (Vcc / 2) by the precharge unit 106 and the equalizer 108. On the other hand, the sense amplifier 101 does not operate because the sense amplifier activation signal SAE is a low logic of the base voltage Vss.

Conventional DRAM precharge equalization circuits use an output of a separate precharge voltage source to precharge a bit line of a memory cell array to a half voltage (Vcc / 2). Since the line must be precharged to half voltage (Vcc / 2), a significant static power consumption occurs because it consists of a voltage distribution type circuit that uses an equivalent resistor with the power supply voltage as an input.

Accordingly, an object of the present invention is to provide a bit line precharge equalization circuit capable of performing a precharge and equalization function by an equalizing transistor and a sense amplifier activation signal without using a precharge voltage source. have.

In order to achieve the above object, the present invention provides a sense amplifier which is operated by two sense amplifier enable signals to pull up one of the authentic and complementary bit lines to the supply voltage and the other down to the base voltage. 302); And the authenticity and precharge voltages equalized by equalizing the true and complement bit lines pulled up to a power supply voltage or pulled down to a base voltage by the sense amplifier and operated by a precharge control signal. A precharge equalization circuit is provided which includes a precharge unit Q38 for precharging complementary bit lines.

1 is a circuit diagram showing the configuration of a conventional DRAM bit line precharge equalization circuit.

FIG. 2 is a waveform diagram illustrating the operation of the bit line precharge equalization circuit shown in FIG.

3 is a circuit diagram illustrating a configuration of a bit line precharge equalization circuit according to an exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining the operation of the bit line precharge equalization circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

300: memory cell 302: sense amplifier

304: pull-up driving node line 306: pull-down driving node line

BL, / BL: bit line Q38: precharge part

3 illustrates a bit line precharge equalization circuit in accordance with an embodiment of the present invention. One memory cell 300 of the memory array is connected to a word line WL, and is connected to a capacitor C3l for storing information and the capacitor C3l to connect the capacitor C3l with an external circuit. And a pass transistor Q31 that serves. One end of the capacitor C3l is connected to ground. The pass transistor Q31 is connected to the authentic and complementary bit lines BL and / BL. A plurality of memory cells are connected to the authentic and complementary bit lines BL and / BL and other plurality of bit lines.

The sense amplifier 302 is connected to the authenticity and complementary bit lines BL and / BL and is loaded from the memory cell 300 on the authenticity and complementary bit lines BL and / BL. To detect and amplify. The pull-up driving node line 304 supplies a power supply voltage Vcc to the sense amplifier 302. The pull-up driving transistor Q36 is connected between the pull-up driving node line 304 and the power supply voltage source Vcc and operated by the pull-up driving activation signal SAP to supply the power supply voltage from the power supply voltage source. Vcc) is transmitted toward the sense amplifier 302 to control the operation of the sense amplifier 302. The pull-down driving node line 306 supplies the base voltage Vss to the sense amplifier 302. The pull-down drive transistor Q37 is connected between the pull-down drive node line 304 and the base voltage source Vss and operated by a pull-down drive activation signal SAN to generate a base voltage from the base voltage source. Vss) is transmitted to the sense amplifier 302 to control the operation of the sense amplifier 302. The pull-up drive activation signal SAP and the pull-down drive activation signal SAN constitute a sense amplifier activation signal.

The sense amplifier 302 has two PMOS transistors Q32 and Q33 that form a latch structure. The sources of the two PMOS transistors Q32 and Q33 are commonly connected to a pull-up driving node line 304, the gate of the PMOS transistor Q32 is connected to the complementary bit line / BL, The gate of the PMOS transistor Q33 is connected to the authentic bit line BL. The drain of the PMOS transistor Q32 is connected to an authentic bit line BL, and the drain of the PMOS transistor Q33 is connected to a complementary bit line / BL. The PMOS transistor Q32 is pull-up when the data of the complement from the memory cell 300 applied to its gate electrode via the complementary bit line / BL has a value of '0'. The first sense amplifier control signal having the power supply voltage Vcc provided by the driving transistor Q36 is transmitted toward the true bit line BL. At this time, the authentic data having a value of "1" on the authentic bit line BL is amplified to have a voltage value of the first sense amplifier control signal. On the contrary, when data having a value of "0 '" is supplied from the memory cell 300 to the authentic bit line BL, the PMOS transistor Q33 sends the first sense amplifier control signal to the complementary bit. Transmitting to the line / BL amplifies the complementary data having a value of "1" on the complementary bit line / BL to have the voltage value of the first sense amplifier control signal.

The CMOS latched sense amplifier 302 further includes two NMOS transistors Q34 and Q35 connected to form a latch structure between the authentic and complementary bit lines BL and / BL. The sources of the two NMOS transistors Q34 and Q35 are commonly connected to the pull-down drive node line 306, the gate of the NMOS transistor Q34 is connected to the complementary bit line / BL, The gate of the NMOS transistor Q35 is connected to an authentic bit line / BL. The drain of the NMOS transistor Q34 is connected to an authentic bit line BL, and the drain of the NMOS transistor Q35 is connected to a complementary bit line / BL. The authenticity and complementary bit lines BL and / BL are connected to the authenticity and complementary data bus lines DB and / DB, respectively.

When the complementary data from the memory cell 300 applied to its gate electrode via the complementary bit line / BL has a value of "1", the NMOS transistor Q34 has a base voltage Vss. The second sense amplifier control signal having the positive bit line (BL). At this time, the authenticity data having a value of "0" on the authenticity bit line BL is reduced to have a voltage value of the second sense amplifier control signal. On the contrary, when data having a value of "1" is supplied from the memory cell to the authentic bit line BL, the NMOS transistor Q35 is provided with the electromotive voltage Vss provided by the pull-down driving transistor Q37. Transmits a second sense amplifier control signal having a complementary bit line / BL toward the complementary bit line / BL so that the complementary data having a value of "0" on the complementary bit line / BL is the voltage of the second sense amplifier control signal. Decrease to have a value. The pairs of PMOS and NMOS transistors constituting the CMOS latch-type sense amplifier amplify the authenticity and complementary data such that the voltage difference of the authenticity and complementary data on the authenticity and complementary bit lines BL and / BL is large.

The precharge unit Q38 includes a MOS including a gate electrode to which a precharge control signal EQ is input, a connected drain electrode connected to the true bit line BL, and a source electrode connected to the complementary bit line / BL. Type transistors. The precharge unit Q38 is operated by a precharge control signal EQ and pulled up and pulled down to the power supply voltage and the base voltage by the sense amplifier 302, respectively. / BL) is precharged and equalized to the precharge voltage (Vcc / 2). Capacitors C _BL and C / _BL connected by dotted lines in FIG. 3 model parasitic capacitors of the true and complementary bit lines BL and / BL, respectively.

FIG. 4 is a waveform diagram for explaining the operation of the precharge equalization circuit shown in FIG. The pull-up driving activation signal SAP illustrated in FIG. 4A is connected to the gate electrode of the pull-up driving transistor Q36 to control the operation of the pull-up driving transistor Q36. The pull-down driving activation signal SAN shown in FIG. 4 (b) is connected to the gate electrode of the pull-down driving transistor Q37 to control the operation of the pull-down driving transistor Q37. The precharge control signal EQ shown in FIG. 4C is a signal for controlling the operation of the precharge transistor Q38.

The first time interval T1 of the time points tO to t1, the third time interval T3 of the time points t2 to t3, and the fourth time interval T4 of the time points t3 to t4 indicate that the pull-up driving activation signal SAP is a high logic of the power supply voltage Vcc. Is the time interval during which the pull-down drive activation signal SAN has a low logic of the base voltage Vss so that the sense amplifier 302 does not operate. On the contrary, in the second time interval T2 between the time points t1 to t2, the pull-up driving activation signal SAP is low logic of the base voltage Vss, and the pull-down driving activation signal SAN is high of the power supply voltage Vcc. It is the time interval in which the sense amplifier 302 operates with logic.

In the first time interval T1 at the time points tO to t1, the second time interval T2 at the time points t1 to t2, and the fourth time interval T4 at the points t3 to t4, the precharge control signal EQ is a low logic of the base voltage Vss. Is the time interval for keeping the transistor turned off. In contrast, the third time interval T3 at the time points t2 to t3 is a time interval in which the precharge control signal EQ has a high logic of the power supply voltage Vcc to keep the transistor turned on.

The fifth time interval T5 between the time points tO to t3 is the third time interval between the second time interval T2 between the time points tl to t2 when the sense amplifier 302 is activated and the time points t2 to t3 when the precharge transistor 038 operates. It is a time interval for precharging the bit lines BL and / BL of authenticity and complement by the precharge voltage Vcc / 2 by the precharge equalization circuit according to the present invention.

As shown in FIGS. 4A, 4B, and 3C, the precharge control signal EQ may include the sense amplifier activation signal and the pull-up driving activation signal SAP. And the pull-down drive activation signal SAN are preferably enabled.

As shown in FIGS. 4A and 4B, when a pull-up driving enable signal SAP having a low logic is applied to the gate electrode of the pull-up driving transistor Q36 at a time point t1. The pull-up driving transistor Q36 is turned on so that a power supply voltage from the power supply voltage source is transmitted to the sense amplifier 302 through the pull-up driving node line 304. At the same time, when a high logic pull-down drive activation signal (SAN) is applied to the gate electrode of the pull-down drive transistor 037, the pull-down drive transistor Q37 is turned on and the base from the base voltage source is turned on. Voltage is transmitted to the sense amplifier 302 via the pull-down drive node line 305. As a result, the authentic bit line BL is pulled up to the power supply voltage and the complementary bit line / BL is pulled down to the base voltage.

After the pull-up drive enable signal SAP and the pull-down drive enable signal SAP are deactivated by the high logic and the low logic, respectively, at the time point t2, the base voltage Vss of the base voltage Vss during the first time interval T1 and the second time interval T2 is When the precharge control signal EQ, which was a logic low, changes to a high logic of the power supply voltage Vcc, the transistor Q38 is turned on. Accordingly, due to the charge redistribution effect of the bit line capacitance of the authenticity and complementary bit lines BL and / BL itself, the authenticity and complementary bit lines BL and / BL may have a precharge voltage Vcc. / 2) precharged and equalized.

In other words, when the potential of the authentic bit line BL is the power supply voltage Vcc and the potential of the complementary bit line / BL is the base voltage Vss, and the bit line capacitances are C _BL and C _{/ BL} , respectively, the charge from the outside When the transistor Q38 is turned on in the absence of supply, the potential of the true bit line BL and the complementary bit line (BL) by the charge redistribution effect (Charge Sharing)

Veq = (C _BL Vcc + C _{/ BL} Vss) / (C _BL + C _{/ BL} )

Is equalized. Suppose C _BL = C _{/ BL} and Vss = 0

Veq = Vcc / 2. That is, the authentic bit line BL and the complementary bit line / BL are precharged with a precharge voltage of Veq = Vcc / 2.

In the above, the case where the potential of the true bit line BL is Vcc and the potential of the complementary bit line / BL is Vss has been described. In the reverse case, the equalization and precharge are performed through the same process. .

The precharge equalization circuit according to the present invention has a precharge and equalization function by utilizing two transistors for precharge and a sense amplifier by a sense amplifier activation signal without using a precharge voltage source. Do this.

Unlike the conventional circuit, the bit line precharge equalization circuit for DRAM according to the present invention enables the precharge operation of the bit line without using the precharge voltage source, so that static power consumption of the precharge voltage source, which has been a problem in the conventional DRAM design, is consumed. The elimination of the precharge power line and the precharge equalization transistors can reduce the design area resulting from them. In general, since the access speed of the DRAM is independent of the precharge operation time interval, the increased precharge time interval according to the present invention does not affect the access performance of the DRAM.

Although the present invention has been described in detail only with respect to the embodiments described above, it will be apparent to those skilled in the art that the present invention can be changed or modified within the spirit and scope of the present invention. It should be limited by the claims.

Claims (4)

A sense amplifier 302, operated by two sense amplifier activation signals, to pull up one of the true and complementary bit lines to the supply voltage and to pull down the other to the base voltage; And connected to the bit lines and operated by a precharge control signal to equalize the true and complement bit lines pulled up to a supply voltage or pulled down to a base voltage by the sense amplifier. And a precharge unit (Q38) for precharging the true and complement bit lines with an equalized precharge voltage. 2. The precharge equalization circuit of claim 1, wherein the precharge control signal is enabled after the sense amplifier activation signal is enabled. The precharge equalization circuit of claim 1, wherein a precharge time interval of the precharge equalization circuit is a sum of an activation time interval of the sense amplifier and an activation time interval of the precharge unit. The precharge unit Q38 is connected to a gate electrode to which the precharge control signal is input, a connected drain electrode connected to the true bit line BL, and the complementary bit line / BL. A precharge equalization circuit comprising a MOS transistor comprising a connected source electrode.

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