JP2527106B2 - Semiconductor memory circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit,
In particular, the present invention relates to a current switching type (CML) semiconductor memory circuit for holding potential information, which is formed of a bipolar transistor element and has a countermeasure against α rays.

[0002]

2. Description of the Related Art A conventional circuit configuration of this type is shown in FIG.
This memory circuit includes a pair of transistors 1 and 2 for writing data and a pair of transistors 3 and 4 for holding data.
And collector load resistances 7 of these transistors 1 to 4,
8 and one of the data writing transistors 1 and 2 and the data holding transistors 3 and 4 as an alternative to the current source 1
It includes a pair of current switching transistors 5 and 6 for controlling the supply of the current of 6 and a capacitor 9 for α-ray countermeasure.

A pair of transistors 1 for writing data
A pair of complementary write data (WD and inversion WD) is applied to both the second bases 30 and 31. Both bases 32 and 33 of a pair of transistors 5 and 6 for current switching
Is a complementary clock signal (indicated by CK and inverted CK)
Is applied, the data is written in the first half cycle of the clock signal (generally, the duty ratio of the clock signal is 50%), and the write data is held in the latter half cycle.

The emitters of both transistors 1 and 2 are commonly connected, and the collector of a current switching transistor 5 is connected to the common emitter connection point.

A pair of transistors 3, which holds the state (write data) of the collector voltage of both transistors 1, 2.
The collector outputs of the transistors 2 and 1 are applied to the bases of the transistors 4, respectively, and the collectors of the transistors 3 and 4 are connected to the collectors of the transistors 1 and 2, respectively. The emitters of both transistors 3 and 4 are commonly connected, and the collector of a current switching transistor 6 is connected to this common emitter connection point.

A constant current source 16 is provided at the emitters of the current switching transistors 5 and 6, and the transistors 5 and 6 are alternately turned on every half cycle of the clock signal, with respect to the common connection point of both emitters. As a result, the current of the constant current source 16 is supplied alternatively.

In such a structure, the data write operation will be described first. When data write is an input 3 2 of the pair of clock signals signal input 3 2, 3 3 becomes high level, the transistor 5 is turned on, the transistor 6 is turned off, thus the current of the constant current source 16 transistors 1 and 2 To the data writing circuit section, and not to the data holding circuit section by the transistors 3 and 4.

In this state, a pair of data writing inputs 3
0, 3 if the input 3 0 of 1 is set to the high level, the transistor 1 is turned on, the transistor 2 is turned off, thus the current flows only to the resistor 7, the collector of the transistor 1 becomes a low level. The collector of the other transistor 2 becomes high level.

[0009] If the input to the inverse 3 1 is at a high level, the transistor 2 is turned on, the transistor 1 from the off, the collector of the transistor 2 is at low level, the collector of the transistor 1 becomes high level. In this way, the data write operation is performed.

To hold this write data, the input 33 of the pair of clock signal inputs 3 2 and 3 3 is set to the high level, and the transistor 6 is turned on. Therefore,
The pair of data holding transistors 3 and 4 are activated. In this state, if the collector of the transistor 1 is at the low level and the collector of the transistor 2 is at the high level, the positive feedback effect between the bases and collectors of the transistors 3 and 4 causes the transistor 3 to rapidly turn on and the transistor 4 to rapidly. Since this state is maintained after it is turned off, the collector of the transistor 1 is maintained at the low level and the collector of the transistor 2 is maintained at the high level.
Write data can be latched.

In such a storage circuit, when α-rays enter from the outside in the data holding state, the stored data may be inverted due to the influence of the α-rays to cause data destruction.

Therefore, as a countermeasure against α-rays, as shown in FIG. 5, a capacitor 9 is connected between the collectors of the transistors 1 and 2, and this capacitor 9 absorbs noise generation due to incidence of α-rays on the transistor. Therefore, a method of preventing the inversion of the stored data is adopted.

Further, in order to reinforce this countermeasure against α rays, the circuit configuration of FIG. 6 is adopted. 6, the same parts as those in FIG. 5 are denoted by the same reference numerals. In the circuit of FIG. 6, a first emitter follower circuit including a transistor 10 and a resistor 14 is additionally connected between the collector of the transistor 1 and the base of the transistor 4 (one end of the capacitor 9), and the collector of the transistor 2 is connected. And a base of the transistor 3 (the other end of the capacitor 9), a second emitter follower circuit including a transistor 11 and a resistor 15 is additionally connected.

That is, the collector output of the transistor 1 is used as the base input of the emitter follower transistor 10, the emitter follower output is supplied to the base of the transistor 4 and one end of the capacitor 9, and the collector output of the transistor 2 is used as the emitter follower transistor. 11
And the emitter follower output is supplied to the base of the transistor 3 and the other end of the capacitor. still,
The emitter resistors 14 and 1 of the emitter followers 10 and 11
5 is connected to the voltage source V1 and the other structure is the same as that of FIG.

Now, it is assumed that the resistors 14 and 15 are set large and the current of the emitter follower circuit is selected to be smaller than the current of the normal emitter follower circuit.

If the collector of the transistor 1 is maintained at the high level and the collector of the transistor 1 is pulled to the low level by the α-ray, the transistor 10 is operated.
Since the emitter follower current of the emitter follower circuit is selected to be extremely small, the low level transmission by the α ray to the emitter follower output becomes slow. Since the collector of the other transistor 2 does not change at all, and therefore the base of the transistor 3 does not change, the instantaneous collector potential change of the transistor 1 due to α-ray is delayed by the emitter follower circuit and the capacitance 9 causes. By being absorbed, more complete α-ray countermeasures become possible.

[0017]

As described above, a small current emitter follower circuit is provided between the collector of the data writing transistor and the base of the data holding transistor to delay the noise transmission response due to α-ray incidence. As a result, the memory circuit is strong against α rays.

However, since the data transmission response speed to each transistor at the time of data retention becomes slower by that much, the operation cycle of the entire device cannot be shortened in the case of performing a normal access operation, and high speed is achieved. It is a factor that hinders the operation.

Therefore, the present invention has been made to solve the above-mentioned drawbacks of the conventional ones, and the purpose thereof is to enable high-speed operation without lowering the operation speed even if countermeasures against α rays are taken. Another semiconductor memory circuit.

[0020]

In a semiconductor memory circuit according to the present invention, a pair of first and second data write circuits are provided in which a pair of data write differential inputs are supplied to their bases and their emitters are commonly connected. A second transistor; a pair of third and fourth data holding transistors whose collectors are respectively connected to the collectors of the first and second transistors and whose emitters are commonly connected;
The collector of the first transistor is used as an input, and the fourth transistor is input.
First emitter follower means whose output is supplied to the base of the transistor, and second emitter follower means whose input is supplied to the collector of the second transistor and whose output is supplied to the base of the third transistor. Set the data writing timing and the data holding timing with the capacitor for absorbing α-rays that is provided between the emitter follower outputs.
Current switching control is selectively performed for the common emitter connection point of the pair of data writing transistors and the common emitter connection point of the pair of data holding transistors in accordance with the pair of timing control differential inputs respectively defined. a pair of current switching transistors forming a, a semiconductor memory circuit having a current source for supplying the current, the data
Data writing timing and data holding timing
The pair of timing control differential inputs are
The output currents of the first and second emitter follower means when writing data,
It is characterized in that it has a current control means for controlling to a greater extent than when data is held.

[0021]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and the same portions as those in FIG. 6 are designated by the same reference numerals. 6 is different from the conventional example in that the emitters C and D of the emitter follower transistors 10 and 11 (both ends of the α-ray absorbing capacitor).
And another current control transistor 12, 13 is inserted between each emitter resistance 14, 15.

That is, the emitter of the emitter follower transistor 10 is connected to the collector of the transistor 12, and the emitter of the transistor 12 is connected to the power source V1 via the resistor 14. Both transistors 10 and 12 are connected in series. To be done. The emitter of the emitter follower transistor 11 is connected to the collector of the transistor 13, and the emitter of the transistor 13 is connected to the power source V1 via the resistor 15.
Both transistors 11 and 13 are connected in series. And these two transistors 12, 1
The bases of 3 are both controlled by the base input 32 of the transistor 5.

The other circuit configuration is the same as that of FIG. 6 and its explanation is omitted.

At the time of data write, the base input 32 of the transistor 5 becomes high level, the circuits for writing data of the transistors 1 and 2 are activated, and the pair of complementary write data at the base inputs 30 and 31 of the transistors 1 and 2 are activated. Data is written in accordance with. At this time, the bases of the current control transistors 12 and 13 are
Since the high level of the base input 30 of the transistor 5 is applied, each output current of the transistors 10 and 11 of the emitter follower circuit increases at the time of data writing,
The response speed of the emitter follower circuit to the write data becomes high, and the outputs C and D of these emitter follower circuits are output during the write state (while the clock signal CK of the base input 30 of the transistor 5 is at the high level). The potential of can be sufficiently tracked and changed according to the write data, and thus the potentials of the collectors C and D of the data write transistors 1 and 2.

FIG. 2 is an operation waveform diagram of each part of the circuit of FIG. It can be seen that the emitter follower outputs C and D are also changing in accordance with the potential change of. In the figure, I indicates the output current of the emitter follower circuit.

In the data holding state, the base 33 of the transistor 6 becomes high level, so that the transistors 3, 3
The data holding circuit 4 is activated. This period is a period in which the clock input signal CK is at the low level (the latter half cycle of one cycle), and the current control transistor 12,
Since the base input of 13 is at low level, the output current I of the emitter follower circuit becomes small. Therefore, the response speed of the emitter follower circuit to the data change becomes small, and even if the α-ray is incident on the transistor 1 or 2 whose collector is at the highest potential (high level), the emitter follower circuit has a slow response to hold the data. The data change due to the α ray is not transmitted to the transistor 4 or 3,
The line measures will be sufficient.

As shown by the waveforms A'to D'and I'in the time chart of FIG. 2, the current I'of the emitter follower transistors 10 and 11 is always small and constant in the conventional circuit of FIG. Since it is set to, the response of the emitter follower circuit becomes slow even during data write. Therefore, in the circuit of the present invention shown in FIG. 1, one cycle can be shortened to 1 ns. However, if one cycle is similarly set to 1 ns in the circuit shown in FIG. The operation as is impossible.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. 1 and 6 are designated by the same reference numerals. Conventional transistor 10 and resistor 1 shown in FIG.
In the emitter follower circuit consisting of 4 (transistor 11 and resistor 15), transistor 10 (transistor 1
If 1) is turned from OFF to ON, since the emitter load capacity Ri by its ON transistor <br/> is charged, but the rise time of the emitter output is fast, the transistor 10 (transistor 11) from on the contrary When it is off, the discharge of the emitter load capacitance is performed through the resistor 14 (resistor 15), so the fall time of the emitter output is generally delayed.

Therefore, in the second embodiment of FIG. 3, instead of the emitter resistors 14 and 15, the active pull-down (APD) by the transistors 12 and 13 is used.
A circuit is provided to accelerate the falling response of the emitter outputs C and D.

In this case, the collector output A of the transistor 1 is applied to the base of the transistor 13 of the APD circuit via the coupling capacitor 23, and the collector output B of the transistor 2 is applied to the base of the APD circuit transistor 12 via the coupling capacitor 24. By applying to the base, the complementary changes of both collectors A and B at the time of data write are detected.
The electric charges of the load capacitances of the outputs C and D of the emitter follower transistors 10 and 11 which are transmitted to the bases of the transistors 12 and 13 are rapidly discharged by the transistors 12 and 13, respectively. .

Resistors 14 and 15 are inserted in the emitters of the APD transistors 12 and 13 as in the conventional case. Further, transistors 17 and 18 are provided to generate a base bias of the APD transistor 12, and transistors 19 and 20 are provided for the base bias of the APD transistor 13 as well. The collectors of the transistors 17 and 19 are connected to the highest circuit potential (ground in this example), and a constant base potential VB is applied to the bases.

These transistors 17 and 19 are respectively connected in series with diode-connected transistors 18 and 20, and the base bias of the transistor 12 from the series connection point of the transistors 17 and 18 is connected in series with the transistors 19 and 20. The base bias of the transistor 13 is derived from each point. It should be noted that these base bias circuits are merely examples.
It is not limited to this.

In such a configuration, the transistor 10,
Since the emitter follower current of the emitter follower circuit 11 is set to a small value by selecting the resistors 14 and 15, the response operation is usually slow. As described above, the emitter follower circuit basically has a long output falling operation time and a poor response speed. However, by providing the APD circuit with the transistors 12 and 13, the points A and B due to the change of the write data WD. The potential change at the point is transmitted to the current control transistors 12 and 13, and the emitter follower current transiently increases. As a result, the emitter follower outputs C and D change rapidly, and high-speed operation becomes possible as in the example of FIG.

When the data is held, A
Even if the holding level of the point changes from the high level to the low level instantaneously, the base bias level of the current control transistor 12 does not change at all, so the emitter follower current of the emitter follower transistor 10 does not change and is small. There is. The level change at the point A at this time changes the base bias of the current control transistor 13 of the APD circuit, but since it is transient and the level at the point B does not change, the base bias of the transistor 12 does not change. Therefore, the level at point A returns from the low level to the high level and returns to the original state.

In the circuit of FIG. 3, it is necessary to generate the base bias of the transistors 17 and 19 in the base bias generation circuit of the current control transistors 12 and 13 of the APD circuit by using the power supply VB. Separately, this power supply VB is required, which is not a good idea.

Then, the third embodiment circuit shown in FIG. 4 is obtained. 4, the same parts as those in FIGS. 1 and 3 are designated by the same reference numerals. In this example, a transistor 25 and a resistor 2 are provided at the base of the current control transistor 12 of the APD circuit.
The potential at the point B is supplied via the emitter follower circuit composed of 7 and the potential at the point A is supplied to the transistor 13 via the emitter follower circuit composed of the transistor 26 and the resistor 28. The other structure is the same as that of FIG.

Also in this example, the potential changes at the points A and B during data write are transmitted to the bases of the transistors 13 and 12 of the APD circuit, and the emitter follower transistors 10 and 11 are transmitted.
The output current of the emitter is temporarily controlled to be large, and the emitter follower currents of the emitter follower transistors 10 and 11 are made small at the time of holding the data, and the response speed thereof is slow.

[0039]

As described above, according to the present invention, when an emitter follower is provided in a memory circuit of a semiconductor device as a countermeasure against α rays, the emitter follower circuit controls the emitter follower current to write data. The response speed of the emitter follower circuit is changed by changing the emitter follower current depending on the time and the data holding state, increasing the current when writing data and decreasing the current when holding data. This has the effect of increasing the speed and reducing the influence of α rays during data retention.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is an operation time chart of the circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a circuit diagram of another embodiment of the present invention.

FIG. 5 is a diagram showing an example of a conventional semiconductor memory circuit.

FIG. 6 is a diagram showing another example of a conventional semiconductor memory circuit.

[Explanation of symbols]

 1, 2 Data writing transistor 3, 4 Data holding transistor 5, 6 Current switching transistor 7, 8 Collector resistance 9 α ray absorption capacitor 10, 11 Emitter follower transistor 12, 13 Current control transistor 14, 15 Emitter resistance 16 constant current source 17 to 20 bias transistor 23, 24 coupling capacitor 30, 31 write data input 32, 33 control signal input

Claims (2)

(57) [Claims] 1. A collector of the pair of first and second transistors and, wherein each of the collector first and second transistors data write differential input emitter together supplied to each other base commonly connected Each connected to the emitter
Third and fourth transistors, which are commonly connected to each other ,
The collector of the first transistor is used as an input, and the fourth transistor is input.
A first emitter follower transistor output transistor to the base of Ru is supplied, the second collector of the transistor as an input the third second emitter follower base to the output of the transistor is Ru is supplied transistor
And data, between the bases of said third and fourth transistors
The connected capacitor and the first capacitor when writing data
And current to the common emitter connection point of the second transistor
When the data is supplied and the data is retained, the third and fourth transactions are performed.
Means for supplying current to the common emitter connection point of the transistor,
First and second ends each having one end connected to a power line
A resistor, the other end of the first resistor and the third transistor
A fifth transistor connected between the bases of the
Between the other end of the second resistor and the base of the fourth transistor
And a sixth transistor connected to the fifth transistor, the fifth transistor and the sixth transistor being connected at the time of writing the data.
Data becomes conductive, and when the data is held, the fifth and sixth data are stored.
The semiconductor memory circuit is characterized in that the transistor is non-conductive . 2. A pair of differential inputs for writing data are mutually different.
Source and the emitters are commonly connected
A second transistor and each collector having the first and
An emitter connected to the collector of the second transistor, respectively
Third and fourth transistors, which are commonly connected to each other,
The collector of the first transistor is used as an input, and the fourth transistor is input.
First EMI whose output is supplied to the base of the transistor
Tta-follower transistor and the second transistor
The input is the collector of the base of the third transistor
Second emitter-follower transistor, whose output is supplied to
And the bases of the third and fourth transistors
The connected capacitor and the first capacitor when writing data
And current to the common emitter connection point of the second transistor
When the data is supplied and the data is retained, the third and fourth transactions are performed.
Means for supplying current to the common emitter connection point of the transistor,
First and second ends each having one end connected to a power line
A resistor, the other end of the first resistor and the third transistor
A fifth transistor connected between the bases of the
Between the other end of the second resistor and the base of the fourth transistor
A sixth transistor connected to the first transistor and the first transistor.
Using the collector output of the transistor as the input, the sixth transistor
The first active probe that supplies the output signal to the base of the star
Circuit and the collector output of the second transistor
Input force and output to the base of the 5th transistor
With a second active pull-down circuit that supplies a signal
And the collector output of said first transistor is active les
If it is a bell, the first active pull-down
The circuit makes the sixth transistor conductive and the collector output of the second transistor is active.
If it is a bell, the second active pull-down
A circuit is characterized in that said fifth transistor is conductive
And semiconductor memory circuit.