JPH05258563A - Dynamic type semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a DRAM which can obtain high yield rate without sacrificing high speed performance. CONSTITUTION:This device is constituted by a core circuit a memory cell array 1, a row decoder 2, a bit line sense amplifier 3, a column decoder 4, an address buffer 5, an I/O sense amplifier 6 set between the amplifier 3 and input and output data lines and buffer 7, and a timing control circuit 8 which drives each part of the core circuit. Also, a ratio of delay time of a transfer gate transistor of a memory cell to delay time of a delay circuit 10 which sets activating timing of the bit line sense amplifier is set so as to be more than a ratio of delay time of each part of other core circuit to delay time of a delay circuit which generates a driving signal corresponding this.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a dynamic semiconductor memory device (DRAM).

[0002]

2. Description of the Related Art A DRAM circuit has one transistor / 1
A memory cell array in which dynamic memory cells of capacitors are arranged, a decoder for selecting data in the memory cell array, an address buffer for amplifying an external address for selecting the decoder, and a bit line sense amplifier for amplifying data in the memory cell array. , And a core circuit including an input / output sense amplifier and an input / output buffer provided between the bit line sense amplifier and the input / output pin, and a timing control circuit for controlling the timing for driving each part of the core circuit.

Since the delay time of each part of the DRAM core circuit fluctuates due to fluctuations (variations) in the threshold voltage of the transistors forming the circuit in practice, in order to prevent malfunctions, the delay time of each part of the core circuit corresponds to the delay time. It is necessary to set the delay time of the drive circuit of each unit that generates the drive signal of the next core circuit longer than that. How long it is depends on the balance between high-speed performance and reliability. For example 1991
In the 64Mbit DRAM announced at the international conference in
As shown in FIG. 4A, the delay time of the delay circuit for driving the next core circuit is uniformly increased by 10% with respect to the delay time of each part of the core circuit.

When the capacity of a DRAM is increased to 1 G level, the transistor becomes extremely fine, and especially the transfer gate transistor of the memory cell array becomes as small as a channel length of about 0.2 μm. In the large capacity DRAM using such a fine transistor, (1)
The fluctuation of the threshold value of the transistor becomes large due to the short channel effect and the fluctuation of the impurity distribution, and (2) since the power supply voltage drops from 3.3V to 1.5V, the change rate of the delay time with respect to the threshold change is large. Become. as a result,
The fluctuation of the delay time of a certain core circuit receives this and exceeds the delay time of the delay circuit for driving the next core circuit, resulting in a defect. This defect can be remedied by uniformly delaying the delay time of the delay circuit that sets the operation timing of each part of the core circuit, but doing so sacrifices high-speed performance.

For example, the delay time of each delay circuit for driving each core circuit in a 1 Gbit DRAM is set to 64 Mbit DRA.
From 10% increase in the case of M, 100% as shown in Fig. 4 (b)
If the percentage is increased, the yield is improved, but the access time is delayed from 33 nsec in the case of the 64 Mbit DRAM to 60 nsec, which is about twice as long.

[0006]

As described above, the conventional D
In the RAM, there is a problem that when the capacity is increased, the fluctuation of the delay time of the core circuit becomes large, and it is difficult to obtain a high yield without sacrificing the high speed performance. The present invention solves such a problem, and a high yield can be obtained without sacrificing high-speed performance.
The purpose is to provide AM.

[0007]

A DRAM according to the present invention
Is a memory cell array in which dynamic memory cells are arranged, a decoder for selecting data in the memory cell array, an address buffer for amplifying an external address for selecting the decoder, and a bit line sense amplifier for amplifying data in the memory cell array. , And a core circuit including an input / output sense amplifier and an input / output buffer provided between the bit line sense amplifier and the input / output pin,
A timing control circuit that controls the timing for driving the core circuit, and a delay in the timing control circuit that generates the next drive signal corresponding to the delay time of each part of the core circuit and the delay time of each part of the core circuit. It is characterized in that the ratio to the delay time of the circuit is set according to the magnitude of the fluctuation of the threshold value of the transistor in each part of the core circuit.

[0008]

According to the present invention, for a core circuit in which fluctuations in delay time increase due to an increase in capacity, particularly for a transfer gate portion of a memory cell array, the delay time of the corresponding delay circuit is lengthened so that a DRAM failure occurs. Can be prevented and the yield can be maintained or improved. Also, for core circuits with small fluctuations in delay time, the delay time of the corresponding delay circuit is not unnecessarily increased.
The high speed performance of the DRAM is hardly sacrificed.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall structure of a 1 Gbit DRAM according to an embodiment of the present invention. As shown, the DRAM has a memory cell array 1 in which dynamic memory cells of 1 transistor / 1 capacitor are arranged, a row decoder 2 for selecting a word line, a bit line sense amplifier 3 for detecting bit line data, and a bit line selection. A core circuit composed of a column decoder 4, an address buffer 5 for fetching and amplifying an external address, an I / O sense amplifier 6 and an I / O buffer 7 provided between a bit line sense amplifier and an input / output data line, and these. The timing control circuit 8 generates a timing signal for driving each part of the core circuit.

FIG. 2 shows the respective delay circuits 10 in the timing control circuit for arranging the respective parts of the core circuit at the time of read access in the order of operation and determining the core circuits and their driving timing.
The relationship (10 ₁ to 10 ₆ ) is shown.

FIG. 3 shows the relationship between the delay time of each part of the core circuit at the time of read access and the delay time of the delay circuit 10 corresponding to the same, and is shown in association with FIG. In this embodiment, the delay time of the transfer gate transistor of the memory cell is 3.6 nsec, while the delay time of the delay circuit 10 ₃ which determines the timing of activating the bit line sense amplifier in response to the operation of the transfer gate transistor. τ ₃ is twice as long as 3.6 nsec (1
00%), and the remaining delay circuits 10 ₁ , 10 ₂ , 10
Delay time of ₄ , 10 ₅ , 10 ₆ τ ₁ , τ ₂ , τ ₄ ,
As for τ ₅ and τ ₆ , 1 as in the conventional case of Fig. 4 (a)
The increase is 0%.

In this embodiment, it is assumed that the delay time of each part of the core circuit is the same as that of the 64-Mbit DRAM. The power supply voltage is 1.5V. FIG. 5 is a result of simulating the relationship between the threshold value of the transfer gate transistor of the memory cell and the delay time by SPICE under the circuit conditions shown in FIG. Due to the decrease in the power supply voltage, the reference value of the threshold value of the transistor is set to 650 mV.

The allowable range of the threshold value of the transistor is determined as follows. The lower limit is determined by the leak current during non-operation. Here, the S factor is 60 mV / decade,
Assuming that the gate voltage at which the drain current becomes 1 μA is the threshold value and the leakage during non-operation is suppressed to 1 fA or less, the lower limit of the threshold value is 540 mV. The upper limit is determined by the delay time.

Assuming that the threshold distribution of the transistor follows a normal distribution, the standard deviation of the threshold is σ = 18.8 mV for a transistor having a channel length of 0.2 μm used in 1 Gbit DRAM. At this time, if the delay time of the delay circuit is uniformly increased by 10% as compared with that of the core circuit as in the 64-Mbit DRAM shown in FIG. 4 (a), the allowable range of the threshold is 540 mV or more and 670 m or more.
It becomes V or less, and about 15% of the memory cells cannot be read. On the other hand, if the delay time of the delay circuit is uniformly increased by 100% as shown in Fig. 4 (b), the allowable range of the threshold is 54
It becomes 0 mV or more and 745 mV or less, and the ratio of defective memory cells can be suppressed from 10 ⁻⁷ to 10 ⁻⁸ , but the access time becomes as large as 60 nsec.

On the other hand, in this embodiment, as shown in FIG. 3, the delay time of the delay circuit is set to 100% more than that of the core circuit only for the memory cell portion, and the rest is 10%. Access time 36.
High-speed performance of 2 nsec can be maintained.

By the way, in a 1 Gbit DRAM, it is almost only defective memory cells that affect the yield. This is because (1) the number of transistors is 10 ^{6 in} other core circuits.
In contrast to the individual level, the number of transistors in the memory cell array is as large as 1 G (about 10 ¹⁹ ), and (2) the threshold voltage of the memory cell transistor is higher than that of other core circuits. This is because the change rate of the delay time with respect to the change of the threshold value becomes large and the allowable range of the threshold value becomes narrow because the threshold value is set. Therefore, according to this embodiment, the yield can be improved without sacrificing the high speed performance.

In the embodiment, only the delay time ratio of the delay circuit corresponding to the delay time of the transfer gate transistor of the memory cell array in the core circuit is set larger than that of the other core circuits. Also for the core circuit, the ratio of the delay circuit corresponding to the delay time can be finely set according to the fluctuation of the threshold value,
This makes it possible to more effectively realize both high-speed performance and yield of the DRAM.

[0019]

As described above, according to the present invention, it is possible to obtain a large capacity DRAM with improved yield without sacrificing high speed performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a DRAM configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of a core circuit at the time of read access in the embodiment.

3 is a diagram showing the relationship between the delay time of each core circuit of FIG. 2 and the delay time of the delay circuit.

FIG. 4 is a diagram showing a relationship between a delay time of a conventional DRAM core circuit and a delay time of a delay circuit.

FIG. 5 is a diagram showing a relationship between a threshold value of a memory cell transfer gate transistor and a delay time.

FIG. 6 is a diagram showing circuit conditions for obtaining the data of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Bit line sense amplifier, 4 ... Column decoder, 5 ... Address buffer, 6 ... I / O sense amplifier, 7 ... I / O buffer, 8 ... Timing control circuit, 10 ... Delay circuit.

Claims (2)

[Claims] 1. A memory cell array in which dynamic memory cells are arranged, a decoder for selecting data in the memory cell array, an address buffer for amplifying an external address for selecting the decoder, and a bit for amplifying data in the memory cell array. A line sense amplifier, a core circuit including an input / output sense amplifier and an input / output buffer provided between the bit line sense amplifier and the input / output pin, and a timing control circuit for controlling the timing for driving the core circuit In the dynamic semiconductor memory device, the ratio of the delay time of each part of the core circuit to the delay time of the delay circuit in the timing control circuit that generates the next drive signal corresponding to the delay time of each core circuit is
A dynamic semiconductor memory device, wherein the dynamic semiconductor memory device is set according to the magnitude of the fluctuation of the threshold value of the transistor in each part of the core circuit. 2. A memory cell array in which dynamic memory cells are arranged, a decoder for selecting data in the memory cell array, an address buffer for amplifying an external address for selecting the decoder, and a bit for amplifying data in the memory cell array. A line sense amplifier, a core circuit including an input / output sense amplifier and an input / output buffer provided between the bit line sense amplifier and the input / output pin, and a timing control circuit for controlling the timing for driving the core circuit In the dynamic semiconductor memory device, the delay time in the transfer gate transistor of the memory cell array and the delay time of the delay circuit in the timing control circuit that sets the activation timing of the bit line sense amplifier from the operation of the transfer gate transistor Is set to be larger than the ratio of the delay time of each part of the other core circuit to the delay time of the delay circuit in the timing control circuit that generates the next drive signal corresponding to the delay time of each part of this core circuit. And a dynamic semiconductor memory device.