JPH10269771A - Semiconductor memory and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for realizing appropriate overdrive regardless of unevenness in process. SOLUTION: When a delay circuit is included in an overdrive pulse generating circuit 101 for controlling drive of overdrive transistors Q3, Q4, the gate length of the transistor constituting this delay circuit is matched with the gate length of the overdrive transistors Q3, Q4, thereby compensating unevenness in process of a MOS transistor and restraining generation of overshoot or undershoot.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
Further, the present invention relates to an improved overdrive circuit for overdriving a common source therein, such as a dynamic random access memory (DR).
AM) and techniques that are effective when applied to AM).

[0002]

2. Description of the Related Art In a semiconductor memory device, for example, a DRAM in which a plurality of dynamic memory cells for storing information are arranged in an array, a trend toward a lower voltage is used in order to improve reliability and reduce power consumption. The power supply voltage supplied from outside the semiconductor chip is stepped down by a step-down circuit inside the chip and then supplied to each internal circuit. As the voltage is reduced, the signal on the bit line is also reduced in amplitude. However, there is a limit to lowering the threshold voltage of a MOS transistor, and therefore, the read / write operation speed tends to decrease. Therefore, it is necessary to devise a circuit so that the read / write operation speed does not decrease even when the voltage is reduced.

An example of a document describing a power supply technique in a semiconductor integrated circuit is disclosed in, for example, Japanese Unexamined Patent Publication No.
There is 9-111033.

[0004]

As a technique for driving a bit line with a reduced amplitude at high speed, there is an overdrive. According to this overdrive, only for a predetermined time from the operation start timing of the sense amplifier,
By increasing the voltage level of the common source above the normal level, the speed of bit line driving can be increased. In other words, the power supply voltage of the sense amplifier is slightly higher than the normal voltage to overdrive the sense amplifier. However, in a DRAM employing such an overdrive circuit, due to process variations,
The drive capability of the MOS transistor for overdrive is undesirably changed, and overshoot and undershoot are likely to occur. The overshoot leads to an increase in power consumption because the bit line capacitance is charged more than necessary. In addition, the precharge level determined by the short-circuit of the complementary bit line pair is undesirably changed to cause a decrease in the read margin. In addition, undershoot has the same disadvantages as in the case of overshoot described above,
This causes refresh deterioration and destruction of memory cell data due to lower back bias of the transfer MOS and the parasitic MOS of the memory cell.

An object of the present invention is to provide a technique for realizing appropriate overdrive irrespective of process variations.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a sense amplifier (SA) for amplifying a signal output from a memory cell to a complementary bit line pair in synchronization with a sense amplifier start signal, and a power supply voltage for supplying an operation power supply voltage to the sense amplifier. An overdrive transistor for overdriving the sense amplifier by extending the potential difference between the common source line pair (PCS, NCS) and the common source line pair beyond a normal level only for a predetermined time from the operation start timing of the sense amplifier. (Q3, Q4) and an overdrive pulse generation circuit (10) for generating an overdrive pulse for driving and controlling the overdrive transistor.
1), the gate length of the transistor constituting the delay circuit (33) included in the overdrive pulse generating circuit is matched with the gate length of the overdrive transistor, and Compensate for process variations.

For example, when the gate length of the overdrive transistor is shortened due to process variation and the driving capability is large, the driving capability of the transistor constituting the delay circuit in the same semiconductor chip also becomes large. , The pulse width of the overdrive pulse is shortened.

When the gate length of the overdrive transistor is long due to process variations and the driving capability is small, the driving capability of the transistor constituting the delay circuit in the same semiconductor chip is similarly reduced, and the delay circuit is not used. Is relatively long, and the pulse width of the overdrive pulse is relatively long. Thus, the pulse width of the overdrive is adjusted according to the process variation, which compensates for the process variation.

At this time, the delay circuit can include a plurality of inverter circuits (IV1, IV2) for delaying the sense amplifier start signal.

Further, such a semiconductor memory device (83)
And a central processing unit (81) capable of accessing the data processing device.

[0013]

FIG. 8 shows an embodiment of a data processing apparatus according to the present invention.

The computer system shown in FIG. 8 is an example of a data processing device. Although not particularly limited, a CPU (central processing unit) 8 is connected via a system bus BUS.
1. A memory controller 82, a ROM (read only memory) 84, a peripheral device control unit 85, a display system 86, etc., are connected to each other so as to be able to exchange signals, and perform predetermined data processing according to a predetermined program. Can be.

The memory controller 82 controls the operation of a plurality of DRAMs 83A, 83B, 83C having a multi-bank configuration.

The CPU 81 is a logical core of the present system, and mainly includes address designation, information read / write, data operation, instruction sequence, acceptance of interrupt, information exchange between the storage device and the input / output device. It has a function of starting up and the like, and includes an arithmetic control unit, a bus control unit, a memory access control unit, and the like. DRAM 83A, 8
3B, 83C, and ROM 84 are positioned as internal storage devices. Various programs and data are stored in the ROM 84. DRAM 83A, 83B, 83C
Functions as a main memory, and the DRAMs 83A, 83
Programs and data required for calculation and control by the CPU 31 are loaded into 3B and 83C. Peripheral device controller 8
5 controls the operation of the storage device 88 and the keyboard 8
9 and the like. As the storage device 88, an auxiliary storage device such as a hard disk device is applied.

Since the DRAMs 83A, 83B and 83C have the same configuration, only the DRAM 83A will be described in detail below.

FIG. 2 shows an example of the configuration of the main part of the DRAM 83A.

Although the DRAM 83A is not particularly limited,
A known semiconductor integrated circuit manufacturing technique including a memory cell array 20 having a storage capacity of 64 megabits and having a plurality of dynamic memory cells MC arranged in an array, and a column-based direct peripheral circuit 21 coupled thereto. As a result, it is formed on one semiconductor substrate such as a single crystal silicon substrate.

The memory cell array 20 includes a plurality of representative word lines WL0 to WL5 and a plurality of complementary data lines DL1, DL1 * to
DL6, DL6 * (* indicates row active or signal inversion), and a plurality of dynamic memory cells MC arranged at intersections of word lines and data lines. Each of the plurality of dynamic memory cells MC includes an n-channel MOS transistor and a charge storage capacitor connected in series to the n-channel MOS transistor, one of which is typically shown. Although the dynamic memory cell MC is not particularly limited, it has a 1/4 pitch cell arrangement with the highest integration, and the layout pitch of the sense amplifier SA is reduced by arranging every other complementary data line. In such a dynamic memory cell MC, the corresponding word line is driven to the selected level, so that the n-channel type
The OS transistor is turned on, and data can be read / written.

The column system direct peripheral circuit 21 includes a sense amplifier SA, a precharge circuit PCC, and a column switch SEL arranged corresponding to complementary data lines, respectively. As representatively corresponding to the complementary data lines DL2 and DL2 *, the sense amplifier SA, the precharge circuit PCC, and the column switch SEL are configured as follows.

In the sense amplifier SA, two inverters each formed by coupling a p-channel MOS transistor and an n-channel MOS transistor are coupled in a loop, and the input / output node thereof is connected to a complementary data line DL.
2, DL2 *.

When the sense amplifier SA is operating, a slight potential difference between the complementary data lines DL2 and DL2 * is amplified by the sense amplifier SA by reading data from the memory cells. Such an operating power supply voltage for the sense amplifier SA is supplied from the power supply unit 50 via a pair of common source lines PCS and NCS.

The precharge circuit PCC is provided for precharging a complementary data line in the column-based direct peripheral circuit 21, and is an n-channel MOS transistor coupled to bridge the complementary data line. 93, 94 and 95. The n-channel MOS transistors 93 and 94 are connected in series with each other,
The operation is controlled by the precharge signal PCB to supply a predetermined precharge voltage to the complementary data line. The operation of the n-channel MOS transistor 95 is controlled by a precharge control signal PCHB having a higher level than the precharge signal PCB, and short-circuits the complementary data line.

The column switch SEL is an n-channel MOS transistor 9 whose operation is controlled by a column selection control signal YS0 obtained by decoding a column address.
6,97. For example, when the column selection control signal YS0 is asserted to a high level, the corresponding n-channel MOS transistor is turned on, so that the complementary data lines DL2 and DL2 * become common I
/ O. In that state, the complementary data lines DL2,
The data of DL2 * can be output to the common I / O, and the write data of the common I / O can be taken into the complementary data lines DL2, DL2 *.

In the column-type direct peripheral circuit 21, n-channel MOS transistors (referred to as shared MOS transistors) 81 to 86 and 71 to 76 are provided which can interrupt the data line to the sense amplifier SA in the middle thereof. The shared MOS transistor is first
By controlling with the shared control signal SHRL and the second shared control signal SHRR, the complementary data line is selectively coupled to the sense amplifier SA. For example, the shared MOS transistor 8
1 to 86 are turned on by the first shared control signal SHRL, the shared MOS transistor 71
-76 are turned off by the second shared control signal SHRR. In this case, the data lines belonging to the memory cell array 20 are selectively coupled to the sense amplifier SA. On the other hand, when the shared MOS transistors 71 to 76 are turned on by the second shared control signal SHRR, the shared MOS transistors 81 to 86 are turned off by the first shared control signal SHRL. Are selectively coupled to the sense amplifier SA.

In the above description, the complementary data lines DL2, DL2
Although a circuit corresponding to DL2 * has been representatively described, a circuit corresponding to another complementary data line is also configured in the same manner as described above.

FIG. 1 shows an example of the configuration of the power supply unit 50.

As shown in FIG. 1, the power supply unit 50 includes a p-channel MOS transistor Q1 for supplying the voltage Vdl to the common source line PCS on the p-channel MOS transistor side of the sense amplifier SA, It includes an n-channel MOS transistor Q2 for supplying the voltage Vsg to the common source line NCS on the n-channel MOS transistor side, and an overdrive circuit 100 for overdriving the sense amplifier SA.

N channel type MOS transistor Q2
Is controlled by a sense amplifier activation signal φSA, and the p-channel MOS transistor Q1 is controlled by a sense amplifier activation signal φSA *.

The overdrive circuit 100
Are based on a p-channel MOS transistor Q3 for supplying the voltage Vdd to the common source line PCS, an n-channel MOS transistor Q4 for supplying the voltage Vss to the common source line NCS, and a sense amplifier activation signal φSA *. The p-channel MOS transistor Q3 and the n-channel MOS transistor Q4
Pulse φSOD for operation control of
*, And an overdrive pulse generation circuit 101 for generating φSOD.

Here, the voltage Vdd is a high-potential-side power supply voltage, and the voltage Vss is a low-potential-side power supply voltage. The voltages Vdd and Vss are stepped down by a step-down circuit to be the voltage Vdl and the voltage Vsg, respectively, and the potential difference between the voltages Vdl and Vsg is smaller than the potential difference between the voltages Vdd and Vss.

FIG. 5 shows the operation timing of the main part.

During the period when the sense amplifier activation signal φSA is asserted to a high level, the sense amplifier activation signal φS
A turns on the n-channel type MOS transistor Q2, and turns on the p-channel type MOS transistor Q1 by the sense amplifier φSA * which is an inverted signal of the sense amplifier start signal φSA, so that the common source line N
CS and PCS are supplied with voltages Vsg and Vdl, respectively. Further, for a predetermined time after the sense amplifier activation signal φSA is asserted to a high level, the overdrive pulse φSOD is set to a high level (φSOD * is a low level), whereby the common source lines PCS, NC
The potential level of S becomes the voltage Vdd and Vss levels, respectively, only immediately after the start of the start of the sense amplifier, and the sense amplifier SA is overdriven. In this overdrive period, a minute signal level difference between the bit lines BL and BL * is amplified at a relatively high speed.

FIG. 3 shows a configuration example of the overdrive pulse generation circuit 101.

As shown in FIG. 3, overdrive pulse generating circuit 101 generates sense amplifier start signal φSA.
*, An inverter 31 for inverting *, a delay circuit 33 for delaying the sense amplifier activation signal φSA *,
It comprises a NAND gate 32 for obtaining a NAND logic between the output signal of the delay circuit 33 and the output signal of the inverter 31, and an inverter 43 for inverting the output signal of the NAND gate 32. Sense amplifier start signal φSA *
Is a low-active signal. The signal φSA * is logically inverted by the inverter 31.
, The output signal of the NAND gate 32 becomes low level only during the period when both the output signal of the inverter 31 and the output signal of the delay circuit 33 are high level.
The output signal of the NAND gate 32 is φSOD *, which is inverted by the inverter 43 to obtain φSOD. Therefore, the delay time of the delay circuit 33 causes φSO
The pulse width of D, φSOD * is determined. That is, the longer the delay time, the wider the pulse width of φSOD, φSOD *.

FIG. 4 shows a configuration example of the delay circuit 33.

As shown in FIG. 4, the delay circuit 33
Are p-channel MOS transistors Q41 to Q4
4 and a first inverter IV1 in which an n-channel MOS transistor Q45 is connected in series, a p-channel MOS transistor Q46 and an n-channel MOS transistor Q46.
Second transistors IV2 each having S transistors Q47 to Q50 connected in series are alternately arranged. Sense amplifier activation signal φSA * is transmitted to the gate electrodes of all MOS transistors in first inverter IV1. The output signal of the first inverter IV1 is a p-channel MOS transistor Q44 and an n-channel MOS transistor Q44.
Obtained from the series connection point with the S transistor Q45, and is connected to all the MOs in the second inverter IV2 at the subsequent stage.
The signal is transmitted to the gate electrode of the S transistor. Further, the output signal of the second inverter IV2 is an n-channel type MO.
It is obtained from a series connection of the S transistor Q49 and the n-channel MOS transistor Q50, and is transmitted to the subsequent first inverter.

Here, in a general design of a delay circuit in which a plurality of inverters are combined, it is preferable to secure a desired delay time with a smaller number of elements. The gate length of each MOS transistor is relatively long, and the current flowing therethrough is suppressed, so that the delay time per element is relatively long. This is because the number of constituent elements can be reduced and the area occupied by the chip can be reduced.

On the other hand, in each of the MOS transistors forming the delay circuit 33 shown in FIGS. 3 and 4, in order to suppress overshoot and undershoot due to process variation, a standard gate in the semiconductor chip is used. The length is adopted. That is, the gate lengths of the p-channel MOS transistor and the n-channel MOS transistor forming the delay circuit 33 are as shown in FIG.
P-channel MOS transistors Q3 and n
Each of the lengths matches the gate length of the channel type MOS transistor Q4. For example, the p-channel type M shown in FIG.
When the gate length of the OS transistor Q3 is 0.6 μm, the gate lengths of all the p-channel MOS transistors forming the delay circuit 33 are 0.6 μm. When the gate length of the n-channel MOS transistor Q4 shown in FIG. 1 is 0.5 μm, the gate length of all the n-channel MOS transistors forming the delay circuit 33 is 0.5 μm. And
M of the P-channel type MOS transistor and the n-channel type MOS transistor involved in securing the delay time
The number of vertically stacked OS transistors is increased. That is, since the sense amplifier activation signal φSA * is low active, the P-channel type M
Since the OS transistor is involved in securing the delay time, the P-channel MOS transistors Q41 to Q44 are stacked vertically. Stacked vertically.

When the gate lengths of the individual MOS transistors are matched as described above, the process variation is compensated, and
In overdrive of the sense amplifier SA, occurrence of overshoot and undershoot can be suppressed. It is for the following reasons.

FIG. 6 shows the relationship between the variation (.DELTA.t) of the delay time in the delay circuit 33 and the driving capability of the overdrive MOS transistors Q3 and Q4.

That is, the gate lengths of the p-channel MOS transistor and the n-channel MOS transistor constituting the delay circuit 33 are adjusted to the gate lengths of the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4, respectively. In the same chip, process variations in the gate lengths of the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4 also appear in the MOS transistors forming the delay circuit 33. That is, when the gate length of the p-channel MOS transistor Q3 or the n-channel MOS transistor Q4 is slightly longer than a desired value due to process variation, the gate length of the MOS transistor forming the delay circuit 33 is slightly smaller than the desired value. It will be longer.

When the gate length of the p-channel MOS transistor Q3 or the n-channel MOS transistor Q4 is slightly longer than a desired value due to process variation and the driving capability is relatively low, the gate length of the MOS transistor forming the delay circuit 33 is used. Is slightly longer than the desired value and the delay time there is relatively long, so that the pulse widths of the overdrive pulses φSOD and φSOD * are widened, and the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4 Since the on-time becomes long, it acts to compensate for the low driving ability of the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4.

Conversely, when the gate lengths of the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4 are slightly shorter than desired values due to process variations and the driving capability is relatively high, the delay is increased. The gate length of the MOS transistor constituting the circuit 33 is also slightly shorter than the desired value, and the delay time there is relatively short, so that the overdrive pulses φSOD, φ
The pulse width of SOD * becomes short, and the p-channel type M
The ON time of the OS transistor Q3 and the n-channel MOS transistor Q4 becomes relatively short. That is, appropriate overdrive is realized regardless of process variations. By compensating for the process variation in this way, the occurrence of overshoot or undershoot due to the process variation is suppressed.

In practice, the power supply voltage condition may fluctuate in addition to the process variation. Such a variation is compensated as follows together with the process variation.

When the overdrive MOS transistors Q3 and Q4 have high driving capability, that is, when the power supply voltage V
When dd is high, when the gate length of the MOS transistor is small, when the threshold value of the MOS transistor is low, or when the drain-source current of the MOS transistor is large, the delay time in the delay circuit 33 is shortened. On time (overdrive time) of MOS transistors Q3 and Q4 is relatively short. Conversely, when the overdrive MOS transistors Q3 and Q4 have low driving capability, that is, when the power supply voltage V
When dd is low, when the gate length of the MOS transistor is long, when the threshold value of the MOS transistor is high, or when the drain-source current of the MOS transistor is small, the delay time in the delay circuit 33 is shortened. On time (overdrive time) of MOS transistors Q3 and Q4 is relatively lengthened. This makes it possible to suppress the occurrence of overshoot or undershoot even when the voltage condition or the process condition changes.

Incidentally, if a MOS transistor having a long gate length is adopted as the whole semiconductor chip, the process variation becomes relatively small, but even in that case, the p-channel type MOS transistor or the n-channel type The gate length of the MOS transistor is set to p-channel type MOS transistor Q3 or n-channel type M transistor.
The process dependency of the overdrive pulse can be further reduced by adjusting the gate length of each of the OS transistors Q4.

As shown in FIG. 7, when the semiconductor chip forming the RAM has two memory cell array portions and peripheral circuits are laid out between them, the MOS transistors Q3 and Q
4 is arranged in the memory array section, and when the overdrive pulse generation circuit 101 is arranged in the peripheral circuit section as indicated by 72, the gate of the MOS transistor forming the overdrive pulse generation circuit 101,
It is desirable that the gates of overdrive MOS transistors Q3 and Q4 be laid out in the same direction. This is because such a layout is very effective in equalizing the process variations of the MOS transistors forming the overdrive pulse generation circuit 101 and the overdrive MOS transistors Q3 and Q4.

According to the above example, the following functions and effects can be obtained.

(1) The gate length of the p-channel MOS transistor or the n-channel MOS transistor constituting the delay circuit 33 is adjusted to the gate length of the p-channel MOS transistor Q3 or the n-channel MOS transistor Q4, respectively. Since the process dependency of the overdrive pulse can be reduced, the occurrence of overshoot and undershoot can be suppressed and appropriate overdrive can be realized regardless of the process variation.

(2) Due to the operation and effect of the above (1), the occurrence of overshoot and undershoot can be suppressed regardless of the process variation.
In this case, current consumption due to overshoot and undershoot can be reduced.

(3) Overdrive pulse generating circuit 1
01 and the gates of the overdrive MOS transistors Q3 and Q4 are laid out in the same direction because the MOS transistor forming the overdrive pulse generation circuit 101 and the overdrive MOS transistor Q3 , Q
4 is very effective in making the process variations equal to each other, whereby the effect of compensating the process variations can be enhanced.

(4) Due to the operation and effect of (2), the current consumption can be reduced in the data processing device to which the DRAM is applied.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, in the above embodiment, the common source line P
Although the description has been given of the case where overdrive is performed by switching the voltage levels of both SC and NSC, the present invention is also applicable to the case where overdrive is performed by switching one of the voltage levels of the common source lines PCS and NCS. The invention can be applied.

In the above description, the invention made mainly by the present inventor is referred to as DRA which is the application field in which the background was used.
Although the description has been given of the case where the present invention is applied to M, the present invention is not limited thereto, and can be applied to various semiconductor integrated circuits.

The present invention can be applied on condition that at least a sense amplifier is included.

[0059]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by adjusting the gate length of the transistor constituting the delay circuit to the gate length of the overdrive transistor, the process variation of the transistor in the overdrive is compensated. In other words, when the gate length of the overdrive transistor is shortened due to process variation and the drive capability thereof is large, the drive capability of the transistor constituting the delay circuit in the same semiconductor chip also becomes large, and the delay time increases. The delay time in the circuit is relatively short, and
If the gate length of the overdrive transistor is increased due to process variation and its drive capability is small, the drive capability of the transistor constituting the delay circuit in the same semiconductor chip is similarly reduced, and the delay in the delay circuit is reduced. Since the time is relatively long, the pulse width of the overdrive pulse is relatively short and long, and occurrence of overshoot and undershoot can be suppressed. Thus, current consumption due to overshoot or undershoot can be suppressed.

By laying out the gates of the MOS transistors forming the overdrive pulse generation circuit and the gates of the MOS transistors for overdrive in the same direction, the MOS transistors forming the overdrive pulse generation circuit, MOS
This is very effective in making the process variations of the transistors equal to each other, whereby the effect of compensating the process variations can be enhanced.

Further, configuring a data processing device including such a semiconductor memory device and a central processing unit capable of accessing the semiconductor memory device can reduce current consumption due to overshoot and undershoot in the semiconductor memory device. Since it is suppressed, it is effective in reducing the power consumption of the data processing device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of an overdrive circuit included in a DRAM according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a main part of the DRAM.

FIG. 3 is a circuit diagram showing a configuration example of an overdrive pulse generation circuit shown in FIG. 1;

FIG. 4 is a circuit diagram illustrating a configuration example of a delay circuit included in the overdrive pulse generation circuit.

FIG. 5 is an operation timing chart of a main part in the DRAM.

FIG. 6 is an explanatory diagram showing a relationship between a variation in delay time in the delay circuit and a driving capability of a MOS transistor for overdrive.

FIG. 7 is an explanatory diagram of a layout direction of a MOS transistor included in the DRAM.

FIG. 8 is a block diagram illustrating a configuration example of a data processing device including the DRAM.

[Explanation of symbols]

 Reference Signs List 20 memory cell array 31, 34 inverter 32 NAND gate 33 delay circuit 50 power supply unit 100 overdrive circuit 101 overdrive pulse generation circuit Q1, Q3 p-channel MOS transistor Q2, Q4 n-channel MOS transistor SA sense amplifier PCS, NCS common source line BL, BL * Bit line φSA, φSA * Sense amplifier start signal φSOD, φSOD * Overdrive pulse

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Miyatake 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Nichicho Cho LSI Engineering Co., Ltd. (72) Inventor Seiji Narii Ome, Tokyo 2326 Imai, Hitachi, Ltd. Device Development Center, Hitachi, Ltd.

Claims (4)

[Claims] 1. A sense amplifier for amplifying a signal output from a memory cell to a pair of complementary bit lines in synchronization with a sense amplifier start signal, and a common source line for supplying an operating power supply voltage to the sense amplifier. A pair of a common source line pair, an overdrive transistor for overdriving the sense amplifier by extending the potential difference from the normal level for a predetermined time from the operation start timing of the sense amplifier, and an overdrive transistor for overdriving the sense amplifier. An overdrive pulse generation circuit that generates an overdrive pulse for drive control, and wherein the overdrive pulse generation circuit includes a delay circuit for determining a pulse width of the overdrive pulse. The gate length of the transistor The semiconductor memory device characterized by comprising in accordance with the gate length of over bar drive transistor. 2. A sense amplifier for amplifying a signal output from a memory cell to a complementary bit line pair in synchronization with a sense amplifier start signal, and a common source line for supplying an operation power supply voltage to the sense amplifier. A pair of a common source line pair, an overdrive transistor for overdriving the sense amplifier by extending the potential difference from the normal level for a predetermined time from the operation start timing of the sense amplifier, and an overdrive transistor for overdriving the sense amplifier. An overdrive pulse generation circuit for generating an overdrive pulse for drive control, wherein the overdrive pulse generation circuit is formed by combining a plurality of inverters, and a delay circuit for delaying the sense amplifier start signal And the delay output signal of the delay circuit A logic gate for generating a one-shot pulse synchronized with the sense amplifier start signal by a logical operation with the sense amplifier start signal; and setting the gate length of the transistor constituting the delay circuit to the gate of the overdrive transistor. A semiconductor memory device characterized by being adapted to a length. 3. The semiconductor memory device according to claim 1, wherein the gate electrodes of the overdrive transistor and the transistor forming the delay circuit have the same direction in the semiconductor chip. 4. A data processing device comprising: the semiconductor storage device according to claim 3; and a central processing unit capable of accessing the semiconductor storage device.