JPH0721774A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To save power consumption of a semiconductor memory using a static memory cell. CONSTITUTION:Static type memory cells 10 are arranged in matrix, word line 11 is made to correspond to each row, and a pair of bit lines 12 is made to correspond to each column. Equalizing transistors 21 are connected to end parts of the bit lines 12, and a power supply is connected to this connecting point through diodes 20 and pre-charge transistors 22. A pre-charge clock phip is given to the equalizing transistors 21 and the pre-charge transistors 22, and when the pre-charge transistors 22 are turned on at a falling of the pre-charge clock phip, a power supply potential reduced with potential by a threshold value of the diodes 20 is applied to the bit lines 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using static memory cells.

[0002]

2. Description of the Related Art SRAM (Static Random Access Mem) using a static type memory cell for obtaining a pair of complementary outputs
ory), corresponding to a pair of complementary output terminals,
A pair of bit lines is connected to each column of memory cells arranged in rows and columns. The pair of bit lines are connected to a power supply via a precharge transistor which is turned on at the time of initialization, and are connected to a data line via a selection transistor which selectively operates according to address information. As a result, after each bit line is charged to a predetermined potential in the initial setting operation, when a specific memory cell is designated based on the address information, a pair of bit lines is set according to the data content stored in the memory cell. One of the two potentials is lowered.

FIG. 4 is a circuit diagram showing a structure of a static type memory cell, and FIG. 5 is a circuit diagram showing a main part of a memory device in which the memory cells are arranged in rows and columns. In a memory cell 10 including four N-channel type MOS transistors 1, 2, 3, 4 and two resistors 5, 6, the drains and gates of the MOS transistors 1, 2 are connected to each other, and the drains of the resistors 5 and 6, respectively. A bistable flip-flop circuit is formed by being connected to a power supply via 6 and grounding the source. The drains of the MOS transistors 1 and 2 forming the flip-flop circuit serve as a pair of complementary output terminals, and the output terminals are respectively paired via the MOS transistors 3 and 4 whose gates are connected to the word line 11 with a pair of bit lines. 12 is connected.

The word line 11 is connected corresponding to each row of a plurality of memory cells 10 arranged in a matrix, and receives the row selection information X1 to Xn corresponding to the number of rows to activate the memory cell 10 of a specific row. Turn into. The bit line 12 is the memory cell 10
The column selection information Y is connected in pairs corresponding to each column.
It is connected to a pair of data lines 14 via a selection transistor 13 receiving 1 and Y2. The bit lines 12 are connected to the power supply via the precharge transistors 15 and the equalizing transistors 16 are provided for each column.
Connected to each other via. The precharge transistor 15 and the equalize transistor 16 are driven by a common precharge clock φ _P (specifically, an equalize clock whose timing is slightly delayed from the precharge clock φ _P ), and are turned on at the time of initialization. Each bit line 12 is charged to the power supply potential.

In such a memory device, after the pair of bit lines 12 are both charged to the power supply potential by initialization, the memory cells 10 designated by the row selection information X1 to Xn are connected to the bit lines 12. . In the static memory cell 10, one of the pair of complementary output terminals has the power supply potential and the other has the ground potential, and therefore, the output having the ground potential of the pair of bit lines 12 charged to the power supply potential. The potential on the side to which the terminal is connected is lowered. Then, the change in the potential of the bit line is detected by a sense amplifier connected to the data line 14, and the read data is determined.

[0006]

When an N channel type MOS transistor is adopted as the precharge transistor 15, the potential of the bit line 12, that is, the source potential of the precharge transistor 15 is higher than the power supply potential by the threshold voltage of the precharge transistor 15. Since the precharge transistor 15 is turned off when the potential reaches a potential lower by the amount, the potential of the bit line 12 does not rise any more. Normally, the period of the precharge operation of the bit line 12 is not set long to shorten the access time, and the initial setting potential of the bit line 12 becomes lower than the power supply potential. When the initial setting potential of the bit line 21 decreases, the potential of the bit line becomes insufficient in low voltage driving, and it becomes difficult to correctly determine the data read from the memory cell 10.

On the other hand, when the P-channel type MOS transistor is adopted as the precharge transistor 15, the precharge transistor 15 is turned on at the fall of the precharge clock φ _P , and then the potential of the bit line 12 becomes the power source potential. Since it does not turn off even if it reaches, the bit line 12 is charged to the power supply potential at the initial setting. When the initial setting potential of the bit line 12 becomes high, the circuit operation becomes stable, but there arises a problem that the power consumption becomes large.

Therefore, it is an object of the present invention to reduce power consumption without deteriorating the stability of circuit operation when using a static memory cell.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it has a pair of complementary output terminals and is arranged in a matrix. Static memory cells and a pair for each column of memory cells, and the bit lines to which the output terminals of each memory cell are connected respectively, and one end of each bit line are connected. A precharge transistor that connects the line to the power supply potential and an equalizing transistor that conducts between the bit lines in each column, and the bit line is connected to the power supply potential through a diode connected in the forward direction. is there.

[0010]

According to the present invention, when the precharge transistor is turned on to charge the bit line, the power supply potential lowered by the threshold value of the diode connected between the bit line and the power supply is applied to the bit line. To be done. Normally, the threshold value of the diode is smaller than the threshold value of the N-channel type MOS transistor. Therefore, if an appropriate number of diodes are connected in series, the initial setting potential of the bit line can be set to an appropriate potential.

[0011]

1 is a circuit diagram showing the configuration of a semiconductor memory device of the present invention. The memory cell 10 and the corresponding word line 11 and bit line 12 are the same as in FIG. 5, and the word line 1 is provided in each row of the plurality of memory cells 10 arranged in a matrix.
1 is associated with each column and a pair of bit lines 12 is provided in each column.
Are associated with. Then, each bit line 12 is connected to the data line 14 connected to the sense amplifier via the selection transistor 13.

The feature of the present invention resides in that the bit line 1
The diode 20 is connected in the forward direction between 2 and the power supply, and the potential applied to the bit line 12 is set lower than the power supply potential by the threshold value of the diode 20. The P-channel type equalize transistor 21 to which the precharge clock φ _P is applied is connected between a pair of bit lines 21 corresponding to each column of the memory cells 10. The cathode of the diode 20 is connected to the connection point between the bit line 12 and the equalizing transistor 21, and the anode of the diode 20 is connected to the drain of the P-channel type precharge transistor 22. And the precharge transistor 2
The source of 2 is connected to the power supply and is supplied with the precharge clock φ _P common to the equalizing transistor 21. As a result, when the precharge clock φ _P falls and the equalizing transistor 21 and the precharge transistor 22 are turned on, the pair of bit lines 12 corresponding to each column of the memory cells 10 are electrically connected to each other, and at the same time,
The power supply potential is applied to the bit line 12 through the diode 20. Therefore, each bit line 12 has a diode 20
When the initializing operation is completed, the bit line 12 is charged to a potential lower than the power source potential by the threshold value of the diode 20 when the power source potential lowered by the threshold value is applied.
Since both the equalize transistor 21 and the precharge transistor 22 are P-channel type MOS transistors, they will not be turned off even if the potential of the bit line 12 rises to the power source potential.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. The memory cell 10, the word line 11, and the bit line 12 are the same as those in FIG. Diode 30
Has an anode connected to the power supply and a cathode connected to the source of the precharge transistor 31. The drain of the P-channel type precharge transistor 31 is connected to the bit line 12, and the potential on the cathode side of the diode 30 is applied to the bit line 12 in response to the precharge clock φ _P given to the gate. The equalize transistor 32 is connected between the pair of bit lines 12 corresponding to each column of the memory cells 10 at the connection point between the precharge transistor 31 and the bit line 12, and the precharge clock φ common to the precharge transistor 31. Upon receiving _P , the mutual bit lines 12 are made conductive. Therefore, bit line 1
The power supply potential lowered by the threshold value of the diode 30 is applied to 2, and the initial setting potential becomes lower than the power supply potential by the threshold value of the diode 30. As described above, when the diode 30 is provided on the power supply side of the precharge transistor 31, a plurality of bit lines 12 can be connected to one diode 30 via the precharge transistor 31, so that the number of elements can be reduced. is there. The unit in which the diode 30 is commonly used is a column unit of the memory cell 10 or
It is determined such that the balance between the current capacity of the diode 30 and the current capacity of the bit line 12 can be maintained in block units.

According to the above configuration, the precharge clock is
Φ_PGoes down and the precharge transistor 22,
When 31 is turned on, one of high level and low level
Each potential V of the pair of bit lines 12₁, V₂But in Figure 3
As shown, both power supply potentials V _DMore diodes 20, 3
Threshold V of 0_TLow potential V_D-V_TStand up to. Ha
Potential V of bit line 12 at level i₁Is temporarily reduced
To do this, the equalizing transistors 21 and 32 are not
Charge clock φ_PBecause it turns on at the falling edge of
It In addition, the precharge clock φ_PIs the bit line 12
Is a predetermined potential (V_D-V_T) Stand up after being charged up to
Precharge transistors 22, 31 and equalizer
The transistors 21 and 32 are turned off, and the bit line 12 is
Both are floating. Charged during initial setup
Bit line 12 potential V_D-V_TAre diodes 20, 3
Threshold V of 0_TIs the threshold of N-channel MOS transistor
Value V_NPrecharge transistor because it is smaller
Initial setting potential when 22 and 31 are N-channel type
V_D-V_NWill be higher than. Therefore, even when driving at low voltage
At the same time that stable circuit operation is obtained, the bit line 12
Power consumption can be reduced by lowering the initial setting potential.

The initial potential V _D -V _T of the bit line can be controlled by connecting a plurality of diodes 20 and 30 in series. That is, when the single diode 20, 30 cannot sufficiently lower the initial setting potential of the bit line 12, the plurality of diodes 2
By connecting 0 and 30 in series, the initial setting potential of the bit line 12 is lowered to a level at which power consumption is effectively reduced. However, if the potential of the bit line 12 drops too low, malfunction may occur as in the case where the N-channel MOS transistor is used as the precharge transistor. Therefore, lowering the initial setting potential of the bit line 12 reduces the circuit operation. It is necessary to do so to the extent that the stability of can be guaranteed.

[0016]

According to the present invention, the power consumption can be reduced while preventing the malfunction of the circuit, and the low power consumption semiconductor memory device in which the stability of the circuit operation is guaranteed can be realized. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing a potential variation of a bit line.

FIG. 4 is a circuit diagram of a static memory cell.

FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

 10 memory cell 11 word line 12 bit line 13 selection transistor 14 data line 15, 22, 31 precharge transistor 16, 21, 32 equalize transistor

Claims (3)

[Claims] 1. A plurality of static memory cells having a pair of complementary output terminals, which are arranged in rows and columns, and a pair are associated with each column of the memory cells, and the output terminals of each memory cell are connected to each other. And a precharge transistor that is connected to one end of each bit line and that connects the bit line to the power supply potential and an equalizing transistor that conducts between the bit lines of each column during the initialization operation. A semiconductor memory device, wherein the bit line is connected to a power supply potential via a diode connected in a forward direction. 2. The semiconductor memory device according to claim 1, wherein a diode is connected in a forward direction between the bit line and the precharge transistor. 3. The semiconductor memory device according to claim 1, wherein a diode is connected in a forward direction to a power supply potential side of the precharge transistor.