JPS639095A - Static type semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up a sense action and operations and to reduce power consumption by precharging a bit line to the inbetween of a power source voltage and a grounding voltage. CONSTITUTION:If a change in an address input generates a bit line equalize signal phiBE to supply it to an equalize signal line 12, transistors QPR, QPR and QEQ in a bit line equalize precharge circuit 10 are turned on. Thus the potentials of a bit line BL and the inverse of BL are precharged at half the power source voltage VDD. When a column and a word line are selected, transmission gate transistors Q5 and Q6 in a memory cell MC are turned on. The bit line BL and the inverse of BL are pulled up and down, respectively, and their difference potential is read out through a sense amplifier SA. Accordingly, the potential difference between bit lines is quickly produced, and simultaneously precharge time is shortened, whereby low power consumption and speed up are attainable.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a pit line of a semiconductor memory, particularly a static random access memory (SRAM) having a complete CMO8 (complementary insulated dart) type memory cell. Regarding the precharge/equalization circuit system.

(Prior Art) In a conventional CMO8 type SRAM, as shown in FIG.
As a pit line precharge/equalization circuit 40 for precharging and equalizing the pair, the pit line BL,
Normally on-type transistors 41 and 42 are connected between BL and the vDD power supply terminal, and a depletion-type equalizing transistor 43 is connected between the pit lines BL and BL. Reference numeral 44 denotes a pit line equalization signal line connected to the dart of the equalization transistor 43. 45 representatively shows one of the CMO8 type memory cells in which a pair of data input/output terminals are connected to the pit lines BL, BL, and the milk indicates a word line connected to the selection control terminal of the memory cell MC. One piece is shown as a representative. Also, 45 and 46 are column decoder output C
It is an N-channel type column selection transistor whose on/off state is switch-controlled by D, and the bit line BL
, BL are connected to a sense amplifier 47 for bit line potential sense amplification (one amplifier is used for a plurality of columns via data lines DL, DL) via the transistors 45 and 46. It is connected. Note that the writing circuit system is not shown.

The read operation in the SRAMK is performed according to the timing shown in FIG. That is, when a change in the address input is detected by an address change detection circuit (not shown) and a bit line equalize signal φ□ is generated and supplied to the equalize signal line 44, the equalize transistor I3 is activated during this signal period. turns on. As a result, the potential of the bit lines BL, BL (with the previous memory cycle completed, one is V!, D potential, the other is V8s
It is at electric potential. ) is equalized to the grid potential. In this case, normally on transistors 41 and 42
When the holding voltage of is expressed as vTH, the precharge potential is v
DD-v becomes H. Note that, prior to this equalization operation, the address input is sent to a column decoder (not shown).
When the column shown in FIG. 4 is selected by the CD signal decoded and generated by the CD signal, the column selection transistors 45 and 46 of this column are turned on. Next, when the word condensed milk in FIG. 4 is selected by the word line selection signal generated by decoding the address input by a row decoder (not shown) and the word line voltage rises to the vDo voltage, this Memory cell M connected to word condensed milk
C is selected and its retained data is transferred to bit lines BL, B
Read out to L. In this case, the memory cell MC is
The transmission transistor (for example, 48) connected to the low potential storage node side is turned on, and current flows from the bit line BL connected to this transistor 48 to the drive transistor 49 through the transistor 48. By being pulled in, the potential of the bit line BL is lowered. On the other hand, the transmission r-) transistor 50 connected to the high potential storage node side of the memory cell MC remains in the off state, and this transistor 50
The potential of the bit line BL connected to the bit line BL does not change and remains at the grid potential. Therefore, bit line BL
, BL, and this potential difference is sense-amplified by the sense antenna 7'47 and becomes read data.

The above SRAM is described in, for example, Nobum, a paper presented at the International Solid State Circuit Conference (I5SCC) in February 1986.
lch1. O,et,al,,-A 30ns 256
K Full C-MOS-8RAM”.

Incidentally, in the access time of an SRAM, the delay from the selection of a memory cell in the read mode to the sensing operation of the sense amplifier occupies the largest proportion. However, in conventional SRAMs, when reading memory cell data, the potential of one of the bit lines of the bit line pair is pulled down from the recharge potential to a low potential using only the driving force of one of the driving transistors in the memory cell. However, since the parasitic capacitance of the bit line is as large as several hundred pi' in a 256KSRAM, the pull-down speed is slow. Therefore, it takes a long time to generate a potential difference between the bit lines BL and BL that enables the sensing operation of the sense amplifier 42, and the access time becomes slow.
It has been difficult to realize high-speed SRAM.

(Problems to be Solved by the Invention) As described above, the present invention solves the problem of one side +7) IK in the memory cell.
This was done to solve the problem that the reading speed of memory cell data is slow due to the use of the driving force of only one driving transistor in the memory cell. An object of the present invention is to provide a static semiconductor memory that can increase the read speed of memory cell data by using the driving force of the load transistor of the present invention, and can realize a high-speed access time.

[Structure of the Invention] (Means for Solving the Problems) The static semiconductor memory of the present invention is a complete CMO8
A synchronous precharge/equalization circuit is connected to the bit lines BL and BL of each column of the memory cell array of memory cell type memory cell, and the memory cell power supply voltage and ground voltage are used as the precharge power supply of this synchronous precharge/equalization circuit. The invention is characterized in that it is equipped with a grid-charge power supply circuit that supplies a voltage intermediate between the two.

(Function) When a memory cell is selected with the bit lines BL and BL precharged and equalized to an intermediate voltage, the two transmission dart transistors of the selected memory cell are turned on, and one of the driving transistors is turned on. The transistor draws current from one bit line, and one load transistor supplies current to the other bit line.
The potentials of the bit lines BL and BL change simultaneously in different directions. As a result, the potential difference between the bit lines required for the sensing operation of the sense amplifier is quickly generated, and the sensing operation is faster. Furthermore, since the precharge/equalization potential is an intermediate potential, the precharge/equalization time can be short and the precharge current can also be small.

Therefore, it becomes possible to realize a high-speed SRAM with low power consumption.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a complete CMO 8-type memo type Morisel, for example 2
1 of the memory cell array in a 56-bit SRAM
The bit line B
L and BL are connected to a precharge power supply circuit 1 via a synchronous precharge/equalization circuit 10. This precharge power supply circuit 11 receives the vDD power supply voltage and is connected to an intermediate potential (for example, a specific example thereof will be described later).
, BL are connected in series to N-channel enhancement type (E type) precharge transistor Q.
p B *N-channel E-type equalizing transistor Q connected between QP11 and bit lines Bl, BL
8Q and each of the above transistors QPR+QpB
+ QEQ gate is bit line precharge signal line 1
Connected to 2. The other circuit parts are the same as those shown in FIG.
The type column selection transistor SA is a sense amplifier commonly used in multiple columns. Complete CMO8 above
Memo type upper Mori cell, N channel E type driving transistor Q1. (h and P-channel E type load transistors Qs and Q4 are connected in a free lug frog connection between the vDD power supply terminal and the v88 power supply terminal (ground terminal), and this flip 7
N-channel E-type transmission dart transistors Qs and Qa are connected between the pair of input and output terminals of the 0-tube and the bit lines BL and BL.
The word line skin is connected to each dart of the transmission transistors Qs and Qs for transmission r-). Note that the writing circuit system is not shown.

FIG. 2 shows an example of the preacher-zoom power supply circuit 11, in which a P-channel E-type transistor 21 whose dirt is connected between the vDD power supply terminal and the ground terminal, and a drain terminal
N-channel E-type transistors 2 connected to each other
2. P-channel E-type transistor 23 whose source and substrate are connected to each other and whose gate and drain are connected to each other.
, f-) are connected in series with an N-channel E-type transistor 24 connected to the vDD power supply terminal. An N-channel E-type transistor 25 has a gate connected to the drain interconnection point of the transistors 21 and 22, and an N-channel E-type transistor 26 has a gate connected to the drain interconnection point of the transistors 23 and 24. v
DDt is connected in series between the source terminal and the ground terminal, and in the case of this transistor, -yVDD = 2.5 V)
is now available.

A read operation in the SRAM having the configuration shown in FIG. 1 is performed according to the timing shown in FIG. 3. That is,
When a change in the address input is detected by an address change detection circuit (not shown) and a bit line equalize signal φ□ is generated and supplied to the equalize signal line 12VC, during this signal period, the bit line equalize/gricharge circuit 10
Each transistor QpHr QpB + Q□ is turned on. As a result, the potential of the bit lines BL and BL (
With the previous memory cycle completed, one side is
The other potential is the vsIl potential. ) is equalized and charged to an intermediate potential (HVl in this example)D)lc7''J.Before the precharge/equalize operation, the address input is decoded by a column decoder (not shown). When the column shown in FIG. 1 is selected by the generated CD signal, the column selection transistor QIIL I QBL of this column is activated.

Be in a man state. Next, when the address input is decoded by a row decoder (not shown) and a generated word line selection signal generates a word line selection signal, the word line skin in FIG. 1 is selected and the word line voltage rises to the vDD potential. The memory cell MC connected to the line skin is selected and its held data is read out to the bit lines BL, BL.

In this case, the two transmission transistors QsrQ6 in the memory cell are turned on, and the driving transistor (for example, Qs) connected to the low potential storage node receives the current from the bit line BL. Retraction,
The load transistor Q3 connected to the high potential storage node side supplies current from the vDD power supply terminal to the bit line BL. As a result, one bit line BL is pulled down from 2.5v to about 2.0v, and the other bit line BL is pulled down from 2.5v to about 2.8v to 3.0v. Therefore, a potential difference is generated between the bit lines BL and BL, and this potential difference is sensed and amplified by the sense amplifier SA to become read data.

As a result, the higher potential side of the bit lines BL and BL is at the vDD potential (operating power supply voltage of the sense antenna fSA).
None, the low potential side is vll, the power supply potential. After this, the word line selection signal returns to the vlIg potential, and the column decode output signal returns to the vsg potential. Note that the timing of the column decode output signal is not limited to the above example, and may rise after the rise of the word line selection signal. Furthermore, the sense amplifier SA may be caused to perform a sensing operation by applying a sense enable signal.

According to the above-mentioned SRAM, since the change in the pit line equalization potential is 1° compared to the conventional example, the equalization time can be shortened, and the amount of charge charge can also be small, so the precharging time can be shortened. Also, when reading data from a memory cell, the current drive capability of one drive transistor in the memory cell pulls down the potential of one bit line, and at the same time, the current drive capability of one load transistor pulls down the potential of the other bit line. The sense movement becomes faster because it makes the sense move faster. That is, the potential difference between the bit lines that allows the sense amplifier SA to perform the sensing operation is the same as in the conventional example (for example, 0.
5 V), compared to the time required to lower the potential of one bit line by 0.5 V using only the current driving capacity of one driving transistor as in the conventional example, in this example, One drive transistor lowers the potential of one bit line by 0.25cm, while the other load transistor lowers the potential of the other bit line by 0.25cm.
The time required to raise V can be shortened to less than i. Further, in this embodiment, the sense amplifier adjusts the potential of the high potential side bit line from 2.8V to 3.8V. While increasing the potential from OV to vDD potential (5■), the potential of the pit line on the low potential side is set to 2. Since sense amplification is performed to lower the potential from Ov to V3s potential (ground potential), the sense amplifier has a lower potential than the conventional sense amplifier, which lowers the potential of the low potential side bit line from about 4.5μ to Vas potential. The amplification operation time can be shortened. Therefore, according to the SRAM of this embodiment,
Since the charge/equalization time and the sensing operation time are each reduced to about 1 compared to the conventional example, it is possible to speed up the reading time of memory cell data, and thus the access time.

Furthermore, as described above, since the bit line precharge potential is approximately 1 compared to the conventional example, the precharge current and, therefore, the power consumption can be reduced.

Note that the grid-charge potential is not limited to 2 vDD K, but may be an intermediate value between the vDD power supply potential and the vs3 power supply potential, but it is desirable that it be around 2 vDD.

Furthermore, the present invention is applicable not only to memory integrated circuits but also to on-chip memories formed on the same chip as a logic integrated circuit or the like.

[Effects of the Invention] As described above, according to the static semiconductor memory of the present invention, by setting the bit line pair to an intermediate potential in synchronization with the precharge/equalize signal, one of the driving transistors in the memory cell can be set to an intermediate potential. It is possible to increase the read speed of memory cell data by using not only the driving force of the load transistor but also the driving force of one of the load transistors, thereby realizing a faster access time and reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 shows an SRAM according to an embodiment of the present invention. 2 is a circuit diagram showing an example of the grid charge power supply circuit in FIG. 1, and FIG. 3 is a circuit diagram showing the read operation of the memory in FIG. 1. 4 is a circuit diagram showing one output RAM of a memory cell array in a conventional SRAM,
FIG. 5 is a timing diagram showing the read operation of the memory of FIG. 4. 10...Synchronous recharge/equalize circuit, 11
...Precharge power supply circuit, BL, BL...pit line, MC...memory cell, Ql, Q2...drive transistor, Qs, Q4...load transistor, Q
s, Qg... Transistor for transmission f-). Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] A complete CMOS memory cell in which two N-channel drive transistors and two P-channel load transistors are connected in a flip-flop manner, and an N-channel transmission gate transistor is connected to the data input/output terminals of the flip-flops. In a static semiconductor memory having an array of , a synchronous precharge/equalization circuit is connected to the bit line BL of each column of the memory cell array, and a precharge power supply for this synchronous precharge/equalization circuit is used. A static semiconductor memory comprising a precharge power supply circuit that supplies a voltage intermediate between a memory cell power supply voltage and a ground voltage.