JP2001307479A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM in which an appropriate bit line reference potential can be set by using a dummy cell of a capacity coupling type. SOLUTION: In a memory cell array 1, a pair of bit lines BLbBL is pre- charged to an internal power source VBLH. This memory cell array 1 is provided with an auxiliary cell array 2 used for adjusting a reference potential. In the auxiliary cell array 2, write-in and read-out of 1/2 VBLH is performed for the memory cell, decision by majority of sense output of an auxiliary sense amplifier circuit 9 is performed by a decision by majority circuit 11, a high level potential VDWLH supplied to a dummy word line driving circuit 5 is generated by a VDWLH generating circuit 13 in accordance with the result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a dynamic semiconductor memory device (DRAM) which requires a low voltage operation and a high speed operation.

[0002]

2. Description of the Related Art Hitherto, high integration and high speed of semiconductor integrated circuits have been achieved by miniaturization of elements. In particular, semiconductor memories are being miniaturized and highly integrated utilizing the characteristics of the regularity of the memory cell array. In particular, a DRAM using a dynamic memory cell including one transistor and one capacitor is at the forefront of increasing capacity.

In the case of a DRAM, since a memory cell itself does not have an amplifying function, a high-sensitivity sense amplifier is required.
Usually, a flip-flop type sense amplifier is used. Before data reading, the bit line pair is precharged to a certain potential. Then, after the precharge of the bit line pair is released and the floating state is established, the word line is activated to access the memory cell. Thereby, the transistor of the selected memory cell is turned on, and the cell capacitor is connected to the bit line. The sense amplifier detects and amplifies a change in the bit line potential due to the connection of the cell capacitor to the bit line by comparing the change with the reference potential of the reference bit line.

[0004] The precharge potential of a bit line before data sensing is equal to the power supply voltage V at the beginning of the history of DRAM.
DD. This is because the DRAM circuit is composed of only NMOS transistors. This VD
In the D precharge method, a dummy cell is required to generate a reference potential. The dummy cell method includes a method of writing １ ／ VDD using a dummy cell having the same capacity as a normal memory cell, and a method of using a dummy cell having a capacity １ ／ of a normal memory cell, and a low level potential GND (= V
SS). Thus, when the dummy cell is connected to the reference bit line, a reference potential intermediate between the bit line potentials when the memory cell data is "0" or "1" can be obtained on the reference bit line.

[0005] CMOS technology has been developed,
When it is used for M, a 1/2 VDD precharge type DRAM appears. Due to high speed and low power consumption, the 1/2 VDD precharge method using the CMOS technology is still the mainstream of DRAM. In this system, no dummy cell is required in principle. However, there are many cases where a dummy cell is used for the purpose of, for example, coupling noise between a word line and a bit line and balancing the capacity of a bit line.

The above-mentioned DRAM has been miniaturized and highly integrated in accordance with the scaling rule of MOS transistors. However, the power supply voltage and the threshold voltage of the MOS transistor are not scaled in the same manner as the device dimensions because of the compatibility with the external connection and the necessity of suppressing the leakage current. However, since the power supply voltage is not scaled, the electric field applied to the MOS transistor increases as the miniaturization progresses. Therefore, the power supply voltage has to be reduced from the viewpoint of reliability.

On the other hand, regarding the threshold voltage of the MOS transistor, the leak of the memory cell must be suppressed to a value specified by the refresh cycle or less.
It cannot be reduced according to the scaling law. Therefore, "1" corresponds to the threshold voltage of the memory cell transistor.
In order to prevent a voltage written as data from decreasing, a word line is driven with a voltage boosted from a power supply voltage. However, if the boosted power supply for driving the word line is also limited from the viewpoint of reliability, the threshold voltage of the cell transistor cannot be reduced, so that the level of “1” data written in the cell is changed to the power supply voltage VDD.
Will be difficult to keep. That is, in the Ｖ VDD precharge method using Ｖ VDD as a reference potential, “1” data is insufficiently written.

Therefore, at present, an internal power supply VBLH lower than the external power supply VDD is prepared in the memory cell array portion, and the internal power supply potential VBLH is made to be substantially equal to the level of "1" data written in the memory cell. I have. In this case, the bit line precharge method is a 1/2 VBLH precharge method in which a reference potential of 1/2 VBLH can be obtained by bit line equalization.

On the other hand, among the power consumption of DRAM, charging and discharging of bit lines occupies the largest ratio. Therefore DR
To reduce the power consumption of the AM, it is very effective to lower the internal power supply VBLH and reduce the bit line amplitude. In recent years, there has been a demand for a lower voltage of the internal power supply VBLH from the demands of systems such as portable electronic information devices. Like this
The lowering of the voltage of the memory cell array section is proceeding more than the peripheral circuits.

[0010]

When the miniaturization of the DRAM advances and the value of the precharge potential 1/2 VBLH decreases to near the threshold voltage of the transistor constituting the sense amplifier with the decrease of the internal power supply VBLH, , 1 / 2V
In the sense amplifier of the BLH precharge system, there is a problem that the operation speed is significantly reduced. To solve this problem, while maintaining the 1/2 VBLH precharge method,
Several attempts have been made to secure and improve operating speed.

For example, a PMOS sense amplifier is connected to VBL
H is driven by a voltage higher than H, or the NMOS sense amplifier is driven by a negative voltage lower than GND. There is a well-synchronized sense system that eliminates the gate bias effect and lowers the threshold voltage during operation of the sense amplifier. In order to ensure the high speed of the sense amplifier under a low voltage, it is necessary to use these methods alone or in combination. Another solution is to adopt a VBLH precharge method instead of the 1/2 VBLH precharge method.

The VBLH precharge system requires a dummy cell as in the case of the VDD precharge system. However, in this case, there are the following problems as miniaturization progresses. In order to obtain a large capacity with a small occupied area, a three-dimensional structure such as a trench structure or a stack structure is used for a memory cell. For this reason, it is difficult to form a dummy cell having half the capacity of a normal memory cell, and a method is used in which a dummy cell having the same structure and capacity as a normal memory cell is formed and 1/2 VBLH is written into the dummy cell. 1/2
To write VBLH, set the bit line pair to 1/2 VBLH
To activate the dummy word line. However, in this method, even if the sensing time is shortened, extra time is required for the bit line equalization for producing 1/2 VBLH, making it difficult to operate in a high-speed cycle.

As a method for generating a reference potential, there is a method using a dummy cell of a coupling capacitance type. This uses a capacitor connected between a dummy word line and a bit line as a dummy cell. For example, a MOS capacitor is used as the capacitor. In this scheme,
While the bit line is being precharged, the dummy word line is also precharged to a predetermined drive voltage, and after the bit line becomes floating, the potential of the dummy word line on the reference bit line side is dropped to thereby reduce the capacitance. A reference potential is generated on the reference bit line by coupling. At this time, the reference potential can be set according to the size of the MOS capacitor forming the dummy cell. With this method, no extra time is required to precharge the bit line to 1/2 VBLH.

However, it is difficult to appropriately set the reference potential in the dummy cell of the capacitive coupling type at the design stage, and it is necessary to make a decision while feeding back the evaluation result of the device. Moreover, even if the reference potential is set as a result of such an evaluation, the reference potential is affected by a variation between chips such as a variation in a process. In addition, due to dynamic factors such as differences in the environment actually used and changes in the temperature inside the chip during operation, the reference potential is not always at an optimum value, and a large margin is required. However, while the effective reduction of the cell capacitance is progressing due to the reduction of the cell capacitance due to the miniaturization, the increase of the capacitance between bit lines, etc., the setting of the large margin is not allowed for the setting of the reference potential.

The above description has been made on the premise of the VBLH precharge method. However, the bit line is precharged to the ground potential GND (generally, a low potential of the bit line amplitude), and the PMO is precharged.
There is also a GND precharge system in which bit line data sensing is performed by a sense amplifier constituted by S transistors. The problem of the reference potential setting in the VBLH precharge method described above similarly exists in the GND precharge method.

The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit device having a DRAM capable of setting an appropriate bit line reference potential using a capacitively coupled dummy cell. It is intended to be.

[0017]

A semiconductor integrated circuit device according to the present invention has a plurality of word lines and a plurality of pairs of bit lines intersecting the word lines, and a dynamic portion is provided at each intersection of the word lines and the bit line pairs. Type memory cells are arranged in a matrix, and at least one is connected to each bit line pair, and is provided with a capacitively coupled dummy cell driven by a dummy word line to generate a reference potential at one of the bit line pairs. A memory cell array; a sense amplifier circuit for detecting and amplifying a potential difference between the bit line pair; and a precharge circuit for precharging the bit line pair to a high potential or a low potential having a bit line amplitude determined by an internal power supply supplied to the memory cell array. A reference potential is generated to one of the bit line pairs via the charge circuit and the dummy cell selected by driving the dummy word line. And a reference potential adjusting circuit for adjusting a reference potential applied to one of the bit line pairs by controlling the level of a drive signal output by the dummy word line driving circuit. Features.

According to the present invention, by providing the reference potential adjusting circuit, the DR using the coupling capacitance type dummy cell is provided.
It is possible to optimally set the reference potential in AM. Specifically, the reference potential adjustment circuit writes, for example, an intermediate potential between the high potential and the low potential of the bit line amplitude in a predetermined memory cell, and makes the potential equal to the potential obtained when the intermediate potential is read out to the bit line. It controls the level of the drive signal output by the dummy word line drive circuit. Thus, the reference potential generated by using the capacitive coupling type dummy cell can be made the same as the reference potential generated by the conventional type dummy cell.

In the present invention, the reference potential adjusting circuit detects, for example, an auxiliary cell array provided independently of the memory cell array and independently accessed for adjusting the reference potential, and a potential difference between a bit line pair of the auxiliary cell array. An auxiliary sense amplifier circuit for amplifying, and an intermediate potential between a high potential and a low potential of a bit line amplitude is written to a predetermined memory cell of the auxiliary cell array, and is read in accordance with a sense output obtained by the auxiliary sense amplifier circuit. And a dummy word line drive signal level generating circuit for generating a drive signal level to be output by the dummy word line drive circuit. In this case, preferably, a signal line pair connected to the bit line pair of the auxiliary cell array via a selection gate is provided, and the bit line pair is pre-set to an intermediate potential of の of the internal power supply potential. It is assumed that an equalizing circuit for charging is provided. More preferably, the auxiliary cell array is provided for a plurality of pairs of bit lines, and a plurality of the auxiliary sense amplifier circuits are provided correspondingly,
A majority circuit is provided for taking the majority of the sense outputs of the plurality of auxiliary sense amplifier circuits.

In the present invention, the reference potential adjusting circuit is also selected by a spare word line parallel to the word line and extended by sharing a bit line pair in the memory cell array for adjusting the reference potential. A spare cell array having a memory cell, and a sense output obtained by the sense amplifier circuit when an intermediate potential between a high potential and a low potential of a bit line amplitude is written to a predetermined memory cell of the spare cell array and read out therefrom, A dummy word line drive signal level generating circuit for generating a drive signal level to be output by the dummy word line drive circuit. Thereby, the reference potential can be adjusted without providing a dedicated auxiliary cell array for adjusting the reference potential. in this case,
The spare cell array to be added is preferably provided for two spare word lines.

In the present invention, preferably, a pair of switch elements for controlling conduction and non-conduction between a bit line pair of a memory cell array and each sense node of a sense amplifier circuit are provided, and a dummy cell is provided. Are arranged closer to the sense amplifier circuit than this switch element. With such a configuration, the reference potential can be coupled by the dummy cell while the bit line is disconnected from the sense amplifier circuit, and the area of the dummy cell can be reduced.

According to the present invention, a DR using an internal power supply potential VBLH lower than the external power supply potential VDD for a memory cell array is provided.
Although it is effective for AM, in this case, as a bit line precharge method, in addition to a method of precharging to a high potential VBLH of an internal power supply, a method of using a method of precharging to a low potential GND is also effective.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a main configuration of a DRAM according to a first embodiment of the present invention. The memory cell array 1
A plurality of word lines WL and a plurality of pairs of bit lines BL and bBL
Are arranged so as to cross each other, and the memory cells MC at the respective intersections are arranged and configured. As shown in FIG. 2, the memory cell MC includes one NMOS transistor and one capacitor. In the memory cell array 1, each bit line pair BL, bBL is provided with one dummy cell DC driven by a dummy word line DW10, DWL1 arranged in parallel with the word line WL.
This dummy cell DC is of a coupling capacitance type, and as shown in FIG. 2, is composed of capacitors C0 and C1 each having one end connected to dummy word lines DWL0 and DWL1 and the other end connected to bit lines BL and bBL. Capacitor C0, C
1 is a MOS type capacitor.

A word line WL of the memory cell array 1 is selected by a row decoder 3 and driven by a word line driving circuit 4. The dummy word lines DWL0 and DWL1 are driven by the dummy word line drive circuit 5. The bit line pair BL, bBL of the memory cell array 1 is connected to the bit line sense amplifier circuit 7. Bit line selection is performed by the column decoder 6 and the column gate 8 driven by the column decoder.

As shown in FIG. 2, the sense amplifier circuit 7 includes an NMOS sense amplifier SA1 having a flip-flop constituted by NMOS transistors QN1 and QN2,
And a PMOS sense amplifier SA2 in which a flip-flop is formed by the PMOS transistors QP1 and QP2. The activation signal SAN is input to a common source of the NMOS sense amplifier SA1. An internal power supply VBLH lower than an external power supply is supplied to a common source of the PMOS sense amplifier SA2. That is, the portion of the memory cell array 1 including the sense amplifier circuit 7 has the internal power supply potential VB
Operated by LH.

As shown in FIG. 2, a bit line pair BL, bB
L is provided with a bit line precharge circuit 21 for precharging the same to the internal power supply potential VBLH. In this example, the precharge circuit 21 is driven by a precharge control signal PRC to generate a pair of bit lines BL and bB.
PMOS transistors QP3, Q for applying VBLH to L
P4.

In this embodiment, an auxiliary cell array 2 which is used to adjust the reference potential of the bit line and is accessed independently of the memory cell array 1 is provided. The auxiliary cell array 2 has the same length in the bit line direction as the memory cell array 1, and as shown in FIG. 3, a dynamic memory cell MC basically similar to the memory cell array 1, and one for each bit line. Each having a coupling capacitance type dummy cell DC. The auxiliary cell array 2 writes 1/2 VBLH, which is an intermediate potential of the internal power supply potential, into a predetermined memory cell by equalizing a bit line pair,
This is read to generate a reference potential serving as a reference. Specifically, in the case of this embodiment, the auxiliary cell array 1
, Three or more pairs of bit lines are provided.

The auxiliary cell array 2 also has the memory cell array 1
Similarly, the auxiliary sense amplifier circuit 9 and the column gate 1
0 is provided. The difference between the unit configuration of the memory cell array 1 shown in FIG. 2 and the unit configuration of the auxiliary cell array 2 shown in FIG. 3 is that the auxiliary cell array 2 is provided with a bit line equalizing circuit 22. This bit line equalizing circuit 22 is provided with an NMO
Bit line pair B via S transistors QN3 and QN4
It is provided on a pair of signal lines DQ and bDQ connected to L and bBL. The equalizing circuit 22 is driven by a control signal line EQL to apply a precharge potential VBLEQL (= １ ／ VBLH) to the signal line lines DQ and bDQ.
S transistors QN5, QN6 and signal lines DQ, bDQ
It has an NMOS transistor QN7 that short-circuits between them.

The equalizing circuit 22 has a function of precharging the bit line pair BL, bBL which has been precharged to VBLH by the bit line precharging circuit 21 again to 1/2 VBLHB after releasing the precharge. . This is because the intermediate potential 1/2 VBLH required for adjusting the reference potential is written to the memory cell as described later. This means that after the precharge of the precharge circuit 21 is released, the column gate 10 is turned on,
This is performed by setting the equalizing control signal line EQL to “H”.

The word line WL and the dummy word line DWL of the auxiliary cell array 2 are set by an appropriate address input.
Selected by the auxiliary cell array controller 12. In the auxiliary cell array 2, an operation of generating a reference potential by writing and reading data is performed as described later. The result is detected by the auxiliary sense amplifier circuit 9. A majority circuit 11 for taking a majority decision of the result is provided, and a dummy word line drive signal level (VDWLH) generation circuit 13 for determining a precharge potential for driving the dummy word line DWL is provided according to the result of the majority decision. Have been.

In this embodiment, the function of the column gate 10 provided on the auxiliary cell array 2 side is different from that of the column gate 8 on the memory cell array 1 side. As shown in FIG. 3, the column gate 1 is located on the auxiliary cell array 2 side.
A bit line equalizing circuit 22 is provided outside of 0,
The column gate 7 is used for simultaneously selecting and deselecting all bit line pairs of the auxiliary cell array 2 for equalizing and releasing bit lines. However, the column gate 10
May select bit line pairs in order one column at a time, similarly to the memory cell array 8 side.

FIG. 4 shows a read operation waveform in this embodiment. During the precharge period of PRVC = “L” (= Vss), the bit line pair BL, bBL is precharged to the high potential of the bit line amplitude, that is, the internal power supply potential VBLH. Meanwhile, the word line WL is at “L”,
The dummy word line DWL is precharged to VDDWLH by the dummy word line drive circuit 5. At time t0, the precharge is released, and thereafter the word line selected at time t1, for example, WL1, becomes "H". At the same time, the precharge of the selected dummy word line DWL1 is released.

Thus, the data of the memory cell MC driven by the selected word line WL1 is transferred to the bit line pair B.
L and bBL are read out to one bit line BL, and the other bit line bBL is supplied with a reference potential by coupling of the dummy cell DC. Selected memory cell M
In C, the potential of the bit line BL changes according to the data “1” and “0” due to the sharing of the charge with the bit line BL. If only charge sharing, data "1",
Although the bit line BL holds the precharge potential VBLH, the potential of the bit line BL actually changes due to coupling noise with the word line WL1 or the like. FIG. 4 shows a case where the bit line BL becomes slightly higher than the precharge potential. As for the bit line bBL, the bit line BL
Becomes a reference potential intermediate between the case where "1" is read out and the case where "0" is read out. Therefore, when the sense amplifier circuit 7 is activated at time t2, if the potential difference from the reference potential is larger than the sensitivity of the sense amplifier circuit,
“1” and “0” data are amplified, and in the case of “1” data, BL = VBLH and bBL = Vss. In the case of “0” data, BL = VSS and bBL as indicated by a broken line.
= VBLH.

Next, a method of setting the reference potential in this embodiment will be described. FIG. 5 shows operation waveforms of the auxiliary cell array 2 in the reference potential adjustment operation. During the precharge period until time t0, the precharge signal PRC is “L”, and the bit line pair BL and bBL of the auxiliary cell array 2
It is precharged to VBLH. During this time, the word line WL is at “L” and the dummy word line DWL is at VDWL.
H is precharged.

At time t0, the bit line precharge is released, and at the same time, the equalize signal EQL becomes "H" and the selected word line WL becomes "H". Although omitted in the figure, the column gate 10 is also in the all-selected state at the same time. Thereby, the bit line pair BL, bBL is connected to the equalizing circuit 2
2 is precharged / equalized to 1/2 VBLH. This potential is written to the memory cell MC selected by the word line WL.

At time t1, the equalizing operation and the operation of writing the equalizing potential to the memory cell are completed. Then, the bit line pair BL, bBL is precharged to VBLH again by the precharge signal PRC = "L".
Next, at time t2, the precharge operation is released, the same word line WL is selected with a slight delay, and the 1/2 VBLH
Is written to the bit line BL.
Read out. This becomes the reference reference potential Vref based on 1/2 VBLH generated by the bit line equalization. At the same time, the dummy word line DWL is pulled down from the precharge potential VDWLH, so that the other bit line bBL has the precharge potential V of the dummy word line DWL.
Reference potential Vrefd determined by the coupling between DWLH and dummy cell DC is applied.

By comparing the potentials Vref and Vrefd read to the bit line pair BL and bBL in this manner, it is possible to adjust the reference potential. Adjustment of the reference potential
In principle, when the reference potential Vrefd generated by the capacitive coupling type dummy cell DC is higher than the reference reference potential Vref, the high level potential VDWLH for driving the dummy word line DWL is raised, and the reference potential Vrefd is higher than the reference reference potential Vref. If low, the dummy word line DWL
Is performed by lowering the high-level potential VDWLH that drives.

More specifically, in this embodiment, the above-described reference potentials Vref and Vref obtained on bit line pair BL and bBL are used.
The difference of refd is detected and amplified by the sense amplifier circuit 9. That is, if Vrefd is higher than Vref, the bit line BL is amplified to Vss, the bit line bBL is amplified to VBLH, and if Vrefd is lower than Vref, the bit line BL is amplified.
Is amplified to VBLH, and the bit line bBL is amplified to Vss.

The above operation is performed simultaneously for all the bit line pairs of the auxiliary cell array 2. Then, the column gate 10 is turned on, and all sense results (or some sense results) of the auxiliary sense amplifier circuit 9 are stored in the data line D.
The data is sent to the majority circuit 11 via Q and bDQ, and a majority decision is made. The majority circuit 11 is a circuit that outputs “0” when “0” is large among input signals, and outputs “1” when “1” is large. If the number of input signals is even and “0” and “1” are the same, the output is made 2 bits, for example, “01”: “0”,
"10": "1", "00": same number.

FIGS. 6 to 8 show examples of the majority circuit 11. FIG. In these majority circuits, A, B, C and D are connected to a data line DQ, and / A, / B, / C and / D are connected to a data line bDQ.
Terminal. FIG. 6 shows a three-input majority circuit using a static combinational circuit.
If two ANDs B and C are "1", "1" is output.

FIG. 7 shows a four-input majority circuit using a dynamic combination circuit, in which a precharge period and a majority decision period alternate. During the precharge period in which the precharge signal PRC is “L”, the two outputs OUT
1 and OUT2 are both "0", resulting in a "00" data state. In the determination period in which the precharge signal PRC is “H”, according to the magnitude of the number of inputs “0” and “1”,
It becomes "01" or "10". If the inputs “0” and “1” are the same, “00” is held.

FIG. 8 shows a three-input majority decision circuit having a comparator configuration using an operational amplifier OP. Before sensing, the data lines DQ and bDQ are precharged to VBLH, the precharge is released, and the sense result is transferred. When the number of “1” s of A, B, and C is large, the operational amplifier O
The inverting input node of P becomes higher than the non-inverting input node, and the operational amplifier OP outputs “0”, and outputs “1” if “0” is more. Since this circuit compares the analog potentials, the number of inputs is even and "0",
Even when “1” has the same number, either “0” or “1” is output due to the variation of the element used, so that the case where “0” and “1” have the same number cannot be handled. .

If the output of the majority circuit 11 is "0",
Since Vrefd is higher than Vref, the dummy word line W
Raise the level of the DL precharge potential VDWLH,
If it is “0”, Vrefd is lower than Vref,
Control is performed to lower the level of the drive potential VDWLH of the dummy word line WDL. By such control, it is possible to generate a corrected reference potential by averaging the effects of coupling noise with the word line and variations in the threshold voltage of the transistors of the sense amplifier.

FIG. 9 shows a VD that specifically performs such control.
3 is a configuration example of a WLH generation circuit 13; The register 91 is
This is a holding circuit that holds the adjusted VDWLH value. The value of the register 91 is stored in the digital / analog converter 9
2 and output via a buffer 93. An up-counter 94, a down-counter 95, and a selector 96 are provided to adjust the value of the register 91 based on the result of the determination by the majority circuit 11. In the up counter 94 and the down counter 95, it is assumed that digital signals are generated by increasing the value of the register 91 adjusted last time by one and decreasing the value by one.

The decision result of the majority circuit 11 is "1",
“0” is input to the selector 96 as a selection signal (up-down signal updown). As a result, the value adjusted by the up counter 94 or the down counter 95 is selected and input to the register 91. Register 9
In addition, the signal of completion of majority decision is an update signal upda.
Enter as te. As described above, the register 91 is updated according to the result of the majority decision, the updated value is converted to an analog value, and is output as a new VDWLH value.

When the output of the majority circuit 11 is 1 bit, this may be used as it is as an up / down signal "update", and its output transition may be used as an update signal "update". When the output of the majority circuit 11 is 2 bits, the supply of the update signal update for the outputs out1 and out2 may be controlled by the combination circuit shown in FIG. That is, if either one of the outputs out1 and out2 is "1", the output "1" of the EXOR gate 101 activates the NAND gate 102, and otherwise, N
The AND gate 102 is made inactive. The upper bit may be used as the up / down signal updown, out of the 2-bit output. Accordingly, when the outputs out1 and out2 are “00” (the same number), the register 91 is not updated,
In the case of "01" or "10", the register 91 can be updated.

The initial value of the reference potential may be set by storing a test result at the time of evaluation in a nonvolatile storage element such as a fuse and writing the result in the register 91 of FIG. 9 at the time of adjustment. The reference potential adjustment procedure is performed a sufficient number of times at the time of device initialization (specifically, for example, [VDW
The reference potential can be initialized by repeating the above (resolution of LH generation circuit) × [output range]). By the adjustment at the time of initialization, it is possible to correct the deviation of the reference potential due to static factors such as process variation and aging.

The adjustment of the reference potential after initialization is performed, for example, in synchronization with refresh. Alternatively, it is also possible to have a unique timer independently of the refresh cycle and to periodically adjust the reference potential. This makes it possible to correct the deviation of the reference potential from the optimum value due to dynamic factors such as changes in temperature and voltage.

As described above, according to this embodiment, V
In a DRAM employing a BLH precharge method and using a capacitively coupled dummy cell, an auxiliary cell array is prepared, and a memory cell of the auxiliary cell array is Ｖ VBLH
And the level of the drive signal supplied to the dummy word line drive circuit so that the potential obtained when the intermediate potential is read out to the bit line is used as the reference potential. Thereby, the reference potential generated by using the coupling capacitance type dummy cell can be made the same as the reference potential generated by the conventional dummy cell. In this case, an optimum reference potential can be adjusted by preparing a plurality of pairs of bit lines in the auxiliary cell array and taking a majority decision on the sense result of the sense amplifier circuit of each bit line pair. In this embodiment, an equalizing circuit necessary for obtaining 1/2 VBLH on the auxiliary cell array side is not directly connected to the bit line pair of the auxiliary cell array but is connected via a selection gate. Therefore, the bit line capacity at the time of data sensing does not differ from that of a normal memory cell array, and high-speed sensing is possible.

[Second Embodiment] FIG. 11 shows a second embodiment.
1 shows a configuration of a DRAM. In the above embodiment, the auxiliary cell array 2 for adjusting the reference potential, which is independent of the normal memory cell array 1, is provided. In this embodiment, a dedicated auxiliary cell array is not used. However,
In the memory cell array 1, two spare word lines SWL0 and SWL1 are provided in the memory cell array 1 as additional rows in addition to the normal row addresses. The portions of the memory cells MC along these spare word lines SWL0 and SWL1 are expanded by sharing the bit line pairs with the original memory cell array 1 used to generate 1/2 VBLH for reference potential adjustment. Spare cell array 1a. Although the number of spare word lines may be one in principle, two spare word lines are used here in consideration of the capacity balance of the bit lines.

In this embodiment, reference potential adjustment is performed in the memory cell array 1 by performing writing and reading in an adjustment cycle different from that for normal access. The specific adjustment method is the same as in the previous embodiment. That is, Ｖ VBLH obtained by the bit line equalization is written to the memory cell MC selected by the spare word line SWL0 or SWL1. That is, this embodiment also has a bit line equalizing circuit 22 similar to that shown in FIG. Then, as described with reference to FIG. 5, the write data of 1/2 VBLH is read as Vref to one of the data line pair BL and bBL,
On the other hand, a reference potential Vrefd is generated by driving the dummy word line DWL0 or DWL1. By comparing these, the precharge potential of the dummy word line is adjusted. The use of the judgment by the majority circuit 11 for a plurality of bit line pairs is the same as in the previous embodiment.

In this embodiment, the column selection signal CSL is clocked while sequentially switching the column address, and the sense results can be sequentially taken out from a plurality of columns. In this case, the majority decision circuit 11 has a shift register 121 as shown in FIG.
May be provided. That is, the sense result is serially taken into the shift register 121 by the clock signal CLK synchronized with the column selection signal CSL. Then, the fetched data is input to the input of the majority circuit 11 in parallel. The control of the VDWLH generation circuit 13 by the output of the majority circuit 11 is the same as in the previous embodiment.

The method of FIG. 12 is effective when the number of bits used for determination is relatively small, but when the number of bits is large, the majority circuit 11 may be configured as shown in FIG. The majority decision circuit 11 has a register 131 capable of counting the number of inputs used for majority decision. Before the majority decision, the initial value selected by the selector 132 is written into the register 131 by raising the initialization signal init and the clock CLK.

The initial value of this register 131 is set to half of the number of inputs used for judgment. After the determination of the sensing result, the data Data of the sensing result is sequentially read in synchronization with the column selection signal CSL, and these are used as count-up signals and count-down signals of the up / down counters 133 and 134. That is, according to the read data Data,
The outputs of the up counter 133 and the down counter 134 are selected by the selector 135 and the register 131 is sequentially updated. Then, the comparison circuit 136 compares the finally updated value of the register 131 with the initial value. Thus, the comparison circuit 136 obtains a majority decision result of “1” if the value of the register 131 is larger than the initial value, and “0” if the value is smaller than the initial value. The control of the VDWLH generation circuit 13 based on this determination result is the same as in the previous embodiment.

According to this embodiment, the same effect as in the previous embodiment can be obtained. Unlike the previous embodiment, a dedicated auxiliary cell array for adjusting the reference potential is not required, so that the area occupied by the chip is small.
However, in the case of this embodiment, since the memory cell array 1 includes a spare cell array for adjusting the reference potential by sharing the bit line, it cannot be said that the reference potential adjustment is performed at an arbitrary timing. The potential adjustment is performed according to the refresh.

[Embodiment 3] FIG. 14 is a modification of the circuit configuration of FIG. 2 used in the above embodiments. That is, in this embodiment, the isolation gate NMOS transistors QN10, QN as a pair of switch elements driven by the isolation signal ISO are provided between the sense nodes SA, bSA of the sense amplifier circuit 7 and the bit lines BL, bBL.
N11 is interposed. The dummy cell DC is arranged not on the bit line side but on the sense amplifier circuit 7 side when viewed from the isolation gate transistors QN10 and QN11.

FIG. 15 shows operation waveforms at the time of data sensing in this embodiment. During the precharge period up to time t0, the bit line pair BL, bBL is precharged to VBLH, and the dummy word line DWL is precharged to VDWLH. During the precharge period, the separation signal ISO is “H”, and the bit line pair BL, bBL is connected to the sense nodes SA, bSA of the sense amplifier circuit 7.
After the precharge is released, the selected word line, for example, WL1 becomes "H" at time t1. As a result, the data of the memory cell MC selected by the word line WL1 is read to the bit line BL, and the potential of the bit line BL changes according to the data “1” and “0”. Dummy word line DWL
Has not been released yet at this point.

After that, at time t2, the separation signal ISO is set to "L" to separate the sense node of the sense amplifier circuit 7 from the bit lines BL and bBL, and then at time t3, the precharge of the dummy word line DWL1 is released. Thereby, the bit lines BL and bBL are connected to the sense nodes SA and bSA.
In this case, the potential of the sense node bSA is lowered by coupling of the dummy cell DC, and the reference potential is obtained. And then time t
In step 4, the sense amplifier circuit 7 is activated. Thus, the read “1” and “0” data are amplified with the bit line pair BL and bBL disconnected from the sense nodes SA and bSA of the sense amplifier circuit 7. In the case of "1" data, SA = VBLH, bSA = Vss. In the case of "0" data, SA = VSS, bSA as indicated by a broken line.
= VBLH. Thereafter, at time t5, the separation signal ISO is set to "H" again, whereby the sensed data is transferred to the bit lines BL and bBL and restored to the memory cell MC.

According to this embodiment, the dummy cell DC
Therefore, only the sense node of the sense amplifier circuit 7 performs the potential reduction due to the capacitance coupling, not the bit line. The capacity of the sense node is sufficiently smaller than the bit line capacity, and the read data is amplified while the bit line capacity is separated, so that high-speed sensing is possible. Further, since the capacity of the partner to which the dummy cell is capacitively coupled is small, the capacity of the dummy cell, and thus the area, can be reduced.

[Fourth Embodiment] FIG. 16 shows an embodiment in which the circuit configuration of FIG. 14 is slightly modified. In this embodiment, the isolation gate NMOS transistors QN10, QN
N11 can be controlled by separate isolation signal lines ISO1 and ISO2. As such a configuration,
As in the previous embodiment, in a state where the bit lines BL and bBL are separated from the sense nodes SA and bSA, a reference potential is applied to the reference bit line by coupling of the dummy cells DC to perform data sensing. At the time of data restoration, isolation gate transistors QN10, QN11
Turns on only the bit line to which the memory cell MC is connected, and keeps the reference bit line off. By performing such control, unnecessary charge / discharge on the reference bit line side can be eliminated, and power consumption can be reduced.

[0061]

As described above, according to the present invention, the reference potential generated by the coupling capacitance type dummy cell is optimally set on the basis of the reference potential generated by writing 1/2 VBLH into the memory cell. As a result, it is possible to eliminate the penalty of the access time required for generating the reference potential as in the related art.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of the memory cell array of the embodiment.

FIG. 3 is a diagram showing a specific configuration of an auxiliary cell array of the embodiment.

FIG. 4 is a diagram showing operation waveforms of data sensing according to the embodiment.

FIG. 5 is a diagram showing operation waveforms of reference potential adjustment according to the embodiment.

FIG. 6 is a diagram showing a configuration example of a majority circuit in the embodiment.

FIG. 7 is a diagram showing another configuration example of the majority circuit in the embodiment.

FIG. 8 is a diagram showing another example of the configuration of the majority circuit in the embodiment.

FIG. 9 is a diagram showing a configuration of a VDWLH generation circuit in the embodiment.

FIG. 10 is a diagram showing a modification of the update clock input unit of the VDWLH generation circuit.

FIG. 11 is a diagram showing a configuration of a DRAM according to another embodiment of the present invention.

FIG. 12 is a diagram showing a configuration example of a majority circuit in the embodiment.

FIG. 13 is a diagram showing another configuration example of the majority circuit in the embodiment.

FIG. 14 is a diagram showing a configuration of a DRAM according to another embodiment of the present invention.

FIG. 15 is a diagram showing operation waveforms of data sensing according to the embodiment.

FIG. 16 is a diagram showing a configuration of a DRAM according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Auxiliary cell array, 3 ... Row decoder, 4 ... Word line drive circuit, 5 ... Dummy word line drive circuit, 6 ... Column decoder, 7 ... Sense amplifier circuit, 8 ... Column gate, 9 ... Sense amplifier Circuit, 10 ...
Column gates, 11 majority circuit, 12 auxiliary cell array controller, 13 dummy word line high-level potential generation circuit.

Claims (13)

[Claims] 1. A semiconductor memory device comprising: a plurality of word lines; and a plurality of pairs of bit lines intersecting the word lines. Dynamic memory cells are arranged in a matrix at each intersection between the word lines and the bit line pairs. A memory cell array which is connected at least one by one and is driven by a dummy word line and provided with a capacitive coupling type dummy cell for generating a reference potential at one of a pair of bit lines; and detects and amplifies a potential difference between the bit line pair. A sense amplifier circuit, a precharge circuit for precharging the bit line pair to a high potential or a low potential having a bit line amplitude determined by an internal power supply supplied to the memory cell array, and selecting by driving the dummy word line A dummy word line drive circuit for generating a reference potential at one of the bit line pairs via the dummy cell. The semiconductor integrated circuit device characterized by having a reference potential adjusting circuit for adjusting the reference potential applied to one of said bit line pair by controlling a driving signal level of the word line drive circuit outputs. 2. The reference potential adjusting circuit writes an intermediate potential between a high potential and a low potential of a bit line amplitude in a predetermined memory cell, and makes the potential equal to a potential obtained when the intermediate potential is read out to a bit line. 2. The semiconductor integrated circuit device according to claim 1, wherein a level of a drive signal output from said dummy word line drive circuit is controlled. 3. The reference potential adjustment circuit detects and amplifies a potential difference between an auxiliary cell array provided independently of the memory cell array and independently accessed for reference potential adjustment, and a bit line pair of the auxiliary cell array. An auxiliary sense amplifier circuit; and, in accordance with a sense output obtained by the auxiliary sense amplifier circuit when writing and reading an intermediate potential between a high potential and a low potential of a bit line amplitude in a predetermined memory cell of the auxiliary cell array. 2. The semiconductor integrated circuit device according to claim 1, further comprising a dummy word line drive signal level generating circuit for generating a drive signal level to be output from the dummy word line drive circuit. 4. A signal line pair connected to a bit line pair of the auxiliary cell array via a selection gate is provided, and the signal line pair has a bit line pair at an intermediate potential of １ ／ of an internal power supply potential. 4. The semiconductor integrated circuit device according to claim 3, further comprising an equalizing circuit for precharging. 5. The auxiliary cell array is provided for a plurality of pairs of bit lines, a plurality of auxiliary sense amplifier circuits are provided corresponding to the plurality of pairs of bit lines, and the majority of the sense outputs of the plurality of auxiliary sense amplifier circuits are determined. 4. The semiconductor integrated circuit device according to claim 3, further comprising a majority circuit. 6. A spare word line parallel to a word line and extended by sharing a bit line pair in the memory cell array for adjusting a reference potential, and a memory cell selected thereby. A spare cell array having a memory cell, and an intermediate potential between a high potential and a low potential of a bit line amplitude written in a predetermined memory cell of the spare cell array. 2. The semiconductor integrated circuit device according to claim 1, further comprising a dummy word line drive signal level generation circuit for generating a drive signal level to be output by the word line drive circuit. 7. The semiconductor integrated circuit device according to claim 6, wherein said spare cell array is provided for two spare word lines. 8. A signal line pair connected to a bit line pair of the memory cell array via a selection gate is provided, and
7. The semiconductor integrated circuit device according to claim 6, wherein said signal line pair is provided with an equalizing circuit for precharging the bit line pair to an intermediate potential of 1/2 of the internal power supply potential. 9. A sense amplifier circuit provided for each bit line pair of said memory cell array when an intermediate potential between a high potential and a low potential of a bit line amplitude is written to a predetermined memory cell of said spare cell array and read out. 7. The semiconductor integrated circuit device according to claim 6, further comprising a majority circuit for taking a majority decision of the sense outputs obtained. 10. A set of switch elements for controlling conduction and non-conduction between a bit line pair of the memory cell array and each sense node of a sense amplifier circuit, and the dummy cell is connected to the switch 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is disposed closer to the sense amplifier circuit than the element. 11. A bit line pair is precharged with the set of switch elements turned on, and after the bit line pair is released from the precharge, the selected word line is driven to drive the bit line of the memory cell data. A read operation is performed on one of the pair, and thereafter, the switch element is turned off, and the pre-charge release of the selected dummy word line causes coupling of the reference potential by the dummy cell to the other of the bit line pair. The semiconductor integrated circuit device according to claim 10. 12. The set of switch elements is driven by separate control signal lines. When rewriting read data, the switch element on the data read side of the bit line pair is turned on, and the switch element on the reference side is turned on. 11. The semiconductor integrated circuit device according to claim 10, wherein the device is controlled so as to be kept off. 13. The precharge circuit precharges a pair of bit lines to an internal power supply potential, and the dummy word line drive circuit precharges a dummy word line to a high level potential, and precharges the precharge. 2. The semiconductor integrated circuit device according to claim 1, wherein the reference potential is generated by releasing the potential on the reference side of the bit line pair precharged via the dummy cell.