USRE45036E1 - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
- Publication number
- USRE45036E1 USRE45036E1 US13/779,097 US201313779097A USRE45036E US RE45036 E1 USRE45036 E1 US RE45036E1 US 201313779097 A US201313779097 A US 201313779097A US RE45036 E USRE45036 E US RE45036E
- Authority
- US
- United States
- Prior art keywords
- bit line
- voltage
- memory device
- semiconductor memory
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 239000000758 substrate Substances 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 description 47
- 230000003247 decreasing effect Effects 0.000 description 18
- 238000003491 array Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 14
- 101150055221 tbh-1 gene Proteins 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 8
- 102100026338 F-box-like/WD repeat-containing protein TBL1Y Human genes 0.000 description 7
- 101000835691 Homo sapiens F-box-like/WD repeat-containing protein TBL1X Proteins 0.000 description 7
- 101000835690 Homo sapiens F-box-like/WD repeat-containing protein TBL1Y Proteins 0.000 description 7
- 101000800590 Homo sapiens Transducin beta-like protein 2 Proteins 0.000 description 7
- 101150082572 TSB1 gene Proteins 0.000 description 7
- 101150020337 TSB2 gene Proteins 0.000 description 7
- 102100033248 Transducin beta-like protein 2 Human genes 0.000 description 7
- 230000004044 response Effects 0.000 description 7
- 108010077333 CAP1-6D Proteins 0.000 description 5
- 101000897856 Homo sapiens Adenylyl cyclase-associated protein 2 Proteins 0.000 description 5
- 101000836079 Homo sapiens Serpin B8 Proteins 0.000 description 5
- 101000798702 Homo sapiens Transmembrane protease serine 4 Proteins 0.000 description 5
- 102100029500 Prostasin Human genes 0.000 description 5
- -1 TBH2 Proteins 0.000 description 5
- 102100032471 Transmembrane protease serine 4 Human genes 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 108010031970 prostasin Proteins 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
Definitions
- the present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device for efficiently operating under a low power supply voltage condition.
- FIG. 1 is a block diagram showing a core area of a conventional semiconductor memory device.
- the conventional semiconductor memory device includes a row address input unit 20 , a column address input unit 30 , a cell area 100 and a data input/output unit 40 .
- the row address input unit 20 receives a row address and decodes the row address to output the decoded row address to the cell area 100 .
- the column address input unit 30 receives a column address and decodes the column address to output the decoded column address to the cell area 100 .
- the data input/output unit 40 outputs data stored in the cell area 100 and delivers data inputted through a data pad/pin into the cell area 100 .
- the cell area 100 includes a plurality of cell arrays, e.g., 110 , 120 , 130 and 140 and a plurality of sense amplifying blocks, e.g., 150 and 160 .
- Each of the plurality of cell arrays 110 to 140 includes a plurality of unit cells, each for storing data.
- Each of the bit line sense amplifying blocks 150 and 160 amplifies the data outputted from the plurality of cell arrays 110 to 140 to output the amplified data to the data input/output unit 40 .
- each of the bit line sense amplifying blocks 150 and 160 amplifies the data outputted from the plurality of cell arrays 110 to 140 to output the amplified data to the data input/output unit 40 . Otherwise, during a write operation, each of the bit line sense amplifying blocks 150 and 160 latches the data outputted from the data input/output unit 40 to output the latched data to the plurality of cell arrays 110 to 140 .
- FIG. 2 is a block diagram depicting a detailed structure of the cell area 100 shown in FIG. 1 .
- a plurality of unit cells e.g., CELL 1 , CELL 2 and CELL 3 , are provided with every intersection between a plurality of bit line pairs, e.g., BL and /BL, and a plurality of word lines, e.g., WL 0 to WL 5 .
- each unit cell is constituted with a capacitor and a transistor.
- a first cell CELL 1 includes a first capacitor C 0 and a first MOS transistor M 0 .
- the first capacitor C 0 is coupled between the first MOS transistor M 0 and a plate line PL.
- the first MOS transistor M 0 is coupled between the first capacitor C 0 and a bit line BL and has a gate coupled to a first word line WL 0 .
- the first cell CELL 1 and a second cell CELL 2 respectively coupled to the first word line WL 0 and a second word line WL 1 and neighbored with each other are commonly connected to the bit line BL; and the bit line BL is coupled to a sense amplifier 152 a included in the bit line sense amplifying block 150 .
- the first word line WL 0 is selected and activated; then, as a result, the first MOS transistor M 0 is turned on.
- the data stored in the first capacitor C 0 is delivered into the bit line BL.
- the sense amplifier 152 a senses and amplifies the data by using a potential difference between the bit line BL receiving the data delivered through the first MOS transistor M 0 and a bit line bar /BL receiving no data outputted from any cell included in the first cell array 110 .
- the amplified data is outputted through a local data bus line pair LDB and LDBB to the external circuit.
- the sense amplifier 152 a senses and amplifies the data on the bit line bar /BL as well as the data on the bit line BL to thereby transfer the data pair to the external circuit through the local data bus line pair LDB and LDBB.
- the bit line BL has a voltage level of a source voltage VDD and the bit line bar /BL has a voltage level of a ground voltage GND after the sensing and amplifying operations. Otherwise, if the first cell CELL 1 stores data being a logic low level “0”, i.e., the first capacitor C 0 is discharged, the bit line BL has a voltage level of the ground voltage GND and the bit line bar /BL has a voltage level of the source voltage VDD after the sensing and amplifying operations.
- the third word line WL 2 is selected and activated; then, as a result, the third MOS transistor M 2 is turned on.
- the data stored in the third capacitor C 2 is delivered into the bit line bar /BL.
- the sense amplifier 152 a senses and amplifies the data by using the potential difference between the bit line bar /BL receiving the data delivered through the third MOS transistor M 2 and the bit line BL receiving no data outputted from any cell included in the first cell array 110 .
- a word line corresponding to inputted row and column addresses is activated and, then, data stored in a cell coupled to the word line is sensed and amplified by the sense amplifier 152 a. After then, the amplified data is substituted with the inputted data. That is, the inputted data is latched in the sense amplifier 152 a. Next, the inputted data is stored in the unit cell corresponding to the activated word line. If it is completed to store the inputted data in the unit cell, the word line corresponding to the inputted row and column addresses is inactivated.
- FIG. 3 is a block diagram describing a connection between each cell array and each sense amplifying block included in the cell area 100 shown in FIG. 1 .
- the conventional semiconductor memory device has a shared bit line sense amplifier structure.
- the shared bit line sense amplifier structure means that two neighbor cell arrays are coupled to one sense amplifying block.
- the first sense amplifying block 150 is coupled to the first cell array 110 and the second cell array 130 ; and the second sense amplifying block 170 is coupled to the second cell array 130 and the fifth cell array 180 .
- each of the plurality of sense amplifying blocks 150 and 170 has a plurality of sense amplifiers.
- the number of plural sense amplifiers corresponds to the number of the bit line pair coupled to one cell array.
- the number of plural sense amplifiers corresponds to the number of two bit line pairs because two cell arrays hold one sense amplifying block in common for implementing a higher integrated circuit.
- the first sense amplifier 150 is provided with the first and the second cell arrays 110 and 130 in common.
- the first sense amplifying block 150 further includes first and second connection blocks 151 and 153 . Since the bit line sense amplifying block is commonly coupled to two neighbor cell arrays 110 and 130 , there should be control for connecting or disconnecting the first sense amplifying block 150 to one of the two neighbor cell arrays 110 and 130 .
- Each of the first and the second connection blocks 151 and 153 has a plurality of switching units, e.g., transistors.
- the plurality of transistors, e.g., MN 1 to MN 4 , in the first connection block 151 is turned on or off based on a first connection control signal BISH 1 ; and the plurality of transistors, e.g., MN 5 to MN 8 , in the second connection block 153 is turned on or off based on a second connection control signal BISL 1 .
- the first connection control signal BISH 1 is activated, all transistors included in the first connection block 151 is turned on, that is, the first cell array 110 is coupled to the sense amplifier block 152 of the first sense amplifying block 150 .
- the second connection control signal BISL 1 is activated, all transistors included in the second connection block 153 is turned on, that is, the second cell array 130 is coupled to the sense amplifier block 152 of the first sense amplifying block 150 .
- another sense amplifying block 170 includes a plurality of sense amplifiers and two connection blocks controlled in response to other connection control signals BISH 2 and BISL 2 for connecting or disconnecting a sense amplifier block of the bit line sense amplifying block 170 to one of the two neighbor cell arrays 130 and 180 .
- each sense amplifying block e.g., 150 and 170 , further includes a precharge block and a data output block besides the first and the second connection blocks 151 and 153 and sense amplifiers.
- FIG. 4 is a block diagram depicting the first sense amplifying block 150 shown in FIG. 2 .
- the bit line sense amplifying block 150 includes first and second connection blocks 151 a and 153 a, a sense amplifier 152 a, a precharge block 155 a, first and second equalization blocks 154 a and 157 a and a data output block 156 a.
- the sense amplifier 152 a amplifies the potential difference between the bit line BL and the bit line bar /BL based on first and second sense amplifier power supply signals SAP and SAN.
- the precharge block 155 a precharges the bit line pair BL and /BL as a bit line precharge voltage VBLP, enabled by a precharge signal BLEQ activated when the sense amplifier 152 a is inactivated.
- the first equalization block 154 a makes a voltage level of the bit line BL be same to a voltage level of the bit line bar /BL in response to the precharge signal BLEQ, wherein the bit line pair BL and /BL is coupled to the first cell array 110 (not shown).
- the second equalization block 157 a is also used for making a voltage level of the bit line BL be same to a voltage level of the bit line bar /BL in response to the precharge signal BLEQ, wherein the bit line pair BL and /BL is coupled to the second cell array 130 (not shown).
- the data output block 156 a outputs data amplified by the sense amplifier 152 a to the local data bus line pair LDB and LDBB based on a column control signal YI generated from the column address.
- bit line sense amplifying block 150 further includes first and second connection blocks 151 a and 153 a, each for connecting or disconnecting the sense amplifier 152 a to one of neighbor cell arrays respectively based on first and second connection control signals BISH and BISL.
- FIG. 5 is a waveform showing an operation of the conventional semiconductor memory device.
- FIGS. 1 to 5 the operation of the conventional semiconductor memory device is described in detail.
- the read operation can be split into four steps: a precharge step, a read step, a sense step and a restore step.
- the write operation is very similar to the read operation except that the write operation includes a write step instead of the read step in the read operation and, more minutely, a sensed and amplified data is not outputted but an inputted data from an external circuit is latched in the sense amplifier during the sense step.
- a capacitor of a unit cell is charged, i.e., stores a logic high level “1”. Also, it is assumed that during the read operation, the first connection block 151 a is enabled and the second connection block 153 a is disabled so that the sense amplifier 152 a is coupled to the first cell array 110 .
- bit line BL and the bit line bar /BL are precharged by the bit line precharge voltage VBLP. At this time, all word lines are inactivated.
- the precharge signal BLEQ is activated as a logic high level so that the first and the second equalization blocks 154 a and 157 a are also enabled.
- the bit line BL and the bit line bar /BL are percharged as the half of the core voltage VCORE.
- the first and the second connection block 151 a and 153 a are also activated, i.e., all transistors included in the first and the second connection block 151 a and 153 a are turned on.
- a symbol ‘SN’ means a potential level charged in the capacitor of the unit cell.
- ‘SN’ has a level of the core voltage VCORE as a logic high level “1”.
- a read command is inputted and carried out.
- the first connection block 151 a is coupled to the first cell array 110 and the second connection block 153 a is coupled to the second cell array 130 .
- the sense amplifier 152 a is coupled to the first cell array 110 and isolated from the second cell array 130 because the first connection block 151 a is activated and the second connection block 153 a is inactivated.
- the word line corresponding to the inputted row and column addresses is activated as a high voltage VPP until the restore step.
- the reason why the word line is activated as the high voltage VPP higher than the source voltage VDD that data stored in a capacitor with the logic high level “1” is reduced by the threshold voltages of a plurality of NMOS transistors constituting the unit cell during transferring to the bit line BL.
- the high voltage VPP which is higher than the core voltage VCORE supplied with the cell area of the semiconductor memory device, is generated for activating the word lines. As a result, it is possible to activate the word lines at a high speed.
- the word line is activated, a plurality of MOS transistors within the unit cell corresponding to the word line is turned on; and the data stored in the capacitor of the unit cell is delivered into the bit line BL.
- the bit line BL precharged as the half of the core voltage is boosted up by a predetermined voltage level ⁇ V.
- a voltage level of the bit line BL is increased not to the core voltage VCORE but to the predetermined voltage level ⁇ V because a capacitance Cc of the capacitor is smaller than a parasitic capacitance Cb of the bit line BL.
- the voltage level of the bit line BL is increased by the predetermined voltage level ⁇ V from the core voltage VCORE.
- a voltage level of the symbol ‘SN’ is also increased to the predetermined voltage level ⁇ V from the core voltage VCORE.
- bit line pair BL and /BL maintains a level of the half of the core voltage VCORE.
- the first sense amplifier power supply signal SAP is supplied with the core voltage VCORE and the second sense amplifier power supply signal SAN is supplied with the ground voltage GND.
- the sense amplifier can amplify a voltage difference, i.e., the potential difference, between the bit line BL and the bit line bar /BL by using the first and the second sense amplifier power supply signals SAP and SAN.
- a relatively high side between the bit line BL and the bit line bar /BL is amplified to the core voltage VCORE; and the other side, i.e., a relatively low side between the bit line BL and the bit line bar /BL, is amplified to the ground voltage GND.
- the voltage level of the bit line BL is higher than that of the bit line bar /BL. That is, after amplifying the bit line BL and the bit line bar /BL, the bit line BL is supplied with the core voltage VCORE and the bit line bar /BL is supplied with the ground voltage GND.
- the restore step the data outputted from the capacitor during the read step for boosting up the bit line BL by the predetermined voltage level ⁇ V is restored in the original capacitor. That is, the capacitor is re-charged.
- the word line corresponding to the capacitor is inactivated.
- the conventional semiconductor memory device carries out the precharge step again.
- the first and the second sense amplifier power supply signals SAP and SAN are respectively supplied with the half of the core voltage VCORE.
- the precharge signal BLEQ is activated and inputted to the first and the second equalization blocks 154 a and 157 a and the precharge block 155 a.
- the sense amplifier 152 a is coupled to the two neighbor cell arrays, e.g., 110 and 130 , by the first and the second connection blocks 151 a and 153 a.
- the semiconductor memory device includes an internal voltage generator for generating a core voltage VCORE having a lower voltage level than the source voltage VDD and a high voltage VPP having a higher voltage level than the core voltage VCORE.
- a requested operation speed can be achieved by implementing a nano-scale technology for manufacturing the semiconductor memory device through using above described manner for overcoming a decrease of the voltage level of the source voltage VDD without any other particular method.
- the requested operation speed can be achieved if the nano-scale technology is implemented based on from about 500 nm to about 100 nm. That is, as the nano-scale technology is upgraded, i.e., developed, a power consumption of a fabricated transistor included in the semiconductor memory device is reduced and, if the voltage level of the source voltage is not decreased, an operation speed of the fabricated transistor becomes faster.
- a requested voltage level of the source voltage becomes lower, e.g., from about 2.0 V to about 1.5 V or so far as about 1.0 V.
- the request about the source voltage cannot be achieved by only developing the nano-technology.
- a voltage level of the supply voltage inputted to the semiconductor memory device is lower than a predetermined voltage level, an operating margin of each transistor included in the semiconductor memory device is not sufficient; and, as a result, a requested operation speed is not satisfied and an operation reliability of the semiconductor memory device is not guaranteed.
- the sense amplifier needs more time for stably amplifying a voltage difference between the bit line BL and the bit line bar /BL because a predetermined turned-on voltage, i.e., a threshold voltage, of the transistor is remained under a low supply voltage.
- each voltage level of the bit line BL and the bit line bar /BL is fluctuated, i.e., increased or decreased by a predetermined level on the half of the core voltage VCORE. That is, as the voltage level of the source voltage becomes lower, a little noise can seriously affect the operation reliability of the semiconductor memory device.
- the semiconductor memory device As the semiconductor memory device is more integrated, a size of the transistor becomes smaller and a distance between a gate of the transistor and the bit line gets near more and more. As a result, a bleed current is generated.
- the bleed current means a kind of leakage current between the gate of the transistor and the bit line because of a physical distance between the gate of the transistor and the bit line under a predetermined value.
- FIG. 6 is a cross-sectional view describing a unit cell of the semiconductor memory device in order to show a cause of the bleed current.
- the unit cell includes a substrate 10 , an device isolation layer 11 , source and drain regions 12 a and 12 b, a gate electrode 13 , a capacitor 14 to 16 , a bit line 17 and insulation layers 18 and 19 .
- the symbol ‘A’ means a distance between the gate electrode 13 of the transistor and the bit line 17 .
- the distance between the gate electrode 13 of the transistor and the bit line 17 i.e., ‘A’, becomes shorter.
- the bit line BL is supplied with the half of the core voltage and the gate electrode 13 , i.e., a word line, is supplied with the ground voltage.
- the semiconductor memory device includes a plurality of additional unit cells for substituting the unit cell where the bit line and the gate electrode are short-circuited. At this time, unit cells having a defect are substituted with preliminary unit cells in word line basis.
- a resistor is added between the gate electrode of the transistor and the bit line.
- the resistor can reduce little amount of the bleed current, this is not effective and essential for reducing and protecting a flow of the bleed current.
- the conventional semiconductor memory device has another problem. That is, there exists a bleed current between a sense amplifier and a disconnected cell array.
- the other cell array is disconnected from the cell array by turning off a MOS transistor included in the corresponding connection block.
- a bit line pair of the disconnected cell array has a voltage level of about the half of the source voltage VDD; and one bit line and the other bit line of the sense amplifier have a voltage level of the source voltage VDD and a voltage level of the ground voltage GND respectively.
- the bleed current is flown from the disconnected cell array to the sense amplifier such as “Sub_Vt Leak Current” shown in FIG. 4 .
- This bleed current causes a current increase during a data access operation.
- an object of the present invention to provide a semiconductor memory device for operating in a fast speed under a low power condition and protecting a bleed current from generating to thereby reduce a power consumption.
- a layout of a sense amplifying block of the semiconductor memory device is provided.
- a semiconductor memory device having a folded bit line structure and operating with a source voltage and a ground voltage, including: a first first-type well including a first cell array for providing data to a first bit line or a first bit line bar selected among a plurality of bit lines, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period; a first second-type well including a first sense amplifying MOS transistor having a first-type channel among a plurality of sense amplifying MOS transistors for sensing and amplifying a signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor having a first-type channel for connecting or disconnecting the first bit line and the first bit line bar to or from the first sense amplifying MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel among the plurality of
- a semiconductor memory device device having a folded bit line structure and operating with a source voltage and a ground voltage, including: a first well including a first cell array for providing data to a first bit line or a first bit line bar selected among a plurality of bit lines; a second well including a second cell array for providing data to a second bit line or a second bit line bar selected among the plurality of bit lines; a third well including a first sense amplifying MOS transistor having a first-type channel among a plurality of sense amplifying MOS transistors provided in a bit line sense amplifier, a first connection unit for connecting or disconnecting the first bit line and the first bit line bar to or from the bit line sense amplifier, and a second connection unit for connecting or disconnecting the second bit line and the second bit line bar to or from the bit line sense amplifier; and a fourth well including a second sense amplifying MOS transistor having a second-type channel among the plurality of sense amplifying MOS transistors provided in
- FIG. 1 is a block diagram showing a core area of a conventional semiconductor memory device
- FIG. 2 is a block diagram depicting a detailed structure of the cell area shown in FIG. 1 ;
- FIG. 4 is a block diagram depicting the bit line sense amplifying block shown in FIG. 2 ;
- FIG. 5 is a waveform showing an operation of the conventional semiconductor memory device
- FIG. 6 is a cross-sectional view describing a unit cell of the semiconductor memory device in order to show a cause of a bleed current
- FIG. 7 is a block diagram showing a semiconductor memory device in accordance with an embodiment of the present invention.
- FIG. 8 is a schematic circuit diagram depicting a sense amplifying block of the semiconductor memory device shown in FIG. 7 ;
- FIG. 9 is a timing diagram showing an operation of the semiconductor memory device shown in FIGS. 7 and 8 ;
- FIG. 10 is a layout showing the bit line sense amplifying block of the semiconductor memory device shown in FIG. 8 ;
- FIG. 11 is cross-sectional view describing the layout of the bit line sense amplifying block shown in FIG. 10 .
- FIG. 7 is a block diagram showing a semiconductor memory device in accordance with an embodiment of the present invention.
- FIG. 8 is a schematic circuit diagram depicting a sense amplifying block of the semiconductor memory device shown in FIG. 7 .
- the semiconductor memory device has a folded bit line structure and operates by receiving a source voltage VDD and a ground voltage GND and includes a plurality of unit cells, each of which has an NMOS transistor and a capacitor.
- the semiconductor memory device includes a first cell array 300 a, a bit line sense amplifying block 200 and a first reference cell block 400 a.
- the first cell array 300 a stores data and outputs the data to a first bit line BL or a first bit line bar /BL selected among a plurality of bit lines provided in the plurality of unit cells.
- the bit line sense amplifying block 200 has a bit line sense amplifier 210 for sensing and amplifying a potential difference between data signals loaded on the first bit line BL and the first bit line bar /BL.
- the first reference cell block 400 a transfers a reference signal to the first bit line bar /BL when the data is outputted to the first bit line BL or to the first bit line BL when the data signal is outputted to the first bit line bar /BL.
- the bit line sense amplifying block 200 further includes a first precharge unit 220 a for equalizing the potential difference between the data signals of the first bit line BL and the first bit line bar /BL coupled to the first cell array 300 a at a precharge operation. That is, during the precharge operation, the first precharge unit 220 a floats the first bit line BL and the first bit line bar /BL by not proving a precharge voltage to the first bit line BL and the first bit line bar /BL.
- the first reference cell block 400 a includes a reference capacitor TOP_RC, a first reference switching NMOS transistor TOP_NM 1 and a second reference switching NMOS transistor TOP_NM 2 .
- the reference capacitor TOP_RC has one terminal coupled to a reference power supply terminal TOP_RPL.
- the first reference switching NMOS transistor TOP_NM 1 is located between the other terminal of the reference capacitor TOP_RC and the first bit line BL so as to connect the other terminal of the reference capacitor TOP_RC to the first bit line BL when the data signal is delivered to the first bit line bar /BL when the data signal is delivered to the first bit line BL.
- the second reference switching NMOS transistor TOP_NM 2 is located between the other terminal of the reference capacitor TOP_RC and the first bit line bar /BL so as to connect the other terminal of the reference capacitor TOP_RC to the first bit line bar /BL when the data signal is delivered to the first bit line BL.
- a capacitance of the reference capacitor TOP_RC is substantially same to that of a cell capacitor of the unit cell, e.g., CAP 1 and CAP 2 , included in the first cell array 300 a.
- a voltage level at the reference power supply terminal TOP_RPL can be one of the ground voltages, a half of the source voltage VDD and the source voltage VDD.
- the number of reference capacitors included in the first reference cell block 400 a corresponds to the number of bit line pairs included in a corresponding cell array, i.e., the first cell array 300 a. For instance, if the first cell array 300 a includes 256 bit line pairs, the first reference cell block 400 a includes 256 reference capacitors. Each reference capacitor is coupled to one of a corresponding bit line pair which carries no data signal to thereby deliver the reference signal stored in the reference capacitor to the coupled bit line.
- the bit line sense amplifying block 200 further includes a first connection unit 250 a connected between the bit line sense amplifier 210 and the first precharge unit 220 a for connecting or disconnecting the first bit line BL and the first bit line bar /BL included in the first cell array 300 a to/from the bit line sense amplifier 210 .
- the first connection unit 250 a includes a first connection PMOS transistor TBH 1 and a second connection PMOS transistor TBH 2 .
- the first connection PMOS transistor TBH 1 connects the first bit line BL to the bit line sense amplifier 210 in response to a first connection control signal BISH.
- the second connection PMOS transistor TBH 2 connects the first bit line bar /BL to the bit line sense amplifier 210 in response to the first connection control signal BISH.
- the bit line sense amplifying block 200 further includes a first auxiliary bit line sense amplifier 230 a for amplifying and maintaining a voltage level of a lower one of the first bit line BL and the first bit line bar /BL included between the first cell array 300 a and the first connection unit 250 a as a voltage level of the ground voltage GND.
- a first bit line control signal BLPD_H inputted to the first auxiliary bit line sense amplifier 230 a has a voltage level of the ground voltage GND while the bit line sense amplifier 210 is operated.
- the first auxiliary bit line sense amplifier 230 a includes a first auxiliary NMOS transistor TSB 1 and a second auxiliary NMOS transistor TSB 2 .
- the first auxiliary NMOS transistor TSB 1 has one terminal for receiving the first bit line control signal BLPD_H which is activated when the bit line sense amplifier 210 is enabled, and the other terminal coupled to the first bit line BL which is connected between the first cell array 300 a and the first connection unit 250 a.
- a gate of the first auxiliary NMOS transistor TSB 1 is coupled to the first bit line bar /BL connected between the first cell array 300 a and the first connection unit 250 a.
- the second auxiliary NMOS transistor TSB 2 has one terminal for receiving the first bit line control signal BLPD_H which is activated when the bit line sense amplifier 210 is enabled, and the other terminal coupled to the first bit line bar /BL connected between the first cell array 300 a and the first connection unit 250 a.
- a gate of the second auxiliary NMOS transistor TSB 2 is coupled to the first bit line BL connected between the first cell array 300 a and the first connection unit 250 a.
- the first precharge unit 220 a includes a first precharge NMOS transistor TP 1 for equalizing voltage levels of the first bit line BL and first bit line bar /BL in the first cell array 300 a based on a first precharge signal BLEQ_H.
- a cell array has a folded bit line structure and also has a shared bit line structure, i.e., a bit line sense amplifier is commonly coupled two neighboring cell arrays. Therefore, the semiconductor memory device further includes a second cell array 300 b coupled to the other side of the bit line sense amplifier 210 ; and a second connection unit 250 b for connecting or disconnecting the second cell array 300 b to/from bit line sense amplifier 210 .
- the second cell array 300 b stores data and outputs the data to a selected second bit line BOT_BL or a second bit line bar /BOT_BL.
- the second connection unit 250 b connects or disconnects the second bit line BOT_BL and the second bit line bar /BOT_BL to/from the bit line sense amplifier 210 .
- the semiconductor memory device further includes a second reference cell block 400 b and a second precharge unit 220 b.
- the second reference cell block 400 b transfers a reference signal to the second bit line bar /BOT_BL when the data signal is outputted to the second bit line BOT_BL or to the second bit line BOT_BL when the data signal is outputted to the second bit line bar /BOT_BL; and the second precharge unit 220 b equalizes a potential difference between the second bit line BOT_BL and the second bit line bar /BOT_BL included in the second cell array 300 b during the precharge operation.
- the second precharge unit 220 b floats the second bit line BOT_BL and the second bit line bar /BOT_BL by not proving the precharge voltage to the second bit line BOT_BL and the second bit line bar /BOT_BL during the precharge operation.
- the bit line sense amplifying block 200 further includes a second auxiliary bit line sense amplifier 230 b connected between the second cell array 300 b and the bit line sense amplifier 210 for amplifying and maintaining a voltage level of a lower one of the second bit line BOT_BL and the second bit line bar /BOT_BL included between the second cell array 300 b and the second connection unit 250 b as a voltage level of the ground voltage GND.
- a second auxiliary bit line sense amplifier 230 b connected between the second cell array 300 b and the bit line sense amplifier 210 for amplifying and maintaining a voltage level of a lower one of the second bit line BOT_BL and the second bit line bar /BOT_BL included between the second cell array 300 b and the second connection unit 250 b as a voltage level of the ground voltage GND.
- the second auxiliary bit line sense amplifier 230 b includes a third auxiliary NMOS transistor TSB 3 and a fourth auxiliary NMOS transistor TSB 4 .
- the third auxiliary NMOS transistor TSB 3 has one terminal for receiving a second bit line control signal BLPD_L which is activated when the bit line sense amplifier 210 is enabled, and the other terminal coupled to the second bit line BOT_BL connected between the second cell array 300 b and the second connection unit 250 b.
- a gate of the third auxiliary NMOS transistor TSB 3 is coupled to the second bit line bar /BOT_BL connected between the second cell array 300 b and the second connection unit 250 b.
- the fourth auxiliary NMOS transistor TSB 4 has one terminal for receiving the second bit line control signal BLPD_L which is activated when the bit line sense amplifier 210 is enabled, and the other terminal coupled to the second bit line bar /BOT_BL connected between the second cell array 300 b and the second connection unit 250 b.
- a gate of the fourth auxiliary NMOS transistor TSB 4 is coupled to the second bit line BOT_BL connected between the second cell array 300 b and the second connection unit 250 b.
- the second precharge blocks 220 b includes a second precharge NMOS transistor TP 2 for equalizing voltage levels of the second bit line BOT_BL and the second bit line bar /BOT_BL in the second cell array 300 b based on a second precharge signal BLEQ_L.
- bit line sense amplifier 210 includes first and second sense amplifying PMOS transistors TS 1 and TS 2 , and first and second sense amplifying NMOS transistors TS 3 and TS 4 .
- a gate of the first sense amplifying PMOS transistor TS 1 is connected to the first bit line bar /BL by the first connection unit 250 a or to the second bit line bar /BOT_BL by the second connection unit 250 b.
- One terminal of the first sense amplifying PMOS transistor TS 1 receives a first sense amplifier power supply signal SAP and the other terminal is connected to the first bit line BL by the first connection unit 250 a or to the second bit line BOT_BL by the second connection unit 250 b.
- a gate of the second sense amplifying PMOS transistor TS 2 is connected to the first bit line BL by the first connection unit 250 a or to the second bit line BOT_BL by the second connection unit 250 b.
- One terminal of the second sense amplifying PMOS transistor TS 2 receives the first sense amplifier power supply signal SAP and the other terminal is connected to the first bit line bar /BL by the first connection unit 250 a or to the second bit line bar /BOT_BL by the second connection unit 250 b.
- a gate of the first sense amplifying NMOS transistor TS 3 is connected to the first bit line bar /BL by the first connection unit 250 a or to the second bit line bar /BOT_BL by the second connection unit 250 b.
- One terminal of the first sense amplifying NMOS transistor TS 3 receives a second sense amplifier power supply signal SAN and the other terminal is connected to the first bit line BL by the first connection unit 250 a or to the second bit line BOT_BL by the second connection unit 250 b.
- a gate of the second sense amplifying NMOS transistor TS 4 is connected to the first bit line BL by the first connection unit 250 a or to the second bit line BOT_BL by the second connection unit 250 b.
- One terminal of the second sense amplifying NMOS transistor TS 4 receives the second sense amplifier power supply signal SAN and the other terminal is connected to the first bit line bar /BL by the first connection unit 250 a or to the second bit line bar /BOT_BL by the second connection unit 250 b.
- the first sense amplifier power supply signal SAP is supplied with the source voltage VDD and the second sense amplifier power supply signal SAN is supplied with a low voltage VBB.
- the low voltage VBB has a lower voltage level than the ground voltage GND having a voltage level of about ⁇ 0.5 V.
- the bit line sense amplifier 210 performs a sensing and amplifying operation by using the low voltage VBB and the source voltage VDD.
- the semiconductor memory device further includes a data input/output unit 240 for outputting data sensed and amplified by the bit line sense amplifier 210 through a local data bus line pair LDB and LDBB to an external circuit, and for delivering data inputted from the external circuit via the local data bus line pair LDB and LDBB to the bit line sense amplifier 210 .
- a data input/output unit 240 for outputting data sensed and amplified by the bit line sense amplifier 210 through a local data bus line pair LDB and LDBB to an external circuit, and for delivering data inputted from the external circuit via the local data bus line pair LDB and LDBB to the bit line sense amplifier 210 .
- the data input/output unit 240 includes first and second input/output MOS transistors T 01 and T 02 .
- a gate of the first input/output MOS transistor T 01 receives a column control signal YI.
- One terminal of the first input/output MOS transistor T 01 is connected to the first and the second bit lines BL and BOT_BL and the other terminal of the first input/output MOS transistor T 01 is coupled to a first local data bus line LDB.
- a gate of the second input/output MOS transistor T 02 receives the column control signal YI; and one terminal of the second input/output MOS transistor T 02 is connected to the first and the second bit line bars /BL and /BOT_BL and the other terminal of the second input/output MOS transistor T 02 is coupled to a second local data bus line LDBB.
- FIG. 9 is a timing diagram showing an operation of the semiconductor memory device shown in FIGS. 7 and 8 .
- the semiconductor memory device includes a reference cell block to float a bit line and a bit line bar by not proving the precharge voltage to the bit line and the bit line bar during a precharge step.
- the bit line sense amplifier performs a sensing and amplifying operation by not using the source voltage VDD and the ground voltage GND, but using the source voltage VDD and the low voltage VBB having the lower voltage level than the ground voltage GND, i.e., the voltage level of about ⁇ 0.5 V, and the source voltage VDD.
- a voltage level of the precharge voltage of the bit line can be maintained as the ground voltage GND by making voltage levels of two bit lines be same after a sensing operation of the bit line sense amplifier.
- the semiconductor memory device further includes an auxiliary bit line sense amplifier for maintaining a voltage level of a neighboring bit line pair as a half of the source voltage VDD by using the reference cell block and a precharge unit when the bit line sense amplifier is operated for a data access.
- a data access operation of the semiconductor memory device can be split into four steps: a precharge step, a read/write step, a sense step and a restore step.
- the first and the second precharge signals BLEQ_H and BLEQ_L are activated and maintain an enable state as a voltage level of a high voltage VPP so that voltage levels of a first bit line pair BL and /BL is equalized and voltage levels of a second bit line pair BOT_BL and /BOT_BL is also equalized.
- the precharge voltage is not supplied with the first bit line pair BL and /BL during the precharge step
- the first bit line pair BL and /BL, a sense amplifier bit line pair SA_BL and SA_/BL and the second bit line pair BOT_BL and /BOT_BL is floated (t 0 ).
- the first and the second connection units 250 a and 250 b are turned on; and the ground voltage GND is supplied with all word lines to thereby maintain an inactivated state.
- the first bit line pair BL and /BL, the sense amplifier bit line pair SA_BL and SA_/BL and the second bit line pair BOT_BL and /BOT_BL keeps a voltage level of a half of the source voltage VDD at the precharge step by using the first and the second precharge units 220 a and 220 b right after a read/write operation is performed (After a sensing and amplifying operation is performed by the bit line sense amplifier 210 , one of a bit line pair has a voltage level of the source voltage VDD and the other has a voltage level of the ground voltage GND).
- the bit line voltage level of the half of the source voltage VDD is decreased as a period of the precharge step is longer. If the precharge step is more continuously performed so as not to enter the read/write step, the voltage level of the first bit line pair BL and /BL and the sense amplifier bit line pair SA_BL and SA_/BL is decreased to the ground voltage GND.
- a precharge voltage of each floated bit line has a variable voltage level between the half of the source voltage VDD and the ground voltage GND.
- a timing of performing the read/write operation determines the precharge voltage of each floated bit line.
- a single word line is selected by decoding inputted column and row addresses. All of the NMOS transistors corresponding to the selected word line are turned on and data stored in the cell capacitor is transferred to the first bit line BL through the turned-on NMOS transistor.
- a reference signal is inputted to the first bit line bar /BL and the sense amplifier bit line bar SA_/BL which have no data signal.
- a first reference word line bar /TOP_RWL having no data signal is activated and, thus, the second reference switching NMOS transistor TOP_NM 2 is turned on. Accordingly, the reference signal stored in the reference capacitor TOP_RC is transferred to the first bit line bar /BL and the sense amplifier bit line bar SA_/BL and, thus, voltage levels of the first bit line bar /BL and the sense amplifier bit line bar SA_/BL are increased by an amount of a predetermined voltage level.
- the capacitance of the reference capacitor TOP_RC is substantially same to that of the cell capacitor of the unit cell, e.g., CAP 1 and CAP 2 .
- a charge amount of the reference capacitor TOP_RC which stores the reference signal is a half of a charge amount of the cell capacitor of the unit cell, e.g., CAP 1 and CAP 2 , which stores the high-level data ‘1’.
- reference power supply terminals i.e., HALF_VDD, TOP_RPL and BOT_RPL
- the charge amount of the reference capacitor TOP_RC which stores the reference signal is the half of the charge amount of the cell capacitor of the unit cell which stores the high-level data ‘1’.
- each of voltage levels supplied by the reference power supply terminals TOP_RPL and BOT_RPL is same to a voltage level of a plate voltage PL supplied with the cell capacitor of the unit cell, e.g., CAP 1 and CAP 2 , included in a cell array.
- the voltage level can have a voltage level of the source voltage VDD, a half of the source voltage VDD or the ground voltage GND.
- a voltage level which is same to the plate voltage PL is supplied to the reference power supply terminals TOP_RPL and BOT_RPL so that the reference signal can have a half signal level of the high-level data.
- the signal level increase of the first bit line bar /BL which receives the reference signal is a half of that of the first bit line BL which receives the high-level data.
- the first bit line pair BL and /BL has a voltage level of about 0.5V at an initial state of the precharge step. Thereafter, as the precharge step is continued, it is assumed that each of the voltage levels of the first bit line pair BL and /BL is decreased to about 0.3V.
- the voltage level of the first bit line BL having the high-level data is increased to about 0.5V, i.e., 0.3V+0.2V, and the voltage level of the first bit line bar /BL having the reference signal which has the half signal level of the high-level data is increased to 0.4V, i.e., 0.3V+0.1V.
- the first precharge signal BLEQ_H is activated so as to enable the first precharge unit 220 a during the precharge step and is inactivated so as to disable the first precharge unit 220 a during the read, sense and restore steps.
- the first sense amplifier power supply signal SAP of the bit line sense amplifier 210 receives the source voltage VDD and the second sense amplifier power supply signal SAN receives a first negative low voltage VBB_H.
- the bit line sense amplifier 210 senses a voltage difference between the first bit line pair BL and /BL to thereby amplify a voltage level of a bit line having a higher voltage level, i.e., the first bit line BL, to a voltage level of the source voltage VDD and amplify a voltage level of a bit line having a lower voltage level, i.e., the first bit line bar /BL, to a voltage level of the ground voltage GND (t 2 ).
- the bit line sense amplifier 210 performs the amplifying operation by using the source voltage VDD and the first negative low voltage VBB_H, the amplifying operation can be performed at a high speed in comparison with using the source voltage VDD and the ground voltage GND.
- a voltage level of the sense amplifier bit line bar SA_/BL included between the bit line sense amplifier 210 and the first connection unit 250 a is amplified to the first negative low voltage VBB_H; however, the first bit line bar /BL included between the first cell array 300 a and the first auxiliary bit line sense amplifier 230 a is amplified to the ground voltage GND.
- the first connection control signal BISH inputted to each gate of the first and the second connection PMOS transistors TBH 1 and TBH 2 included in the first connection unit 250 a has a voltage level of the first negative low voltage VBB_H, even though the sense amplifier bit line bar SA_/BL coupled to the bit line sense amplifier 210 is amplified to the first negative low voltage VBB_H, the first bit line bar /BL coupled to the first cell array 300 a is amplified to the ground voltage GND which is higher than the first negative low voltage VBB_H.
- the second connection unit 250 b performs a clamping operation so that a voltage level of the first negative low voltage VBB_H is not transferred to a bit line coupled to the second cell array 300 b even though the bit line sense amplifier 210 amplifies the sense amplifier bit line bar SA_/BL to the first negative low voltage VBB_H. Also, since a parasitic capacitance occurred in the first bit line bar /BL is relatively larger than a sub-threshold voltage of the first and the second connection PMOS transistors TBH 1 and TBH 2 included in the first connection unit 250 a, the first bit line bar /BL coupled to the first cell array 300 a can keep the voltage level of the ground voltage GND during the sense step and the restore step.
- bit line pair coupled to a cell array can keep the voltage level of the ground voltage GND by preventing the first negative low voltage VBB_H amplified by the bit line sense amplifier 210 from being transferred to the bit line pair, a voltage variation of each bit line is minimized. As a result, an operational speed of the bit line sense amplifier 210 can be improved and a power consumption due to the voltage variation of each bit line coupled to each cell array can be reduced.
- the first and the second connection units 250 a and 250 b are provided not only for controlling the connection between the bit line sense amplifier 210 and each cell array but also for preventing the first negative low voltage VBB_H from being transferred to the first bit line pair BL and /BL, the second bit line pair BOT_BL and /BOT_BL included in each cell array.
- the first and the second connection units 250 a and 250 b are not enough for stably maintaining the voltage level of the first bit line pair BL and /BL included in the cell array as the ground voltage GND. Therefore, the first and the second auxiliary bit line sense amplifiers 230 a and 230 b are provided for maintaining the voltage level of the first bit line pair BL and /BL included in the first cell array 300 a as the ground voltage GND even though the sense amplifier bit line pair SA_BL and SA_/BL coupled to the bit lines sense amplifier 210 are amplified to the first negative low voltage VBB_H.
- the first and the second auxiliary bit line sense amplifiers 230 a and 230 b amplify and maintain one of the first bit line pair BL and /BL included in the first cell array 300 a, which has a lower voltage level than the other, as the voltage level of the ground voltage GND while the bit line sense amplifier 210 performs the sensing and amplifying operation.
- the bit line sense amplifier 210 when the bit line sense amplifier 210 amplifies a voltage level of the sense amplifier bit line SA_BL to the source voltage VDD and amplifies a voltage level of the sense amplifier bit line bar SA_/BL to the first negative low voltage VBB_H, the first bit line BL keeps a voltage level of the source voltage VDD and the first bit line bar /BL keeps a voltage level of the ground voltage GND.
- the first auxiliary bit line sense amplifier 230 a decreases a voltage level of the first bit line bar /BL so as to be the ground voltage GND when a voltage level of the first bit line bar /BL is higher than the ground voltage GND and increases a voltage level of the first bit line bar /BL so as to be the ground voltage GND when a voltage level of the first bit line bar /BL is lower than the ground voltage GND.
- first and the second bit line control signals BLPD_H and BLPD_L respectively inputted to the first and the second auxiliary bit line sense amplifiers 230 a and 230 b are activated as the ground voltage GND during an activation period of the bit line sense amplifier 210 , i.e., t 2 , t 3 and t 4 .
- gates of the first and the second auxiliary NMOS transistors TSB 1 and TSB 2 included in the first auxiliary bit line sense amplifier 230 a are cross-coupled to the first bit line pair BL and /BL.
- Each one terminal of the first and the second auxiliary NMOS transistors TSB 1 and TSB 2 receive the ground voltage GND as the first bit line control signal BLPD_H to thereby maintain a lower voltage level of the first bit line pair BL and /BL as the ground voltage GND due to the cross-coupled gates of the first and the second auxiliary NMOS transistors TSB 1 and TSB 2 .
- gates of the third and the fourth auxiliary NMOS transistors TSB 3 and TSB 4 included in the second auxiliary bit line sense amplifier 230 b are cross-coupled to the second bit line pair BOT_BL and /BOT_BL.
- Each one terminal of the third and the fourth auxiliary NMOS transistors TSB 3 and TSB 4 receive the ground voltage GND as the second bit line control signal BLPD_L to thereby maintain a lower voltage level of the second bit line pair BOT_BL and /BOT_BL as the ground voltage GND due to the cross-coupled gates of the third and the fourth auxiliary NMOS transistors TSB 3 and TSB 4 .
- each unit cell included in each cell array is constituted with the NMOS transistor, i.e., TC 1 and TC 2 , and the cell capacitor, i.e., CAP 1 and CAP 2 , if the first negative low voltage VBB_H is transferred to the bit line included in the cell array when the bit line sense amplifier amplifies a bit line pair to the source voltage VDD and the first negative low voltage VBB_H, the NMOS transistor in the unit cell is turned on and data of an unselected unit cell may be lost. Therefore, it is required that the first negative low voltage VBB_H amplified by the bit line sense amplifier is not delivered to the bit line included in the cell array while the bit line sense amplifier is operated.
- each of the first and the second connection control signals BISH and BISL inputted to the first and the second connection unit 250 a and 250 b has two voltage levels: one is the first negative low voltage VBB_H having a negative voltage level whose absolute quantity is equal to each threshold voltage of a first and a fourth PMOS connection transistors TBH 1 , TBH 2 , TBL 1 and TBL 2 included in the first and the second connection units 250 a and 250 b and the other is a second negative low voltage VBB_L having a negative voltage level whose absolute quantity is larger than that of the first to the fourth connection PMOS transistors TBH 1 , TBH 2 , TBL 1 and TBL 2 .
- the first and the second connection control signals BISH and BISL are inputted as the first negative low voltage VBB_H for equalizing voltage levels of each bit line pair included in the first and the second cell arrays 300 a and 300 b, e.g., the first bit line pair BL and /BL, during the precharge step.
- the second connection control signal BISL is provided as the source voltage VDD to disable the second connection unit 250 b and the first connection control signal BISH is activated as a voltage level of the second negative low voltage VBB_L to enable the first connection unit 250 a.
- the activated first connection control signal BISH is provided as the first negative low voltage VBB_H.
- the relatively lower low voltage i.e., the second negative low voltage VBB_L
- the relatively higher low voltage i.e., the first negative low voltage VBB_H
- the bit line sense amplifier 210 which uses the first negative low voltage VBB_H, to perform the sensing and amplifying operation more quickly when the bit line sense amplifier 210 mainly performs the sensing and amplifying operation.
- a column control signal YI is activated for a predetermined time. Then, in response to the column control signal YI, a data signal latched by the bit line sense amplifier 210 is outputted to the local data bus line pair LDB and LDBB (t 3 ). At this time, the outputted data signal is data corresponding to the read command.
- the data signal is restored to an original unit cell by using the data signal latched by the bit line sense amplifier 210 (t 4 ).
- a corresponding word line i.e., WL 1 and WL 2
- the first and the second sense amplifier power supply signals SAP and SAN are respectively supplied with the ground voltage GND and the half of the source voltage VDD so that the bit line sense amplifier 210 is disabled.
- a voltage level of a bit line (the sense amplifier bit line bar SA_/BL in this case) amplified to the ground voltage GND by the bit line sense amplifier 210 is increased to a predetermined voltage level during transferring the data amplified by the bit line sense amplifier 210 . Accordingly, an enough time for the restore time should be provided for the increased voltage level of the sense amplifier bit line bar SA_/BL to be decreased to the ground voltage GND. Otherwise, a wrong data can be restored to the original unit cell; particularly, if an original data is ‘0’, the original data is restored as ‘1’.
- a period of the restore step (t 4 ) should be long.
- the sense amplifier bit line bar SA_/BL is amplified to the first negative low voltage VBB_H lower than the ground voltage GND by the bit line sense amplifier 210 , even though a current is flown to the first bit line bar /BL coupled to the bit line sense amplifier 210 by the local data bus line pair LDB and LDBB, a voltage level of the first bit line bar /BL coupled to the bit line sense amplifier 210 is not increased or at least not higher than the ground voltage GND because the flown current is compensated by the sense amplifier bit line bar SA_/BL having the first negative low voltage VBB_H. Accordingly, the period of the restore step (t 4 ) can be decreased in comparison with the conventional invention.
- the first bit line pair BL and /BL has a same voltage level to be floated.
- the first and the second connection signals BISH and BISL are provided as the first negative low voltage VBB_H and, thus, all of the bit lines BL, SA_BL, BOT_BL, /BL, SA_/BL and /BOT_BL are connected (t 5 ).
- the first bit line pair BL and /BL keeps the voltage level of the half of the source voltage VDD; however, each voltage level of the first bit line pair BL and /BL is decreased as time passes because the first bit line pair BL and /BL is floated not receiving a particular precharge voltage.
- the second reference cell block 400 b and the second precharge unit 220 b are enabled so that each voltage level of the second bit line pair BOT_BL and /BOT_BL is maintained as the precharge voltage.
- the bit line pair is floated not being supplied with a special precharge voltage. Therefore, there is no particular precharge voltage which all of the bit lines keep at the precharge step.
- the precharge voltage means a half of the source voltage VDD which a bit line pair maintains when the bit line pair has a same voltage level after one of the bit line pair has a voltage level of the source voltage VDD and the other has a voltage level of the ground voltage GND after performing a data read or write operation. That is, while the bit line sense amplifier 210 accesses data of a unit cell, a voltage level of the bit line pair which shares the bit line sense amplifier 210 and is not connected to the bit line sense amplifier 210 is maintained as the half of the source voltage VDD by using a corresponding precharge unit and a reference cell block.
- first and the second connection unit 250 a and 250 b include the first to fourth connection PMOS transistors TBH 1 , TBH 2 , TBL 1 and TBL 2 which receive one of the first and the second connection control signals BISL and BISH between the first and the second sense amplifier power supply signals SAP and SAN and the bit line of the inactivated cell array, and even though the PMOS transistors are turned off, a sub-current still flows and the bit line included in the inactivated cell array is rapidly decreased due to a leakage current of the sub-current. If a size of the PMOS transistor is larger, the above-mentioned problem becomes more serious.
- the semiconductor memory device keeps the precharge voltage as the half of the source voltage VDD.
- the bit line sense amplifier senses and amplifies a voltage difference between a bit line pair coupled to one side of the bit line sense amplifier for a data accessing
- the other bit line pair which does not serve to access data and is coupled to the other side of the bit line sense amplifier keeps a precharge voltage level as the half of the source voltage VDD. In this time, there occurs an error since the precharge voltage level is decreased due to a voltage difference between the precharge voltage and a ground voltage supply terminal of the bit line.
- the bit line pair which does not serve to access the data is floated at the precharge step, the above-mentioned problem does not occur.
- the precharge voltage is maintained as the half of the source voltage VDD, the data access operation can be performed more effectively since the precharge voltage level of the half of the source voltage VDD is the most effective for sensing a high-level data and a low-level data.
- the semiconductor memory device in accordance with the present invention maintains a voltage level of a bit line pair which neighbors with the bit line pair served for a data access as the half of the source voltage VDD by using the corresponding reference cell block and the corresponding precharge unit, all of bit line pairs which neighbor with the bit line pair for data accessing can keep a voltage level of the half of the source voltage VDD. Accordingly, the precharge voltage can be secured no generating a particular control signal.
- a cell capacitor of a selected unit cell is discharged. Accordingly, a voltage level of the first bit line BL receiving the low-level data is not changed at the read step after the precharge step, i.e., t 1 . That is, the voltage level of the first bit line BL keeps a voltage level of the ground voltage GND.
- a voltage level of the first bit line bar /BL is increased by a predetermined voltage level.
- an amount of the voltage increase of the first bit line bar /BL is determined by a charge quantity corresponding to the reference signal, i.e., a charge quantity stored in the reference capacitor TOP_RC.
- the bit line sense amplifier 210 senses the voltage difference between the first bit line BL and the first bit line bar /BL to amplify the voltage level of the first bit line BL to the ground voltage GND and the voltage level of the first bit line bar /BL to the source voltage VDD respectively, then, the bit line sense amplifier 210 latches the amplified voltage levels.
- the voltage level of the first bit line BL included in the first cell array 300 a is maintained as the ground voltage GND by the first connection unit 250 a.
- FIGS. 8 and 9 an operation of the semiconductor memory device for writing data can be also described as shown in FIGS. 8 and 9 .
- the write operation is very similar to the read operation. While a data signal sensed and amplified by the bit line sense amplifier 210 is outputted to the local data bus line pair LDB and LDBB during t 3 , a data signal inputted in response to a write command is transferred to the bit line sense amplifier 210 through the local data bus line pair LDB and LDBB at the write operation.
- bit line sense amplifier 210 replaces a previously latched data signal with the delivered data signal, and the newly latched data signal is stored to a unit cell at the restore step (t 4 ).
- the bit line sense amplifier 210 also performs a sensing and amplifying operation by using the source voltage VDD and the first negative low voltage VBB_H at the write operation.
- the semiconductor memory device floats each of the first bit line pair BL and /BL at the precharge step, and the bit line sense amplifier 210 senses and amplifies a voltage difference between the first bit line pair BL and /BL by using the source voltage VDD and the first negative low voltage VBB_H.
- FIG. 10 is a layout showing the bit line sense amplifying block 200 of the semiconductor memory device shown in FIG. 8 .
- FIG. 11 is cross-sectional view describing the layout of the bit line sense amplifying block 200 shown in FIG. 10 .
- the layout of the semiconductor memory device can be implemented as shown in FIGS. 10 and 11 .
- the semiconductor memory device in accordance with the present invention has a folded bit line structure and operates by receiving a source voltage VDD and a ground voltage GND.
- the semiconductor memory device includes a first P-well PW_ 1 , a second P-well PW_ 2 and, a second N-well NW_ 2 .
- the first P-well PW_ 1 includes a first cell array and a first precharge NMOS transistor TP 1 .
- the first cell array stores data and outputs the data to one of the first bit line BL and the first bit line bar /BL selected among the plurality of bit lines provided in the plurality of unit cells.
- the first precharge NMOS transistor TP 1 having an N-channel equalizes voltage levels of the first bit line pair BL and /BL in the first cell array during a precharge step.
- the second N-well NW_ 2 includes first and second sense amplifying PMOS transistors TS 1 and TS 2 , and first and second connection PMOS transistors TBH 1 and TBH 2 .
- the first and the second sense amplifying PMOS transistors TS 1 and TS 2 having a P-channel, among a plurality of sense amplifying MOS transistors, senses and amplifies a signal difference between the first bit line BL and the first bit line bar /BL.
- the first and the second connection PMOS transistors TBH 1 and TBH 2 having a P-channel connects or disconnects the first bit line pair BL and /BL from/to the first and the second sense amplifying PMOS transistors TS 1 and TS 2 .
- the second P-well PW_ 2 includes first and second sense amplifying NMOS transistors TS 3 and TS 4 have an N-channel among the plurality of sense amplifying MOS transistors for sensing and amplifying the signal difference between the first bit line pair BL and /BL.
- the semiconductor memory device floats the first bit line pair BL and /BL by not proving a special precharge voltage to the first bit line pair BL and /BL during the precharge step.
- the first and the second sense amplifying PMOS transistors TS 1 and TS 2 having the P-channel perform a sensing and amplifying operation by using the low voltage VBB having the lower voltage level than the ground voltage GND
- the first and the second sense amplifying NMOS transistors TS 3 and TS 4 having the N-channel perform a sensing and amplifying operation by using the source voltage VDD or a high voltage VPP having the higher voltage level than the source voltage VDD.
- the first P-well PW_ 1 further includes first and second auxiliary MOS transistors TSB 1 and TSB 2 having an N-channel for sensing and amplifying a lower voltage level of the first bit line pair BL and /BL, which is located between the first cell array and the first and the second connection PMOS transistors TBH 1 and TBH 2 , as the voltage level of the ground voltage GND.
- the semiconductor memory device in accordance with the present invention further includes a third P-well PW_ 3 .
- the third P-well PW_ 3 includes a second cell array and a second precharge NMOS transistor TP 2 .
- the second cell array stores data and outputs the data to one of the second bit line BOT_BL and the second bit line bar /BOT_BL selected among a plurality of bit lines provided in the plurality of unit cells.
- the second precharge NMOS transistor TP 2 having an N-channel equalizes voltage levels of the second bit line pair BOT_BL and /BOT_BL in the second cell array during the precharge step.
- the second N-well NW_ 2 further includes third and fourth connection PMOS transistors TBL 1 and TBL 2 having a P-channel for connecting or disconnecting the second bit line pair BOT_BL and /BOT_BL to the first and the second sense amplifying PMOS transistors TS 1 and TS 2 , and the first and the second sense amplifying NMOS transistors TS 3 and TS 4 .
- the second N-well NW_ 2 includes the first to the fourth connection PMOS transistors TBH 1 , TBH 2 , TBL 1 and TBL 2 , and the first and the second sense amplifying PMOS transistors TS 1 and TS 2 .
- the second P-well PW_ 2 includes the first and the second sense amplifying NMOS transistors TS 3 and TS 4 . Accordingly, the second P-well PW_ 2 is wrapped up in the second N-well NW_ 2 as shown in FIG. 11 .
- the third P-well PW_ 3 further includes third and fourth auxiliary NMOS transistors TSB 3 and TSB 4 having an N-channel for sensing and amplifying a lower voltage level of the second bit line pair BOT_BL and /BOT_BL, which is located between the second cell array and the third and the fourth connection PMOS transistors TBL 1 and TBL 2 , as the voltage level of the ground voltage GND.
- the second P-well PW_ 2 further includes first and second input/output NMOS transistors T 01 and T 02 having an N-channel for connecting the data sensed and amplified by the plural sense amplifying MOS transistors TS 1 to TS 4 to a local data bus line pair LDB and LDBB.
- the P-type substrate further includes a first N-well NW_ 1 and a third N-well NW_ 3 .
- the first P-well PW_ 1 is wrapped up in the first N-well NW_ 1
- the third P-well PW_ 3 is wrapped up in the third N-well NW_ 3 as shown in FIG. 11 .
- each of the N-wells and the P-wells can be formed over the P-type substrate, opposite to each other.
- each MOS transistor included in the N-wells and the P-wells has an opposite polarity channel.
- the semiconductor memory device floats the corresponding bit line pair during the precharge step and the bit line sense amplifier senses and amplifies the voltage difference between the bit line pair using the low voltage and the source voltage.
- each of the first and the second connection unit includes plural PMOS transistors, even though the bit line sense amplifier senses and amplifies the voltage difference using the low voltage and the source voltage, the low voltage VBB is not transferred to the cell array.
- the semiconductor memory device further includes the first and the second auxiliary bit line sense amplifier so that the bit line coupled to the cell array is not to be under the ground voltage.
- each of the first to the third N-wells NW_ 1 to NW_ 3 is supplies with first to third positive voltage VP 1 , VP 2 and VP 3
- each of the first to the third P-wells PW_ 1 to PW_ 3 is supplies with first to third negative voltage VN 1 , VN 2 and VN 3 .
- an operating margin of each threshold voltage of PMOS and NMOS transistors included in the semiconductor memory device is not sufficient; and, as a result, an operation reliability of the bit line sense amplifier is not guaranteed.
- an absolute quantity of each threshold voltage of the PMOS and the NMOS transistors is increased in proportion to a voltage level supplied to each of the N-wells and the P-wells. That is, in case of an NMOS transistor having an N-channel, as the absolute quantity of a voltage level of a negative voltage, i.e., VN 1 to VN 3 , supplied to the P-well is increased, a threshold voltage of the NMOS transistor is increased. Likewise, in case of a PMOS transistor having a P-channel, as the absolute quantity of a voltage level of a positive voltage, i.e., VP 1 to VP 3 , supplied to the N-well is increased, a threshold voltage of the PMOS transistor is increased.
- each threshold voltage of the NMOS and the PMOS transistor is different according to the voltage level supplied to each of the N-wells and the P-wells.
- a current driving ability of each MOS transistor included in the corresponding well depends on a bulk voltage supplied to each well.
- a variation of the threshold voltage has influence on the operation reliability.
- bit line sense amplifier In the semiconductor memory device, an operation reliability of the bit line sense amplifier has a great influence on a circuit driving ability.
- the bit line sense amplifier is sensitive to the low supply voltage because the bit line sense amplifier stars to amplify a sensed voltage at the precharge voltage of the bit line pair, e.g., a half of the source voltage VDD.
- each bulk voltage can be supplied to a corresponding well area by separating a well area for forming the bit line sense amplifier from a well area for forming the cell array.
- the cell array includes a plurality of unit cells having an NMOS transistor and a cell capacitor, it is important to arrange the PMOS transistor of the bit line sense amplifier, which operates by using a negative low voltage and connects the bit line sense amplifier to the cell array.
- the semiconductor memory device largely defines three well areas to thereby supply an optimum bulk voltage to each well area: a first well area WELL_ 1 includes the first cell array and the first precharge unit 220 a; a second well area WELL_ 2 includes the bit line sense amplifier 210 and the first and the second connection unit 250 a and 250 b; and a third well area WELL_ 3 includes the second cell array and the second precharge unit 220 b.
- the second well area WELL_ 2 further defines two well area, i.e., the second P-well PW_ 2 and the second N-well NW_ 2 , to thereby arrange the first and the second sense amplifying PMOS transistors TS 1 and TS 2 to the second N-well NW_ 2 , and the first and the second sense amplifying NMOS transistors TS 3 and TS 4 to the second P-well PW_ 2 .
- the first to the fourth connection PMOS transistors TBH 1 , TBH 2 , TBL 1 and TBL 2 are formed at the second N-well NW_ 2 where the first and the second sense amplifying PMOS transistors TS 1 and TS 2 is located.
- the second P-well PW_ 2 is wrapped up in the second N-well NW_ 2 as shown in FIG. 11 . Further, it is possible to effectively connect the first and the second cell array with the bit line sense amplifier 210 included in the first and the third well areas WELL_ 1 and WELL_ 3 .
- the PMOS and the NMOS transistors provided in the semiconductor memory device can be effectively arranged so that the optimum bulk voltage is supplied to the PMOS and the NMOS transistors to thereby get an optimum threshold voltage of each PMOS and each NMOS transistor.
- a power consumption at the precharge step can be reduced. That is, according to the conventional invention, since a source voltage or a half of a supply voltage VDD is provided for the precharge step, a predetermined amount of power is consumed. However, since the semiconductor memory device in accordance with the present invention does not need an additional power for the precharge step, the power consumption can be dramatically reduced.
- a bleed current caused by a short-circuit between a word line and a bit line of a unit cell can be prevented.
- the bit line has a voltage level of a ground voltage GND and, thus, the bleed current can be prevented because there is no voltage difference between the word line and the bit line.
- the bit line has a predetermined voltage level, a little bleed current may be generated; however, the bleed current is not generated after a voltage level of the floated bit line becomes the ground voltage GND.
- a bit line sense amplifier performs a sensing and amplifying operation by using the source voltage VDD and a low voltage VBB which is lower than the ground voltage GND, a data signal delivered to the bit line can sensed and amplified by the bit line sense amplifier at a high speed even though the source voltage VDD is low.
- an absolute quantity of the low voltage VBB may be same to that of the source voltage VDD as an operational voltage of the semiconductor memory device is decreased. In this case, a half of the source voltage VDD becomes the ground voltage GND.
- the bit line sense amplifier amplifies a high-level data to the source voltage VDD and a low-level data to the low voltage VBB and, then, at the precharge step, a voltage level of the bit line pair is maintained as the ground voltage GND.
- the precharge voltage level is a source voltage VDD or a half of the source voltage VDD
- a current is flown from a data line to a bit line and, thus, a voltage level of a bit line amplified to a low level is temporarily increased.
- the bit line sense amplifier since the bit line sense amplifier amplifies a voltage level of a bit line to a negative low voltage, the current flown from the data line is compensated by the negative low voltage. Therefore, a voltage level of the bit line is not increased more than the ground voltage. As a result, a period of the restore step can be decreased and a cycle time also can be decreased.
- the semiconductor memory device is operated by using a low voltage restraining using a high voltage, a power consumption for generating the high voltage can be reduced. That is, an absolute quantity of the low voltage is smaller than that of the high voltage and characteristics of the low voltage is better than that of the high voltage.
- the semiconductor memory device can perform a data access operation at a high speed under a low operational voltage.
- a semiconductor memory device having a folded bit line structure with a shared bit line structure it is possible to get an optimum threshold voltage of each PMOS and each NMOS transistor provided in the semiconductor memory device by forming each cell array and a bit line sense amplifier using a separate well area.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (36)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/779,097 USRE45036E1 (en) | 2005-03-31 | 2013-02-27 | Semiconductor memory device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050027382A KR100571650B1 (en) | 2005-03-31 | 2005-03-31 | Semiconductor device for low voltage |
KR10-2005-0027382 | 2005-03-31 | ||
US11/396,193 US7355913B2 (en) | 2005-03-31 | 2006-03-30 | Semiconductor memory device |
US13/779,097 USRE45036E1 (en) | 2005-03-31 | 2013-02-27 | Semiconductor memory device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/396,193 Reissue US7355913B2 (en) | 2005-03-31 | 2006-03-30 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE45036E1 true USRE45036E1 (en) | 2014-07-22 |
Family
ID=37108327
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/396,193 Ceased US7355913B2 (en) | 2005-03-31 | 2006-03-30 | Semiconductor memory device |
US13/779,097 Expired - Fee Related USRE45036E1 (en) | 2005-03-31 | 2013-02-27 | Semiconductor memory device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/396,193 Ceased US7355913B2 (en) | 2005-03-31 | 2006-03-30 | Semiconductor memory device |
Country Status (3)
Country | Link |
---|---|
US (2) | US7355913B2 (en) |
JP (1) | JP2006287225A (en) |
KR (1) | KR100571650B1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100745368B1 (en) * | 2005-11-22 | 2007-08-02 | 삼성전자주식회사 | Semiconductor memory device having advanced data input/output path |
JP2010287272A (en) * | 2009-06-10 | 2010-12-24 | Elpida Memory Inc | Semiconductor device |
KR101973212B1 (en) | 2010-11-05 | 2019-04-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
WO2015170220A1 (en) | 2014-05-09 | 2015-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and electronic device |
KR102424285B1 (en) | 2018-02-01 | 2022-07-25 | 에스케이하이닉스 주식회사 | Multi level sensing circuit and semiconductor device including the same |
US10586586B1 (en) * | 2018-11-07 | 2020-03-10 | Micron Technology, Inc. | Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same |
US10943644B1 (en) | 2020-02-19 | 2021-03-09 | Micron Technology, Inc. | Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same |
Citations (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5198995A (en) | 1990-10-30 | 1993-03-30 | International Business Machines Corporation | Trench-capacitor-one-transistor storage cell and array for dynamic random access memories |
JPH0589667A (en) | 1991-02-25 | 1993-04-09 | Motorola Inc | Dynamic-random-access-memory having improved page-mode performance and method thereof |
US5235550A (en) | 1991-05-16 | 1993-08-10 | Micron Technology, Inc. | Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts |
JPH0685200A (en) | 1992-07-13 | 1994-03-25 | Samsung Electron Co Ltd | Semiconductor device provided with triple well structure |
US5367488A (en) * | 1992-03-18 | 1994-11-22 | Goldstar Electron Co., Ltd. | DRAM having bidirectional global bit lines |
JPH08235862A (en) | 1995-02-28 | 1996-09-13 | Toshiba Corp | Dynamic semiconductor memory device |
KR970018497A (en) | 1995-09-14 | 1997-04-30 | 김광호 | Semiconductor memory device |
JPH09135006A (en) | 1995-11-09 | 1997-05-20 | Hitachi Ltd | Semiconductor storage |
US5696725A (en) | 1995-12-29 | 1997-12-09 | Hyundai Electronics Industries Co., Ltd. | High-speed sense amplifier for semiconductor memory device |
US5761123A (en) * | 1995-06-13 | 1998-06-02 | Samsung Electronics, Co., Ltd. | Sense amplifier circuit of a nonvolatile semiconductor memory device |
JPH10214485A (en) | 1998-03-06 | 1998-08-11 | Toshiba Corp | Semiconductor integrated circuit device |
KR19980067036A (en) | 1997-01-30 | 1998-10-15 | 김광호 | Bit line control circuit and method |
JPH10340581A (en) | 1997-06-06 | 1998-12-22 | Toshiba Corp | Semiconductor integrated circuit device |
US5870343A (en) * | 1998-04-06 | 1999-02-09 | Vanguard International Semiconductor Corporation | DRAM sensing scheme for eliminating bit-line coupling noise |
JPH11232871A (en) | 1997-12-10 | 1999-08-27 | Fujitsu Ltd | Semiconductor storage device, data read-out method from semiconductor storage device and data storage device |
JP2000077628A (en) | 1998-06-19 | 2000-03-14 | Toshiba Corp | Semiconductor memory device |
US6078538A (en) | 1998-08-20 | 2000-06-20 | Micron Technology, Inc. | Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
US6097652A (en) * | 1998-08-13 | 2000-08-01 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices including circuits and methods for discharging isolation control lines into a reference voltage |
JP2000243085A (en) | 1999-02-22 | 2000-09-08 | Hitachi Ltd | Semiconductor device |
JP2003217280A (en) | 2002-01-22 | 2003-07-31 | Mitsubishi Electric Corp | Semiconductor memory device |
US6654290B2 (en) * | 2001-01-03 | 2003-11-25 | Samsung Electronics Co., Ltd. | Flash memory device with cell current measuring scheme using write driver |
US6678199B1 (en) | 2002-06-19 | 2004-01-13 | Micron Technology, Inc. | Memory device with sense amp equilibration circuit |
KR20040065322A (en) | 2003-01-13 | 2004-07-22 | 주식회사 하이닉스반도체 | Sense amplifier in semiconductor memory device |
JP2005051044A (en) | 2003-07-29 | 2005-02-24 | Hitachi Ltd | Semiconductor integrated circuit device |
-
2005
- 2005-03-31 KR KR1020050027382A patent/KR100571650B1/en not_active IP Right Cessation
-
2006
- 2006-03-30 JP JP2006093578A patent/JP2006287225A/en active Pending
- 2006-03-30 US US11/396,193 patent/US7355913B2/en not_active Ceased
-
2013
- 2013-02-27 US US13/779,097 patent/USRE45036E1/en not_active Expired - Fee Related
Patent Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5198995A (en) | 1990-10-30 | 1993-03-30 | International Business Machines Corporation | Trench-capacitor-one-transistor storage cell and array for dynamic random access memories |
JPH0589667A (en) | 1991-02-25 | 1993-04-09 | Motorola Inc | Dynamic-random-access-memory having improved page-mode performance and method thereof |
US5235550A (en) | 1991-05-16 | 1993-08-10 | Micron Technology, Inc. | Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts |
US5367488A (en) * | 1992-03-18 | 1994-11-22 | Goldstar Electron Co., Ltd. | DRAM having bidirectional global bit lines |
JPH0685200A (en) | 1992-07-13 | 1994-03-25 | Samsung Electron Co Ltd | Semiconductor device provided with triple well structure |
JPH08235862A (en) | 1995-02-28 | 1996-09-13 | Toshiba Corp | Dynamic semiconductor memory device |
US5761123A (en) * | 1995-06-13 | 1998-06-02 | Samsung Electronics, Co., Ltd. | Sense amplifier circuit of a nonvolatile semiconductor memory device |
KR970018497A (en) | 1995-09-14 | 1997-04-30 | 김광호 | Semiconductor memory device |
JPH09135006A (en) | 1995-11-09 | 1997-05-20 | Hitachi Ltd | Semiconductor storage |
JPH10233092A (en) | 1995-12-29 | 1998-09-02 | Hyundai Electron Ind Co Ltd | High speed sense amplifier for semiconductor storage |
US5696725A (en) | 1995-12-29 | 1997-12-09 | Hyundai Electronics Industries Co., Ltd. | High-speed sense amplifier for semiconductor memory device |
KR19980067036A (en) | 1997-01-30 | 1998-10-15 | 김광호 | Bit line control circuit and method |
JPH10340581A (en) | 1997-06-06 | 1998-12-22 | Toshiba Corp | Semiconductor integrated circuit device |
JPH11232871A (en) | 1997-12-10 | 1999-08-27 | Fujitsu Ltd | Semiconductor storage device, data read-out method from semiconductor storage device and data storage device |
JPH10214485A (en) | 1998-03-06 | 1998-08-11 | Toshiba Corp | Semiconductor integrated circuit device |
US5870343A (en) * | 1998-04-06 | 1999-02-09 | Vanguard International Semiconductor Corporation | DRAM sensing scheme for eliminating bit-line coupling noise |
JP2000077628A (en) | 1998-06-19 | 2000-03-14 | Toshiba Corp | Semiconductor memory device |
US6097652A (en) * | 1998-08-13 | 2000-08-01 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices including circuits and methods for discharging isolation control lines into a reference voltage |
US6078538A (en) | 1998-08-20 | 2000-06-20 | Micron Technology, Inc. | Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
JP2000243085A (en) | 1999-02-22 | 2000-09-08 | Hitachi Ltd | Semiconductor device |
US6654290B2 (en) * | 2001-01-03 | 2003-11-25 | Samsung Electronics Co., Ltd. | Flash memory device with cell current measuring scheme using write driver |
JP2003217280A (en) | 2002-01-22 | 2003-07-31 | Mitsubishi Electric Corp | Semiconductor memory device |
US6678199B1 (en) | 2002-06-19 | 2004-01-13 | Micron Technology, Inc. | Memory device with sense amp equilibration circuit |
KR20040065322A (en) | 2003-01-13 | 2004-07-22 | 주식회사 하이닉스반도체 | Sense amplifier in semiconductor memory device |
JP2005051044A (en) | 2003-07-29 | 2005-02-24 | Hitachi Ltd | Semiconductor integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
US7355913B2 (en) | 2008-04-08 |
US20060233038A1 (en) | 2006-10-19 |
KR100571650B1 (en) | 2006-04-17 |
JP2006287225A (en) | 2006-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8125844B2 (en) | Semiconductor memory device for low voltage | |
US7251174B2 (en) | Semiconductor memory device for low power system | |
US7221606B2 (en) | Semiconductor memory device for low power system comprising sense amplifier with operating voltages lower/higher than ground/voltage supply and auxiliary sense amplifier | |
USRE45036E1 (en) | Semiconductor memory device | |
KR101026658B1 (en) | Semiconductor device having single-ended sensing amplifier | |
US7218548B2 (en) | Semiconductor memory device for low voltage | |
US7336522B2 (en) | Apparatus and method to reduce undesirable effects caused by a fault in a memory device | |
US7126867B2 (en) | Semiconductor memory device for low power system | |
US7924644B2 (en) | Semiconductor memory device including floating body transistor memory cell array and method of operating the same | |
US7359268B2 (en) | Semiconductor memory device for low voltage | |
US7145821B2 (en) | Semiconductor memory device for low power system | |
US6292417B1 (en) | Memory device with reduced bit line pre-charge voltage | |
US7295482B2 (en) | Semiconductor memory device for a low voltage operation | |
US7417910B2 (en) | Low voltage semiconductor memory device | |
US7203099B2 (en) | Semiconductor memory device for low power condition | |
US7573768B2 (en) | Low voltage semiconductor memory device | |
US20060092730A1 (en) | Semiconductor memory device for low power condition | |
US8218384B2 (en) | Sense amplifier for controlling flip error and driving method thereof | |
JPH06187781A (en) | Semiconductor integrated circuit device | |
JP2009048772A (en) | Semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: CHANGE OF NAME;ASSIGNOR:658868 N.B. INC.;REEL/FRAME:032457/0545 Effective date: 20140101 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001 Effective date: 20140611 Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:036159/0386 Effective date: 20150514 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
AS | Assignment |
Owner name: CPPIB CREDIT INVESTMENTS, INC., CANADA Free format text: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:046900/0136 Effective date: 20180731 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CPPIB CREDIT INVESTMENTS INC.;REEL/FRAME:054371/0884 Effective date: 20201028 |