JPH08235862A - Dynamic semiconductor memory device - Google Patents

Abstract

PURPOSE: To make it possible to suppress a sense amplifier capacity to a lower level without addition of correction, such as addition of severity to design rule for sense amplifier circuits, to assure the bit line reading out voltage of cell information and to obtain a DRAM strong to the software error of a bit line mode. CONSTITUTION: This dynamic semiconductor memory device is provided with the DRAM having a memory cell array 10 consisting of memory cells MC arranged in matrix, the bit lines BL and word lines WL and the sense amplifier circuit 20 consisting of an equalizing circuit 22, sense amplifiers 24, 30 of a flip-flop type, cell array selection transistors 21 and data transfer transistors 23. A part 30 of the flip-flop type sense amplifiers 24, 30 of the sense amplifier circuit 20 are arranged nearer the sense array 10 side than the cell array selection TRs 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM) and, more particularly, to a DRAM having both high cell array density and high reliability.

[0002]

2. Description of the Related Art In a DRAM in which dynamic memory cells of 1 transistor / 1 capacitor are formed in a matrix, information charges of memory cells selected by word lines are read out to bit lines. At this time, since the capacitance of the bit line is larger than the capacitance of the memory cell capacitor, the potential fluctuation appearing on the bit line is extremely small,
This is sense-amplified by a sense amplifier.

FIG. 12 shows a configuration example of a conventional memory cell array and sense amplifier circuit of a DRAM. This DRA
Reading of M cell information will be briefly described with reference to FIG. During standby, the bit line pair BL, / BL is fixed to the precharge potential V _BL by the control signal / EQL = "H" of the BL equalize circuit and the control signals PT0, PT1 = "H" of the cell array selection Tr. There is. Generally, V _BL is often set to (1/2) V _CC when the power supply voltage is V _CC .

Next, consider the case of reading cell information.
Now, considering the case of reading from the memory cell 1 connected to WL0, PT0 remains at the “H” level and the sense amplifier circuit and the cell array on the side having the memory cell 1 are kept connected, PT1 is lowered to "L" level, and the cell array on the right side of the sense amplifier in the drawing is separated from the sense amplifier circuit.

Next, after setting / EQL = "L" to bring the bit line pair BL, / BL into a floating state, the selected word line (here, WL0) and its corresponding dummy word line (here, DWL0). Is started and the cell data is read to the bit line (/ BL in this case).

Further, a cell having the same capacity as the memory cell is generally used as the dummy cell, and the voltage written is between the "H" level and the "L" level written in the cell (1/2 Often V _CC . In this way, B
The difference between the potentials read to L and / BL causes the sense amplifier drive signal SAP to rise from V _BL and / SAN to V _BL.
The sense amplifier is moved and amplified by pulling it down from.

As described above, normally, the reading of information from the memory cell is performed in the state where the sense amplifier circuit is connected to the bit line. Therefore, the capacity of the cell is C _S and the voltage for writing information to the cell is V _W, and the capacitance of the bit of the cell array portion C _B, the capacity of the sense amplifier circuit and C _SA, voltage V _R appearing at the bit line when reading the information charges from the memory cell to the bit line, V _R = { It can be expressed as C _S / (C _B + C _S + C _SA )} V _W (1) Therefore, the voltage read to BL is proportional to C _S / (C _B + C _S + C _SA ) and V _W.

In recent years, DRAM has been improved in memory cell structure.
Due to the progress of designing technology and fine processing technology, the density has been remarkably increased. At the research and development level, trial manufacture of a DRAM having an integration degree of 256 Mbits has been advanced.

In the process of increasing the density of DRAM, the number of memory cells connected to one bit line has not increased. This is because the bit line and memory cell contacts occupy a considerable part of the bit line capacitance, so that increasing the number of cells to be connected increases the bit line capacitance C _B , resulting in the required read voltage V _R. This is because it becomes difficult to secure As described above, if the number of memory cells connected to the bit line is constant, the capacity of the bit line decreases with the miniaturization of the DRAM as the density increases. On the other hand, the design rule of the sense amplifier circuit is not made finer than that of the memory cell. This is because the DRAM is designed with a margin in consideration of the operational stability. Therefore, the capacity C _SA of the number of sense amplifiers does not decrease as much as the memory cell capacity even if the generation of DRAM changes.

C _B , C _SA , and C _SA / of each generation of DRAM
FIG. 14 shows an example of (C _B + C _SA ). Because even changed DRAM generation C _SA does not change much, C _SA / (C
_B + C _SA ) increases with each generation. As a result, formula (1)
At, the influence of C _SA on V _R becomes relatively large. The write voltage V _RW depends on the power supply voltage V _CC . In some cases V _CC is written ( "1" when the writing), but sometimes written by lowering, it is not much to be boosted above V _CC. Due to the higher density of DRAM, the power supply voltage V _CC tends to decrease due to the demand for ensuring the reliability of miniaturized devices and lower power consumption, and this tendency can be seen from the equation (1). As described above, it becomes an element that works in the opposite direction to maintaining V _R.

Furthermore, it is difficult to secure a large cell capacity C _S due to the miniaturization of memory cells. As described above, (1) the power supply voltage V _CC tends to decrease as the density of DRAM increases. (2) The sense amplifier capacitance C _SA does not become so small even if the generation changes. (3) It becomes difficult to secure the memory cell capacity C _S. Therefore, it becomes very difficult to maintain the read voltage V _R to the bit line of the memory cell in the formula (1). A particular problem is that C _SA is not reduced (scaled) as the DRAM density increases, and the factor that C _SA occupies as a factor that determines V _R increases with each generation. is there.

Further, the fact that C _SA is not scaled means that the ratio of the area of the sense amplifier circuit to the memory cell portion increases in the cell array including the sense amplifier circuit. As a result, the α line collides between the time when the information charge is read to the bit line and the time when the sense amplifier operates, causing a bit line mode lift error caused by destroying the charge ratio of the bit line pair. As a result, the factor occupied by the sense amplifier circuit is expected to increase.

[0013]

As described above, the conventional DR
In the AM, it is difficult to maintain a sufficient read voltage from the memory cell to the bit line because the sense amplifier circuit is not sufficiently scaled, and the sense amplifier is not affected by the soft error in the bit line mode. There is a problem that the factors occupied by the circuit increase.

The present invention has been made in consideration of the above circumstances, and an object thereof is to suppress the sense amplifier capacitance C _SA to a small value without making modifications such as tightening the design rules of the sense amplifier circuit. It is possible to provide a DRAM that can secure a bit line read voltage for cell information and is resistant to a soft error in the bit line mode.

[0015]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention (Claim 1) includes a plurality of dynamic memory cells arranged in a matrix, a plurality of bit lines for transmitting and receiving data to and from these memory cells, and an arrangement arranged so as to intersect these bit lines. A memory cell array including a plurality of word lines and the like for selecting memory cells, an equalizer circuit that holds a bit line at a constant voltage during non-operation and a waiting period, and a flip-flop that senses the potential of the bit line during operation Type sense amplifier, a cell array selection transistor for connecting the cell array to the sense amplifier, a sense amplifier circuit including a data transfer transistor for exchanging data with the outside of the cell array, and the like. A part of the flip-flop type sense amplifier of the sense amplifier circuit is selected as the cell array selection transistor. Than Njisuta and characterized by being arranged on the cell array side.

According to the present invention (claim 2), in a dynamic semiconductor memory device, a plurality of dynamic memory cells arranged in a matrix, and a plurality of bit lines for exchanging data with these memory cells. A memory cell array composed of a plurality of word lines and the like arranged to intersect these bit lines to select a memory cell, and an equalizing circuit for holding the bit lines at a constant voltage during non-operation and waiting periods, A sense amplifier circuit including a flip-flop type sense amplifier that senses the potential of the bit line during operation, a cell array selection transistor for connecting the cell array to the sense amplifier, a data transfer transistor for exchanging data with the outside of the cell array, and the like. And a cell array selection transistor of the sense amplifier circuit and the cell array. And characterized by being provided with an auxiliary sense amplifier provided between the.

The preferred embodiments of the present invention are as follows. (1) When reading data from the memory cell, the activated cell array is separated from the sense amplifier circuit by the cell array selection transistor, and after reading the data, the sense amplifier arranged on the cell array side of the cell array selection transistor is first After that, the sense amplifier circuit is connected to the memory cell array, and the remaining sense amplifiers are operated. (2) Arrangement of flip-flop type sense amplifiers arranged in the cell array at a plurality of locations in a single unit array, and disperse the sense amplifiers. (3) Twist the bit lines in the flip-flop type sense amplifier arrangement area arranged in the cell array. (4) The bit line configuration of the cell array must be a folded type. (5) A memory cell array is arranged on both sides of the sense amplifier circuit via cell array selection transistors, and a part of a flip-flop type sense amplifier or an auxiliary sense amplifier is arranged on the cell array side of each cell array selection transistor. To be. (6) The flip-flop type sense amplifier is a p-channel M
It is composed of a p-type sense amplifier composed of an OS transistor and an n-type sense amplifier composed of an n-channel MOS transistor, and a part of the sense amplifier arranged on the cell array side of the cell array selection transistor or an auxiliary sense amplifier is an n-type sense amplifier. .

[0018]

According to the present invention, since a part of the flip-flop type sense amplifier of the sense amplifier circuit or the auxiliary sense amplifier is arranged between the cell array selection transistor and the cell array, when the word line is raised and the data is read out. In addition, the cell array selection transistor can be turned off, and the initial amplification can be performed by the sense amplifier arranged on the cell side of the cell array selection transistor. This makes it possible to reduce the influence of the capacitance of the sense amplifier circuit at the time of reading data and increase the read voltage of the cell. In addition, the cell array selection transistor is turned on.
By setting the sense amplifier circuit side to a constant voltage by the equalizing circuit during the FF, it is possible to shorten the floating time of the sense amplifier circuit and reduce the soft error in the BL mode.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a DRAM according to a first embodiment of the present invention.
The configurations of the cell array section and the sense amplifier circuit section of
FIG. 2 shows a timing diagram to show the operation.

FIG. 1 shows an example in which the present invention is applied to a cell array having a folded (folded) BL structure. The memory cell array 10 (10a, 10b) is configured by arranging a plurality of memory cells MC (MC1 to MC2) in a matrix, and a plurality of bit lines BL (BL1 to 2 and / BL1) for exchanging information charges with them. 2) are arranged in parallel. Further, the memory cell MC intersects with the bit line BL.
A word line WL for selecting is arranged. The memory cell MC has a well-known 1-transistor / 1-capacitor structure.

Since the sense amplifier circuit 20 has a folded BL structure in this example, it is shared by the cell arrays 10 on both sides. Therefore, the cell array selection transistors 21 (MN0 to 3) controlled by the signal PT are provided. Cell array selection transistor 2 arranged at two locations
Between 1a and 21b (between MN0, 1 and MN2, 3), a BL equalizer 22 for holding the bit line pair BL, / BL at a desired potential (V _BL ) and data exchange with the outside of the cell array. Transfer transistor 2 for controlling
3 and a pMOS sense amplifier 24 are provided.

An nMOS sense amplifier 30 is arranged between the sense amplifier circuit 20 and the cell array 10. That is, the nMOS sense amplifier 30 is provided between the cell array selection transistor 21a and the left cell array 10a.
a is provided, and the nMOS sense amplifier 3 is provided between the cell array selection transistor 21b and the cell array 10b on the right side.
0b is provided.

The circuit operation of this embodiment will be described with reference to the timing chart of FIG. In the precharge state of / RAS = “H”, the bit line precharge signal / EQL =
“H” and the cell array selection signal PT = “H”,
Each bit line BL is held at the precharge potential V _BL .
Here, V _BL is not particularly limited, but for example (1 /
2) _Set to V _CC . In addition, the sense amplifier drive signal SAP, /
SAN _L and _R SAN _R are also held in V _BL .

Next, in the active cycle with / RAS = "L", PT becomes "L" for both left and right (L, R), and the cell array 10 and the sense amplifier circuit 20 are separated. Next, WL rises, data is read from the memory cell MC, and the sense amplifier drive signal / SAN _L =
The potential of the bit line BL on the cell array 10a side is amplified by "L".

When the signal is amplified to some extent, EQL =
When "L", the sense amplifier circuit 20 is floated, and the cell array selection signal PT on the operating array side is set.
(PT _L ) is set to “H”, the sense amplifier circuit 20 and the bit line BL on the cell array 10a side are connected, and the signal is completely amplified by the sense amplifier drive signal SAP = “H”.

At the end of the active cycle, WL =
"L", / SAN, SAP = V _BL , / EQL = "H",
The original state may be returned in the order of PT _R = “H”. As described above, in the present embodiment, when the cell data is initially sensed, n
Other sense amplifier circuit 2 except MOS sense amplifier 30
By separating 0 from the bit line BL, the influence of the sense amplifier capacitance on the bit line read voltage of cell data can be reduced and the sense margin can be increased. Further, even when the bit line BL is in a floating state and data is being read from the cell, the sense amplifier circuit 20 is provided until immediately before PT = “H” / EQL =
The potential can be held at L _BL as “H”, which is also effective for reducing soft errors in BL mode. (Embodiment 2) FIG. 3 shows the D according to the second embodiment of the present invention.
It is a figure which shows the structure of the cell array part and sense amplifier part of RAM. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the nMOS sense amplifier 25 is provided in the sense amplifier circuit 20 together with the pMOS sense amplifier 24. That is, the nMOS sense amplifier is divided and arranged on the cell array 10 side and the sense amplifier circuit 20 side with respect to the cell array selection transistor, and as a result, the size of the sense amplifier arranged on the array side 10 can be reduced. It is effective in reducing the chip area. The operation timing is n in the sense amplifier circuit 20.
The drive signal / SAN ₀ of the MOS sense amplifier 25 is set to SAP.
2 is the same as that of FIG. 2 except that the operation is performed at substantially the same timing.

Even with such a structure, the same effect as that of the first embodiment can be obtained. (Embodiment 3) FIG. 4 is a diagram showing the construction of the essential parts of a third embodiment of the present invention. The sense amplifier circuit 20 and the nMOS sense amplifier 30 on the cell array 10 side are either the first or the second.
This is the same as each circuit of the embodiment. This embodiment is characterized in that two sets of different bit line pairs of nMOS sense amplifiers 30 are arranged in one region inside the cell array 10. (Embodiment 4) FIG. 5 is a diagram showing the construction of the essential parts of a fourth embodiment of the present invention. This embodiment is an example in which the bit line BL is twisted in the third embodiment.
In the area where the sense amplifier 30 is arranged, the bit line B
It is characterized in that an increase in the chip area is suppressed by twisting L. (Embodiment 5) FIG. 6 is a diagram showing the construction of the essential parts of a fifth embodiment of the present invention. NM in one memory cell array 10
The design rule of the nMOS sense amplifier 30 is relaxed by distributing the region in which the OS sense amplifier 30 is arranged in a plurality of places. (Embodiment 6) FIG. 7 is a diagram showing a configuration of a main portion of a sixth embodiment of the present invention. One memory cell array 10
In the case of twisting BL at a plurality of places in the same, by using a part or all of the twist areas as an area for arranging the sense amplifier 30, both the twist of the bit line BL and the relaxation of the design rule are made compatible. It is characterized by

In the fifth and sixth embodiments described above, for example, two wiring layers are used for the bit lines BL, and a folded BL structure is realized between the upper and lower bit lines BL. This is especially effective when the design rules of a special sense amplifier are strict.

Although not shown in the figure, in the system using the two-layer BL, the upper layer and the lower layer existing inside the array are the regions for switching the bit lines BL as the regions for arranging the nMOS sense amplifier 30. Using it also has the same effect as the sixth embodiment. (Embodiment 7) FIG. 8 is a diagram showing a configuration of a main portion of a seventh embodiment of the present invention. In the present embodiment, the sense amplifier circuits 20 and n are arranged in one sense amplifier arrangement area by arranging the cell arrays by shifting by 1/2 array with the width of the sense amplifier circuit 20 as the pitch in the fourth embodiment.
The MOS sense amplifiers 30 are alternately arranged to relax the design rule of each sense amplifier.

This system is effective even when the sense amplifier design rule is strict as in the above-mentioned two-layer BL system. Further, it can be easily applied to the other embodiments described so far. (Embodiment 8) FIG. 9 is a diagram showing a configuration of a main part of an eighth embodiment of the present invention. This is the present invention Open B
This is an example applied to an L-structure cell array. As shown by the dotted line in the figure, the bit line BL of one cell array 10 is passed through the sense amplifier circuit 20 to pass through the nMOS sense amplifier 3
It is necessary to connect to 0, but for this purpose the bit line BL
May be connected to another wiring layer and passed therethrough. (Embodiment 9) FIG. 10 is a diagram showing the configuration of the essential parts of a ninth embodiment of the present invention. This is an example applied to an open BL / folded BL hybrid array called an open / folded BL configuration. In this open folded BL configuration, a pair of bit lines BL is recombined with a selected word line, and a BL select transistor 40 causes a sense amplifier on the left side of the drawing to operate in a folded BL configuration and a sense amplifier on the right side to operate. This is a system that operates in an open BL configuration.

In this embodiment, the folded BL
In the left-side sense amplifier which performs the open type operation, the nMOS sense amplifier 30 is arranged between the bit line selection transistor 40 and the sense amplifier circuit 20 in the left sense amplifier which performs the open BL type operation as in the first embodiment. In the amplifier, as in the eighth embodiment, the sense amplifier circuit 20
And an nMOS sense amplifier 30 are arranged to support an open folded BL configuration. (Embodiment 10) FIG. 11 is a diagram showing the configuration of the essential parts of a tenth embodiment of the present invention. This is FOF / BL
This is called a configuration, and cell data is read using a folded BL type and writing is an open folded B type.
This is an example applied to a system of L type.

Similar to the case of the sense amplifier which performs the folded BL type operation of the open folded BL structure according to the ninth embodiment, the sense amplifier circuit 20 is provided on the side opposite to the cell array 10 via the BL selection transistor 40.
And the nMOS sense amplifier 30 are arranged, the FOF
・ Supports BL configuration.

The present invention is not limited to the above embodiments. For example, the sense amplifier arranged in the cell array is not necessarily limited to the nMOS sense amplifier, but may be a pMOS sense amplifier. The configuration of the sense amplifier circuit is not limited to that shown in FIGS. 1 and 3, and includes at least an equalizer circuit for the bit line, a sense amplifier for sensing the potential of the bit line, and a cell array selection transistor. I wish I had it. In addition, various modifications can be made without departing from the scope of the present invention.

[0035]

As described above, according to the present invention, when the cell data is read, the influence of the capacitance of the sense amplifier section is minimized to enhance the sense margin, and B
It is possible to realize a DRAM that can reduce the L-mode soft error.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a cell array unit and a sense amplifier circuit unit of a DRAM according to a first embodiment.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a diagram showing a configuration of a cell array section and a sense amplifier circuit section of a DRAM according to a second embodiment.

FIG. 4 is a diagram showing a configuration of a main part of a DRAM according to a third embodiment.

FIG. 5 is a diagram showing a configuration of a main part of a DRAM according to a fourth embodiment.

FIG. 6 is a diagram showing a main part configuration of a DRAM according to a fifth embodiment.

FIG. 7 is a diagram showing a configuration of a main part of a DRAM according to a sixth embodiment.

FIG. 8 is a diagram showing a main part configuration of a DRAM according to a seventh embodiment.

FIG. 9 is a diagram showing a main part configuration of a DRAM according to an eighth embodiment.

FIG. 10 is a diagram showing a configuration of a main part of a DRAM according to a ninth embodiment.

FIG. 11 is a diagram showing a configuration of a main part of a DRAM according to a tenth embodiment.

FIG. 12 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit of a conventional DRAM.

FIG. 13 is a diagram showing operation waveforms of a conventional DRAM.

[14] each generation of DRAM and _{C B, CS A, C SA} /
The figure which shows the relationship of (C _B + C _SA ).

[Explanation of symbols]

 10 (10a, 10b) ... Memory cell array 20 ... Sense amplifier circuit 21 (21a, 21b) ... Cell array selection transistor 22 ... BL equalizer 23 ... Data transfer transistor 24 ... pMOS sense amplifier 25, 30 (30a, 30b) ... nMOS sense amplifier 40 ... Bit line selection transistor

Claims (2)

[Claims] 1. A plurality of dynamic memory cells arranged in a matrix, a plurality of bit lines for transmitting and receiving data to and from these memory cells, and memory cells arranged to intersect these bit lines. A memory cell array including a plurality of word lines for selection, an equalizing circuit that holds a bit line at a constant voltage when not operating, a flip-flop type sense amplifier that senses the potential of the bit line when operating, A dynamic semiconductor memory device comprising: a cell array selection transistor for connecting a cell array and a sense amplifier; and a sense amplifier circuit including a data transfer transistor for exchanging data with the outside of the cell array. Select a part of the flip-flop type sense amplifier of the amplifier circuit in the cell array Dynamic semiconductor memory device characterized by comprising arranged on the cell array side than transistors. 2. A plurality of dynamic memory cells arranged in a matrix, a plurality of bit lines for transmitting and receiving data to and from these memory cells, and memory cells arranged to intersect these bit lines. A memory cell array including a plurality of word lines for selection, an equalizing circuit that holds the bit lines at a constant voltage when not operating, and a flip-flop type sense amplifier that senses the potential of the bit lines when operating. A cell array selection transistor for connecting the cell array and the sense amplifier; and a sense amplifier circuit including a data transfer transistor for exchanging data with the outside of the cell array; a cell array selection transistor of the sense amplifier circuit; And an auxiliary sense amplifier provided between the cell array and Dynamic semiconductor memory device according to claim and.