JPH06333382A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve an operating margin and to reduce power consumption while decreasing the chip size in a semiconductor memory. CONSTITUTION:A memory cell 2a is activated when a word line WL1 rises and data are transferred from the memory cell 2a to a bit line 11. A bit line having reference to the bit line 11 is an arbitrary one among the respective bit lines 15-18 located on a symmetric position with the bit line 11 about a sense amplifier 1 by means of respective wirings 31, 32. The bit line 15 is here made to be the reference to the bit line 11. At the same time when the word line WL1 rises, only the respective control lines S1, S5 are risen and only the respective transfer gates 21, 25 are opened. Consequently, the data written in the memory cell 2a are transferred to the wire 31 of a wiring layer other than the bit line 11 from the bit line 11 through the transfer gate 21 and sensed by the sense amplifier 1 through the wire 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Specifically, it relates to a sense circuit of DRAM.

[0002]

2. Description of the Related Art FIG. 3 shows one pair of bit lines BL and bar BL.
FIG. 9 is a circuit diagram of a main part of a conventional folded bit line type DRAM provided with one sense amplifier 1.

A pair of bit lines BL and BL are connected to one sense amplifier 1. And each bit line B
A 1-transistor type memory cell 2 composed of one MOS transistor and one MOS capacitor is connected to each of L and BL. Each memory cell 2 is connected to each word line WL.

Here, complementary signals are applied to the bit lines BL and BL, respectively, and they have a reference relationship with each other. That is, the bit line BL serves as a reference for the bit line bar BL, and the bit line bar BL serves as a reference for the bit line BL.

In FIG. 3, the input / output line connected to the sense amplifier 1 is omitted. In addition, when the containment sense is performed, transfer gates (not shown) are respectively provided between the bit lines BL and bar BL and the sense amplifier 1.
Connect. Then, when data is read from the memory cell 2 to the bit line BL (or bit line bar BL) at the time of reading data, the transfer gate is temporarily closed (non-conducting) for sensing, and at the time of restore, the transfer gate is restored Try to open (conduct).

By the way, in recent years, with the increase in capacity of DRAMs, it is required to reduce the chip size of DRAMs more than the present size. As one of the measures, it is considered to reduce the number of sense amplifiers. That is, since the sense amplifier is configured by using a large number of transistors each having a large transistor size, the occupied area on the chip is much larger than that of the memory cell.

FIG. 4 shows a conventional folded bit line type DRAM in which one sense amplifier 1 is provided for two pairs of bit lines BL1, BL1, BL2, BL2 in order to reduce the number of sense amplifiers. It is a main part circuit diagram of.

Two pairs of bit lines BL1, bar BL1, BL2, bar BL2 are connected to one sense amplifier 2 via transfer gates 3 and 4, respectively. here,
Complementary signals are applied to the bit lines BL1 and BL1 and are in a reference relationship with each other. That is, the bit line BL1 serves as a reference for the bit line bar BL1 and the bit line bar BL1 serves as a reference for the bit line BL1. Further, complementary signals are applied to the bit lines BL2 and BL2, respectively, and they have a reference relationship with each other. That is, the bit line BL2 serves as a reference for the bit line bar BL2, and the bit line bar BL2 serves as the bit line BL2.
It serves as a reference to 2.

When sensing each bit line BL1 and bar BL1, the transfer gate 3 is opened and the transfer gate 4 is closed so that only each bit line BL1 and bar BL1 is connected to the sense amplifier 2. When sensing each bit line BL2, bar BL2, the transfer gate 4 is opened and the transfer gate 3 is closed so that only each bit line BL2, bar BL2 is connected to the sense amplifier 2.

That is, the DRAM shown in FIG. 4 has two pairs of left and right bit lines BL by the transfer gates 3 and 4.
We share 1, bar BL1, BL2, bar BL2.
Therefore, if the number of memory cells 2 is the same (8 in FIG. 3 and FIG. 4), the number of sense amplifiers 2 in the DRAM shown in FIG. 4 can be halved as compared with the DRAM shown in FIG. .

Incidentally, also in FIG. 4, the input / output lines connected to the sense amplifier 1 are omitted. When the containment sense is performed, the sense side bit line BL1, bar
Only the transfer gates 3 and 4 of BL1, BL2 and bar BL2 are opened and closed. That is, bit line BL1, bar BL1
Memory cell 2 to bit line
When data is transferred to BL1 (or bit line bar BL1), the transfer gate 3 is once closed and sensed, and the transfer gate 3 is opened again at the time of restoration. At this time, the transfer gate 4 is kept closed.

[0012]

By the way, in order to improve the operation margin of the DRAM, it is necessary to increase the ratio (CS / CB) of the memory cell capacity CS and the bit line capacity CB. For that purpose, shortening the bit line length to reduce the number of memory cells connected to the bit line is the easiest circuit method. In addition, shortening the bit line length to reduce the number of memory cells connected to the bit line also leads to reduction in power consumption.

However, the conventional DRAM shown in FIG.
Then, when the bit line length is shortened to reduce the number of memory cells connected to the bit line, the number of sense amplifiers increases, which causes a problem of hindering the reduction of the DRAM chip size.

For example, in FIG. 4, one sense amplifier 1 senses eight memory cells 2. Therefore, if the number of memory cells 2 sensed by one sense amplifier 1 is reduced by half from eight to four, as shown in FIG.
Two sense amplifiers 1 are needed.

That is, in the conventional folded bit line type DRAM, the operation margin is improved and power consumption is reduced by shortening the bit line length to reduce the number of memory cells connected to the bit line. It was not possible to achieve both the reduction in chip size and the reduction in number.

Further, in order to improve the operation margin of DRAM, it is necessary to increase the noise margin of each bit line. However, the conventional folded bit line type DR
In AM, a pair of bit lines having a reference relationship are adjacent to each other in parallel, and thus there is a problem in that they receive noise from each other. Therefore, conventionally, a method has been adopted in which a pair of bit lines having a reference relationship are twisted together to cancel the noise of both bit lines (called a twist type bit line).

However, in the twist type bit line,
Since the twist must be repeated and the area of the twist portion is required, there is a problem that the chip size becomes large.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of improving an operation margin and reducing power consumption while reducing a chip size. To provide.

[0019]

The invention according to claim 1 is
A word line and a bit line to which a one-transistor type memory cell is connected, transfer gates provided for each bit line, and two bit line groups each having the same number of bit lines and having a reference relationship with each other, For each of two bit line groups, only one sense amplifier is provided, and each transfer gate of each bit line group and the sense amplifier are connected to each other, and each wiring is in a reference relationship with each other. And

A second aspect of the present invention is characterized in that, in the semiconductor memory device according to the first aspect, each of the wirings is formed in a wiring layer different from that of each of the bit lines. According to a third aspect of the present invention, in the semiconductor memory device according to the first aspect, each bit line of one bit line group and each bit line of the other bit line group are not adjacent to each other in parallel. It is the gist of having arranged.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the first aspect, two bit line groups (41, 4) are provided.
The gist is that 2) is arranged symmetrically with respect to the sense amplifier.

[0022]

Therefore, according to the first aspect of the present invention, the two bit line groups are in a reference relationship, and each bit line group is connected to one sense amplifier by the two wirings in the reference relationship via the transfer gates. It is connected.

Therefore, when an arbitrary word line rises and an arbitrary memory cell is selected, the bit line connected to the memory cell is selected in one bit line group. Then, any one bit line of the other bit line group is determined as the reference of the selected bit line of the one bit line group. Then, the transfer gate of the selected bit line of one bit line group and the transfer gate of the determined bit line of the other bit line group are both closed (conducted), and each bit line is set to 1 by each wiring. Connected to two sense amplifiers. That is, each wiring serves as the node itself of the sense amplifier and functions similarly to a pair of bit lines in the open bit line system.

According to the second aspect of the invention, each wiring and each bit line are formed in different wiring layers. Therefore, the wiring capacitance of each wiring can be reduced, and the capacitive load from each wiring to each bit line is also reduced. Here, by shortening each bit line to reduce the number of memory cells connected to the bit line, the ratio of the memory cell capacity to the bit line capacity can be increased, and the operation margin of the semiconductor memory device can be improved. Also, power consumption can be reduced.

According to the third aspect of the invention, the bit lines are arranged so that the bit lines of one bit line group and the bit lines of the other bit line group are not adjacent to each other in parallel. ing. Therefore, the two bit lines having the reference relationship do not receive noise from each other. As a result, the noise margin of each bit line can be increased, and the operation margin of the semiconductor memory device can be improved.

According to the invention described in claim 4, the same effect can be obtained by the same operation as that of the invention described in claim 3.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will be described below with reference to FIG. FIG. 1 is a circuit diagram of a main part of the DRAM of this embodiment.

The DRAM of this embodiment has one sense amplifier 1 for comparison with the conventional DRAM shown in FIG.
, Eight bit lines 11 to 18, eight memory cell cells 2a to 2h, and eight transfer gates 21 to 2
8 and wirings 31 and 32. The bit line length of each bit line 11-18 is half of each bit line BL1, bar BL1, BL2, bar BL2 shown in FIG. Further, each of the memory cell cells 2a to 2h has the same configuration as that of each of the memory cell cells 2 shown in FIG.
This is a one-transistor type memory cell composed of one MOS transistor and one MOS capacitor. The memory cells 2a to 2h are connected to the word lines WL, respectively.
1 to WL8.

The bit line 11 is used for each transfer gate 2
It is connected to the bit line 13 via 1 and 23. The bit line 12 is connected to the bit line 14 via the transfer gates 22 and 24. The bit line 15 is connected to the bit line 17 via the transfer gates 25 and 27. The bit line 16 is connected to the bit line 18 via the transfer gates 26 and 28. A node A between the transfer gates 21 and 23 and a node B between the transfer gates 22 and 24 are provided.
Are connected to the sense amplifier 1 via the wiring 31. The node C between the transfer gates 25 and 27 and the node D between the transfer gates 26 and 28 are connected to the sense amplifier 1 via the wiring 32.

That is, the bit lines 11 to 14 are connected to the sense amplifier 1 via the transfer gates 21 to 24 and the wiring 31, respectively. In addition, the bit lines 15 to 18 are respectively connected to the transfer gates 2
It is connected to the sense amplifier 1 through 5-28 and the wiring 32.

The bit lines 11 to 14 form a bit line group 41, and the bit lines 15 to 18 form a bit line group 42. Further, both bit line groups 41 and 42 are arranged symmetrically with respect to the sense amplifier 1.

Opening / closing control of the transfer gates 21 to 28 is performed by control signals S1 to S8 applied to the respective gates. That is, when the control signals S1 to S8 rise, the corresponding transfer gates 21 to 28 are opened (conducted).

Here, there is no reference relation between the bit lines 11 to 14, and no reference relation between the bit lines 15 to 18. The reference relationship is that each line 31,
32 is any two bit lines symmetrically positioned by 32. That is, it is any one of the bit lines 15 to 18 that has a reference relationship with each of the bit lines 11 to 14. The bit lines 15 to 18 have a reference relationship with each of the bit lines 11 to 1, respectively.
Any one of the four. That is, the bit line groups 41 and 42 are in a reference relationship with each other.

The wirings 31 and 32 are connected to the bit line 1 respectively.
It is formed in a wiring layer different from that of 1 to 18. For example, when the bit lines 11 to 18 are formed in the polycide wiring layer, the wirings 31 and 32 may be formed in the uppermost aluminum wiring layer of the chip (second layer aluminum wiring). As a result, the wiring capacitance of the wirings 31 and 32 can be made extremely small, and the capacitive load applied from the wirings 31 and 32 to the bit lines 11 to 18 can be almost eliminated.

By the way, the uppermost aluminum wiring layer of the chip is generally provided for the global signal line which is the decode signal line of the column. In other words, by utilizing the low wiring density of the global signal lines, the wiring lines 31,
32 is formed.

However, if the wirings 31 and 32 are formed of aluminum wiring, it is difficult to reduce the line width of the wirings 31 and 32. However, here, two bit lines (1
1 and 12, 13 and 14, 15 and 16, 17 and 18), one wiring 31 and 32 is formed. Therefore, the line width of each of the wirings 31 and 32 is equal to that of each of the bit lines 11 to 1.
8 can be made sufficiently thick.

In FIG. 1, the input / output line connected to the sense amplifier 1 is omitted. Next, regarding the read operation of the DRAM of the present embodiment configured as described above,
The case where the word line WL1 is activated (that is, the data written in the memory cell 2a is read) will be described as an example.

When the word line WL1 rises, the memory cell 2
a is activated and data is transferred from the memory cell 2a to the bit line 11. Here, the bit line having a reference relationship with the bit line 11 is an arbitrary one of the bit lines 15 to 18 which is symmetrical to the bit line 11 by the wirings 31 and 32 with respect to the sense amplifier 1. is there. Here, the bit line 15 is used as a reference for the bit line 11.

Then, at the same time when the word line WL1 rises, only the controls S1 and S5 rise and only the transfer gates 21 and 25 open (become conductive). At this time, each control S2, S3, S4, S
6, S7 and S8 do not rise, and the transfer gates 22, 23, 24, 26, 27 and 28 are closed (not connected).

Therefore, the data written in the memory cell 2a is transferred from the bit line 11 to the wiring 31 via the transfer gate 21, and is input from the wiring 31 to the sense amplifier 1 to be sensed.

As described above, in the DRAM of this embodiment, the bit lines 11 to 14 are connected to the sense amplifier 1 via the transfer gates 21 to 24 and the wiring 31, respectively, and the bit lines 15 to 18 are connected. Each of them is connected to the sense amplifier 1 via the transfer gates 25 to 28 and the wiring 32. Then, with respect to the sense amplifier 1, any two bit lines symmetrically arranged by the wirings 31 and 32 are treated as having a reference relationship. Therefore, each transfer gate 21-
By appropriately controlling 28, each wiring 31, 32
Can have the same reference relationship as the pair of bit lines BL1 and BL1 (or BL2 and BL2) shown in FIG. That is, each of the wirings 31 and 32 functions as a node itself of the sense amplifier 1 and functions similarly to a pair of bit lines in the open bit line system. Therefore, the data read from each of the memory cells 2a to 2h can be transferred to and sensed by the sense amplifier 1 from each of the bit lines 11 to 14 through the wiring 31 or each of the bit lines 15 through the wiring 32. The write operation is the reverse of the read operation.

Now, the DRAM of this embodiment will be compared with the conventional DRAM shown in FIG. DRAM of this embodiment
Then, one sense amplifier 1 has eight memory cells 2a ...
Senses 2h. This is the conventional D shown in FIG.
The same is true for RAM. However, in the DRAM of this embodiment, as described above, the bit line lengths of the bit lines 11 to 18 are the same as the bit lines BL1, BL1 and BL2 shown in FIG.
It is half of bar BL2. Furthermore, the DR of this embodiment
In AM, one memory cell 2 is provided for each bit line 11-18.
Only a to 2h are connected. That is, in the DRAM of this embodiment, the bit line length and the number of memory cells connected to one bit line can be halved with the same number of sense amplifiers as compared with the conventional DRAM shown in FIG. it can.

As a result, in the DRAM of this embodiment, by shortening the bit line length to reduce the number of memory cells connected to the bit line, the operation margin is improved and the power consumption is reduced, and the number of sense amplifiers is reduced. It is possible to achieve both reduction in chip size and reduction in chip size.

Further, in the DRAM of this embodiment, the bit lines 11 to 18 and the wirings 31 and 3 which are in the reference relation.
2 are not adjacent in parallel. Therefore, each bit line 11
18 and the wirings 31 and 32 do not receive noise from each other. Therefore, the noise margin of each bit line 11-18 and each wiring 31, 32 can be increased, and the operation margin of the DRAM can be improved. Here, the manufacturing process of each bit line 11-18 and each transfer gate 31-38 is the same as that of the conventional one, and each wiring 31, 32 can be formed in the same process as the global signal line as described above. That is, there is no problem that the number of manufacturing steps is increased when the DRAM of this embodiment is embodied.

The present invention is not limited to the above embodiment, but may be implemented as follows, for example. 1) Containment sense may be performed. For example,
When the word line WL1 is activated as described above, when the data is transferred from the memory cell 2a to the bit line 11, the transfer gates 21 and 25 are temporarily closed (disabled) for sensing, and the transfer gate is restored at the time of restoration. 21 and 25 are reopened (conducted).

2) As shown in FIG. 2, one sense amplifier 1 senses 16 memory cells.
That is, each bit line 11-14, each memory cell 2a-2d, and each transfer gate 21-24 shown in FIG.
Circuit 51, each bit line 15 to 18, each memory cell 2e to 2h, and each transfer gate 25.
2 to 2 are respectively provided, and as shown in FIG. 2, they are connected by wirings 31 and 32 in the same manner as in FIG.

In this case, since the wiring lengths of the wirings 31 and 32 are long, the wirings 31 and 32 are connected to the bit lines 11 to 1 respectively.
The capacitive load given to 8 is greater than that of the DRAM shown in FIG. Nevertheless, compared with the conventional DRAM shown in FIG. 4, it is possible to improve the operation margin and reduce the power consumption.

Further, if more memory cells are sensed by one sense amplifier 1, a sense amplifier that is not activated during the refresh operation (a word line extending above the bit line is connected to a bit line that does not rise). (Sense amplifier) can be eliminated. That is,
Along with the increase in capacity of DRAM, some sense amplifiers are not activated during the refresh operation. However, a plurality of sense amplifiers that are not activated are included in one sense amplifier 1 described above.
Will be replaced with.

3) The wirings 31 and 32 are not formed on the uppermost layer of the chip, but are formed on an appropriate layer different from the bit lines 11 to 18. The material of the wirings 31 and 32 is not aluminum, but a low resistance material such as silicide or polycide.

4) Instead of connecting the nodes A to D between the two transfer gates (21 and 23, 22 and 24, 25 and 27, 26 and 28) and the wirings 31 and 32,
The transfer gates 21 to 28 are individually wired 31,
Connect to 32. For example, for the wiring 31, the transfer gates 21 to 24 are connected to different portions of the wiring 31.

[0051]

As described above in detail, according to the present invention, in the semiconductor memory device, it is possible to improve the operation margin and reduce the power consumption while reducing the chip size.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a DRAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of a DRAM according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of a main part of a conventional folded bit line type DRAM.

FIG. 4 is a circuit diagram of a main part of another conventional folded bit line type DRAM.

FIG. 5 is a circuit diagram of a main part of another conventional folded bit line type DRAM.

[Explanation of symbols]

 1 Sense Amplifier 11-18 Bit Line 21-28 Transfer Gate 31, 32 Wiring 41, 42 Bit Line Group WL1-WL8 Word Line

Claims (4)

[Claims] 1. A word line (WL1 to WL8) and a bit line (11 to 1) to which a one-transistor type memory cell is connected.
8), each transfer gate (21 to 28) provided for each bit line (11 to 18), and the same number of bit lines (11 to 14 and 15 to 18), respectively, which are in a reference relationship with each other. One bit line group (41, 42), one sense amplifier (1) provided for two bit line groups (41, 42), and each transfer of each bit line group (41, 42) The gates (21 to 24, 25 to 28) and the sense amplifier (1) are connected to each other, and each wiring (31,
32) and a semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the wirings (31, 32) are connected to the bit lines (1).
1 to 18), which is formed on a wiring layer different from that of the semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein each bit line (11 to 1) of one bit line group (41).
4) and each bit line (15) of the other bit line group (42)
~ 18) so that they are not adjacent in parallel to each bit line (1
1 to 18) are arranged in the semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein two bit line groups (41, 42) are arranged symmetrically with respect to the sense amplifier (1).