JPS5818715B2 - memory - Google Patents

Description

[Detailed description of the invention] The present invention relates to the structure of a memory cell.

Specifically, it relates to semiconductor memories, particularly MOS transistor memories.

Hereinafter, the present invention will be specifically explained in detail.

Conventionally, a memory using a MOS transistor that can selectively read out only memory cells provided at the intersection of a selection line and a data line is disclosed in the specification of Japanese Patent Application No. 49-5349 (Title of the Invention, Memory, Application No. 49. 1.9).

In other words, a plurality of memory cell selection lines, a plurality of data lines that intersect with the selection lines, a memory cell arranged at each of the intersection points, and a data line corresponding to the data line. A memory cell array consisting of control lines provided in the same direction, memory cells arranged at the intersections of each of the lines, a sense amplifier for detecting the output on the data line, and the plurality of control lines and selection lines. A memory has been disclosed that has means for selectively driving specific control lines and selection lines, and is configured such that only memory cells located at the intersections of these specific lines can be read.

The present invention relates to improvements in such memory.

In particular, when detecting a specific data memory cell, it is desirable to differentially detect the output of that memory cell and the output of a reference dummy cell.

However, when canceling the noise component between the outputs of the data memory cell and the dummy cell, it is desirable to arrange the memory cell and the dummy cell so that the noise generated in both is approximately equal.

However, the conventional arrangement of dummy cells
As stated in the specification of No. 349, the termie cells were arranged parallel to the selection line and on a different selection line from the data memory cells.

However, since these selection lines are actually slightly different, the noise originating from these selection lines is slightly different between the data memory cell and the termie cell, and it has been impossible to cancel them out completely.

In order to solve this problem, the present invention arranges a dummy cell on a specific control line, and detects the differential output of the data memory cell and the dummy cell on the same selection line.

Examples of the present invention will be specifically described below.

FIG. 1 is an explanatory diagram of an example of a memory cell that can be used in the present invention.

This is a prior application (patent application 1978-133078, November 1975)
The application was filed on April 7th, 2007, with the title of the invention being "semiconductor memory."

This is a memory cell using two layers of polysilicon (poly si).

That is, the electrode CP, data line control electrode DG, and word line W are made of polysilicon.

An oxide film indicated by IS is formed between CP, DG and the P-type substrate, and in particular, a thin oxide film is formed in a portion forming an inversion layer region.

This susceptible oxide film area is indicated by the bold line area in the figure.

The part directly below the CP in this bold line area becomes the storage capacity section.

IS is also configured between Ljs, cp and W.

The storage charge is stored in the inversion layer formed directly under the thin oxide film under the CP electrode, and by turning on the word line W, this charge is transferred from the inversion layer formed directly under the DG to the data line through the gate portion Q. The diffusion layer region KK is taken out through a data line formed of an inversion layer region formed under the electrode DG, and stored information is read out from the memory cell MC.

Writing to MC is performed by turning on W and supplying storage charge from K to MCK.

In such a cell, it is necessary to form an inversion layer directly under the DG and apply a DGK high voltage (hereinafter an example of n-channel MO8) in order to use this as a data line.

Conversely, by applying the DGK pulse voltage, a memory can be created in which only the memory cells at the intersections of word lines and data lines can be selected.

FIG. 2 is an example of the configuration of a memory arranged in a 2×2 matrix, and is an explanatory diagram of the operating principle of the memory cell.

The memory voltage currently stored directly under the CP or OV (tt Q
tt K compatible) and vDD (~10V, compatible with 〃1〃)
and W (WO, Wl) and DG (DGo.

Assume that a step-like pulse voltage from OV to vDD is applied to DGl).

In such a memory, only the MC to which voltage is applied to both W and DG is connected to the sense amplifier SA and the data input circuit D.
It is connected to the IC for reading and writing.

Even if applied to either one (for example, W.

on, DGo off) off DG (e.g. DG.

) Since no inversion layer is formed directly under Do(DG.

When it is on, an inversion layer is formed and becomes a data line).
It is separated from DIC8A.

Therefore, for example W. By selectively applying pulses to Wl, DGo, and DG, one MC can be selected from the 2×2 matrix.

In conventional dynamic memories of this type, all memory cells connected to a word line are read simultaneously, and these reads are destructive.
(Read Out, DRO), therefore, in order to rewrite, as many amplifiers as there are MCs to be simultaneously read out are required, which has the disadvantage of increasing the occupied area and power consumption.

On the other hand, this memory is always one step away from the memory matrix.
The advantage is that all of these drawbacks are eliminated because no MCL is read out.

Although the memory to which the present invention is applied has been explained using the memory cell having the structure shown in FIG. 1, it is clear that the present invention is not limited to this structure, and the memory cell MC as shown in FIG. , a gate Q controlled by the word line voltage and a gate controlled by the voltage of the data line control line DG) QD
MC with both gates turned on.
However, the output may be taken out onto the data line.

(In the examples shown in FIGS. 1 and 2, this gate QD is configured in a distributed manner by data lines and DG.

) The symbols in FIG. 3 have the same meanings as in FIG.

The memory cell used in the configuration of FIG. 3 can be configured as shown in FIG. 4.

Here, D is a data line formed by a diffusion layer, and a gate QD is formed between the data line control electrode DG and the substrate.
and is connected to the inversion layer formed under the electrode CP via the gate Q.

FIG. 5 is an example of another memory cell that can be used in the present invention.

The gate QD is turned on by DGo, and at this time, WoK
When m pressure is applied, this voltage turns on the gate Q, and MC at the intersection of Wo and DGoO is successively output.

In the above example, MC is made up of two gates Q, QD, and a storage partial capacitance forming capacitor C8.

However, it is also possible to form the gate and this memory storage part with the same element.

In any case, the present invention provides a memory having a word line, a data line, a control line arranged in the same direction as the data line, and a memory cell arranged at the intersection of these lines, and the word line and control line are selected as appropriate. By doing so, only the memory cells at the intersections thereof can be selected.

The present invention using the above-mentioned memory cell will be explained below.

FIG. 6 shows a circuit system using the MC shown in FIG.

This is an example in which a signal from a selected MC is detected differentially using a dummy cell DC for canceling noise when voltage is applied to the word line, as shown in FIG.

To select the MC connected to the even-numbered DG (DGo, DC2), turn on DDG 1; to select the MC connected to the odd-numbered DG (DGl, DC3), turn on DDGo. Just turn it on.

At this time, MC and DC are detected by CDT and σDTK, respectively, and detected by differential detector SA, and data D is obtained.

Output. Writing of data Di is performed by write circuit DIC.

The feature of this embodiment is that the MC and DC to be selected are connected on one word line, which makes it easy to cancel noise and simplify the word line drive circuit.

Furthermore, although FIG. 6 shows an example in which the common data lines CDT and CDT are taken out in the same direction, they can also be taken out from both sides as shown in FIG.

In general, the MO readout signal voltage as shown in Figure 1 is extremely small, so great care must be taken to prevent CDTs and CDT electrical imbalances (e.g. capacitance imbalances) due to mask misalignment that occurs during the manufacturing process. .

For example, if the capacitance of the CDT becomes too large than that of the CDT in FIGS. 5 and 8 due to mask displacement, the unbalance of this capacitance, etc. becomes noise due to constraints, and signals cannot be detected normally.

If CDT and CDT are crossed an odd number of times as shown in FIGS. 9 and 10, the capacitance will be completely balanced, and this drawback can be eliminated.

However, the figure shows an example of one-time crossover.

FIG. 11 shows an example of a memory configuration that utilizes this voltage matching read/write characteristic.

MA is a submatrix, which is 2×4 in the figure.

Each MA has a DIC and a SA as shown in FIG. 6, but they are omitted in the figure.

Wo, Wl-DGo-DG3 are commonly wired to each MA, and a pulse is selectively applied to Wo and Wl by the word drive circuit WD and address signal a2.

Similarly, DG leg circuit DGD and address signal a.

, one of DGo-DG3 and D
DGo.

A pulse is selectively applied to one of the DDG1.

As a result, the SIC signal in each MA is read out from one selected MC and termi cell in the MA, and a plurality of output signals from each SA are further selected (not shown in FIG. 2). ) only one is read out of the chip.

An important feature of FIG. 11 is that the MAs are simply connected by wiring, and the circuits (WD, DGD) that drive them can be concentrated and laid out in one location.

In conventional semiconductor memory, address decoders and drive circuits are arranged on each word line or each data line in each memory matrix, and the area occupied by these is considerably larger than that of MC, so the pitch of MC and The pitches of these circuits are no longer matched, and this is becoming a serious hindrance to higher integration.

On the other hand, Fig. 11 simply shows the wiring (this pitch is usually M
Since the only problem is that the pitch can be made smaller than the pitch of C, there is no obstacle to higher integration.

Figure 12 shows M, which has a particularly small pitch direction among MC.
C (The figure shows the word line direction as an example.

It is also assumed that the data line direction is sufficiently wide.

), FIG. 11 shows an example in which one readout signal is extracted from each MA, whereas one readout signal is extracted from an MA group consisting of a plurality of MAs.

First, turn on GCo-GC3 (high voltage), Woo, Wol
is turned on, all transistors corresponding to Q are turned on, and all word lines Woo-W3 are charged (precharged) to a high voltage.

At this time, DGo-DG is set to OV. Next KWD and address signal a4 discharge one of the unselected lines of Woo and Wol to Ov.

This causes the unselected word line of each MA to become Ov.

After this, control circuit REFC and address signals a5, a
6, only one selected line among GCo to Go2 is OVKed, and other non-selected lines are kept at high voltage.

After this, W becomes high voltage. 0 and W.

, to Ov. One of the word lines (Woo to W3) selected by the above operation, for example, W.

. ) only becomes high voltage, and all others become 0vvL.

After completing the above operations, use DGD and a□-a3 to
DG, the selected one (for example, DGo) K
Apply high voltage pulses.

By this W. Only the MC at the intersection of 0 and DGo can be selected.

The features of this embodiment compared to FIG. 3 are as follows.

Normally, if each Yυ also selects one MC, the SAs belonging to each MA must be operated because it is a destructive read.

When the general KSA is operated, the power consumption increases.

If a large number of SAs operate at the same time, the memo IJ L
Since this exceeds the allowable power consumption for the SI, it is necessary to minimize the power consumption of other peripheral circuits.

Considering that the product of power consumption and speed is generally constant, this means that it will be slower.

Therefore, the example shown in FIG. 12 can be said to be an embodiment suitable for high speed because the SA only operates in one bias.

Note that in a memory that is destructively read out simultaneously from all memory cells connected to one word line, such as a conventional so-called IMO8T cell formed with one transistor and a storage capacity, only one memory cell is selected. , the inability to selectively operate one SA (therefore, the speed is low) is readily apparent from the essential drawback of the IMO8T cell that it is forced to perform a rewrite operation, as described above.

The example in Figure 4 can be realized by using MC like the example in Figure 1.
This is due to the advantage that it operates in a voltage matching manner.

Note that since the MC shown in FIG. 1 is a dynamitter type MC, it must be periodically rewritten (refreshed).

In this case, it is generally said that it is more efficient to refresh multiple MCs at the same time.

This refresh operation can be performed in the example shown in FIG. 4 as follows.

That is, when the reflex command signal REF is valid, W
Either oo or Wol; (for example, W.

After discharging 1), if GCo-GC3 is set to V, Q
Since the transistor corresponding to is cutoff, Wo
OK was connected W.

0°Wlo, W2o, and W3o are held at high voltages.

If DGo is then turned on, the four MCs present at the intersections of the four word lines and DGo are selected, and the SAs in the MAs to which they belong operate to perform refresh.

In addition, W. It is clear that if the wiring pitch of the o-W31 is sufficiently large, a voltage can be applied to a selected word line by connecting a decoder and a drive circuit to each word line as in the conventional manner.

FIG. 13 is a specific example of FIG. 12.

As mentioned above, in FIG. 12, GCo is selected and becomes OVK, and only Woo is held at a high voltage, and then D
When Go turns on, the read signal from the MC becomes the 11th
It appears in CDT, CDT in the figure.

After that, when the AS set signal is turned on, this read signal is amplified by the flip-flop type SA.

After that, the control signal RWC is turned on and the data output line is activated.

, DoK output. If both Wo and Wl are unselected, G
Since Co becomes a high voltage, SA will not operate even if SET is turned on, and CDT and CD will not operate even if RWC is turned on.
T-hari.

The cut is made from yD6.

From the above, it has been found that a high-speed, highly integrated memory LSI can be realized by the present invention.

[Brief explanation of drawings]

1 to 5 are explanatory diagrams of a memory cell to which the present invention is applied, and FIGS. 6 to 13 are detailed explanatory diagrams of the present invention. Wo, Wl...word line, Do-D3...data line, DGo-Do3...control line, DD. ...Dummy data line, DDGo, DDGl...Dummy control line, SA...Sense amplifier, DGD...
Control line control circuit.

Claims (1)

[Claims] 1. A plurality of memory cells each of which is associated with a data line common to reading and writing, and which is arranged at the intersection of a plurality of selection lines and a control line that are orthogonal to each other. Reading and writing of information stored in a memory cell are performed when both the corresponding selection line and control line are selected. termy cells and the rest as data storage memory cells, select a single selection line from the plurality of selection lines, and make the outputs of the data storage memory cells and the differential detection terminal cells on this selection line differential. A memory characterized by detecting and reading data. 2. A memory according to claim 1, in which a plurality of termie cells are provided on the same selection line, and different termie cells are selected in correspondence with data memory cells on the selection line. 3. A memory according to claim 1, in which two termy cells are provided on the same selection line, and different termy cells are selected depending on whether the data memory cell is in an even numbered position or an odd numbered position. 4. The memory according to claim 1, in which dummy cells are provided only at the ends of each selection line. 5. In the memory according to claim 1, some of the plural data lines and the remaining plural data lines of each of the data lines are connected to each other to form first and second output lines,
After the output lines cross each other, the memory is connected to the detection means. 6. In the memory according to claim 1, a plurality of data lines and a plurality of remaining data lines of each of the data lines are respectively connected on different sides of the memory cell array. A memory serving as a second output line and connecting this output line to the detection means. 7 Claims 1, 2, 3, 4, and 5 in which the memory cell comprises a capacitor and a transistor
or the memory according to item 6. 8. It has a plurality of memory cells that are respectively associated with data lines common to reading and writing and arranged at the intersections of a plurality of selection lines and control lines that are orthogonal to each other, and each memory cell has a plurality of memory cells that are associated with data lines common to reading and writing, and are arranged at the intersections of a plurality of selection lines and control lines that are perpendicular to each other. In the memory IJ in which reading and writing are performed when both the corresponding selection line and control line are selected, each of the plurality of memory cells is grouped and arranged in a two-dimensional matrix as a memory cell array; Among the memory cells in each memory cell array, those arranged on a specific control line are used as differential detection memory cells, the rest are used as data storage memory cells, and each memory cell array is provided with the data storage memory. and detecting means for differentially detecting the cell and the dummy cell, and the detecting means detects the data storage on the selected line when a single selected line in the memory cell array is selected among the plurality of selected lines. A memory characterized in that outputs of a memory cell and a differential detection dummy cell are differentially detected. 9. A memory according to claim 8, in which corresponding selection lines of memory cell arrays in different rows are connected to each other. 10. A memory in which control lines corresponding to each other in memory cell arrays in different columns are connected in the memo IJ of claim 8. 11. A memory in which all memory arrays are provided with means for driving the selection line and control line in common in the memo IJ of claim 8. 12. Using a memory cell that requires refreshing as a memory cell in the memory according to claim 8,
A memory that drives a selection line and a control line to select mutually corresponding memory cells of a plurality of memory cell arrays in the same row or column during refreshing.