JPS63166092A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a dRAM with a large sense margin and to extend its refresh cycle by arranging dummy cells along dummy bit lines parallel to bit lines and selecting one dummy cell with one word line. CONSTITUTION:The dynamic type dRAM is provided with one dummy cell for each word line WL and also provided with a couple of dummy bit lines DBL for transferring information charges to and from those dummy cells DC; when a memory cell MC selected with some word line WL is connected to one bit line of a bit line couple PL, one dummy cell DC driven with this word line WL is connected to the other bit line BL from a dummy bit line DBL through a switch circuit. Only one dummy cell is therefore selected with one word line, so a reference potential written therein is left as it is for nearly the same time with the information potential of memory cells. Consequently, the potential of the dummy cell is fixed and the high sense margin is held for a long time.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a dynamic type R
Regarding AM (dRAM).

(Prior Art) In a dRAM in which dynamic memory cells of one transistor/one capacitor are arranged in a matrix, when reading the information charge of each memory cell, a bit with a sufficiently large capacity compared to the cell capacitor is used. Read through the line. Therefore, in order to correctly amplify the "H" and "L" levels of information, a highly sensitive sensing method is required. A typical dRAM uses a method of comparing and amplifying the voltage levels of a bit line connected to a memory cell to be read and a paired bit line connected to a dummy cell. Normally (1/2) VCC is written into the dummy cell so as to generate an intermediate potential between the "H" level read from the memory cell and the "L" level.

FIG. 4 shows a specific example of the configuration of a conventional dRAM array. This bit line (1/2) Vcc precharge method dR
The AM sensing operation will be briefly explained with reference to FIG.

Bit line pair BL during standby.

BL is controlled by the control signal EQL-“H2 so that VBL=(
1/2) Vcc is fixed at c. When the cell information read operation is started, the control signal EQL is set to "L", the bit lines BL and BL are set in a floating state, and then the selected word line WL is started, and the memory cell selected by this word line is activated. For example, B
Read out to L.

A dummy cell signal is read onto the bit line BL paired with this bit line by setting the dummy word line DWL to "H" level. Here, for the dummy cell, use one with the same capacity as the memory cell, and set it to VDC - (1/2) Vcc in advance.
If a level of Become. Therefore, these bit line pairs BL.

By amplifying the potential difference of BL with a sense amplifier, an equal sense margin can be obtained for "1" reading and "O" reading.

However, such conventional dRAM has the following problems. Since the storage node of a memory cell configured with one transistor/one capacitor becomes floating after the word line is closed, the charge stored as "1" information continues to decrease over time due to leakage. This is why refresh is required to rewrite "1" information every predetermined time. However, each time one memory cell is selected, half of the dummy cell is normally selected by two dummy word lines and rewritten each time, so the potential of (1/2) vcc is Fixed. Therefore, in order to correctly read out the "1" information of the memory cell, the sense amplifier's sensitivity is set to Δ■, and the memory cell potential is set to (1/2) V from VCC as shown in FIG.
It is not possible to leave the memory cell alone for longer than the time Δ for it to decay to CC1ΔV. This is a major obstacle to extending the refresh cycle of dRAM.

(Problems to be Solved by the Invention) In the conventional dummy cell method, as shown in [-], when the write level of a memory cell decays over time,
``There was a problem in that the read sense margin decreased and therefore the refresh cycle could not be made sufficiently long.

An object of the present invention is to provide a dRAM that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) A dRAM according to the present invention includes one dummy cell provided for each word line, and a pair of dummy bit lines for exchanging information charges with these dummy cells. When a memory cell selected by a certain word line is connected to one of the bit line pair, one dummy cell driven by this word line is connected to the dummy bit line via a switch circuit, and the memory cell is connected to one of the bit line pairs. is configured to be connected to the bit line of

(Function) With this configuration, only one dummy cell is selected by one word line, so the reference potential stored in it is left alone for the same amount of time as the information potential of the memory cell. . In other words, the potential of the dummy cell exhibits attenuation characteristics similar to that of the memory cell. As a result, a high sense margin can be maintained for a long time compared to the conventional method in which the potential of the dummy cell is fixed and only the information potential of the memory cell is reduced.

(Example) The present invention will now be described in detail.

FIG. 1 shows a schematic configuration of a dRAM according to an embodiment. ? M
fi memory cells MC are arranged in a matrix, and bit line pairs BL, B of the number of stages exchange information charges with them.
L (BLl, BL, , BL2.

BL2,...) are arranged. Memory cell MC has a well-known one-transistor/one-capacitor structure. Each bit line pair has a sense amplifier SA.
1. It is connected to SA2, .

A word line WL, which selects a memory cell MC.

One dummy cell DC is provided along WLO, -, WLn, and WLn. These dummy cells DC have the same structure as the memory cell MC, and the bit line B
Electric current is exchanged between a pair of dummy bit lines DBL and DBL arranged in parallel with L and BL. The dummy bit lines DBL, DBL are connected to the switching elements S1. It is connected to bit lines BL and BL via S2. Note that the selected dummy cell DC
The relationship between the memory cell MC and the word line (for example, WL
o) is driven so that the selected memory cell MC is connected to one of the bit line pair (for example, BLl),
A dummy cell DC driven by this word line is connected to the other bit line (BL, ).

The operation of the dRAM configured in this manner will be explained with reference to FIG. 2. When dRAM is on standby, all bit lines BL, B
L and dummy bit line DBL.

DBL has control signals EQLB and EQLD “H”, respectively.
By changing the level, it is precharged to (1/2) Vcc. When reading is started, the control signal EQLD,
Both EQLB become “L” level, and all bit lines BL,
BL and dummy bit lines DBL and DBL are in a floating state.

In this state, the selected word line WL+ (or WL
I) becomes "H" level, and thereby the information of memory cells MC and dummy cells DC along this word line is read to bit line BLi (or BLI) and dummy bit line DBL (or DBL), respectively. The potential change of the dummy bit line DBL (or DBL) is applied to the bit line BL via the buffer amplifier A2 (or A,) and the switch element S2 (or S,).
I (or BLi). In other words, the information of the memory cell and dummy cell selected by one word line is distributed and transmitted to the paired bit lines BL and BL. After this, the switch element s,
s2 is turned off to disconnect the dummy bit lines DBL, DBL from the bit lines BL, BT, and the sense amplifier SAI is activated by the sense amplifier activation signal SEN to start sensing the bit line pair BL, BL. Furthermore, before dropping the selected word line WLI (or WLI), the control signal EQ is
LDm is set to "H" level, and (1/2) Vcc is rewritten into the dummy cell selected by this word line.

FIG. 3 shows temporal changes in the memory cell potential and dummy cell potential of information "1" in this embodiment, in correspondence with FIG. 4 of the prior art. In this embodiment, as described in 1-1, only one dummy cell is selected by one word line, so the write level of the dummy cell also attenuates over time like that of the memory cell.

As a result, a high sense margin can be obtained even when left unused for a long time. In other words, the dRAM of this embodiment can have a longer refresh cycle than the conventional one.

It should be noted that the present invention is not limited to the second embodiment,
Various modifications can be made without departing from the spirit of the invention.

[Effects of the Invention] As described below, according to the present invention, dummy cells are arranged along dummy bit lines parallel to bit lines, and one dummy cell is selected by one word line. By this, the reference potential of the dummy cell can be attenuated in the same way as the write potential of the memory cell, and as a result, dRAM with a large sense margin can be obtained, and dRA
The refresh cycle of M can be made long.

Figure 1 is a diagram showing the configuration of a dRAM according to an embodiment of the present invention.
Figure 2 is a timing diagram to explain its operation, and Figure 3 is a timing diagram to explain its operation.
4 is a diagram showing the structure of a conventional general dRAM, and FIG. 5 is a timing diagram for explaining its operation.
FIG. 6 is a diagram showing how the write potentials of the memory cell and dummy cell change.

MC...memory cell, DC...dummy cell, BL.

BL...Bit line, DBL, DBL...Dummy bit line, WL, WL...Word line, SAj...Sense amplifier, A,, A2...Buffer amplifier, s,, s2
...Switch element.

Applicant's agent Patent attorney 1: Takehiko Suzue Figure 3

Claims (4)

[Claims] (1) Multiple dynamic memory cells arranged in a matrix, multiple pairs of bit lines that exchange information with these memory cells and are connected to sense amplifiers, and lines that intersect with these bit line pairs. In a semiconductor memory device having a plurality of word lines arranged for selecting memory cells, a pair of dummy bit lines arranged parallel to the bit line pair and a dummy bit line selected by the word line are provided. A plurality of dummy cells exchange reference signal charges with one of the pairs, and when a certain word line is selected and the selected memory cell is connected to one of the bit line pair, this word line A semiconductor memory device comprising: a switch circuit that connects a dummy bit line to which a selected dummy cell is connected to the other bit line. (2) The semiconductor memory device according to claim 1, wherein the dummy cell is written with (1/2)V_c_c. (3) The semiconductor memory device according to claim 1, wherein the dummy cell has the same structure as a memory cell. (4) The semiconductor memory device according to claim 1, wherein the dummy bit line is connected to the bit line selected by the switch circuit via a buffer amplifier with an amplification factor of 1.