JP2009048772A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with a memory cell in which refresh operation is not required, also high integration and large capacity can be achieved. <P>SOLUTION: Two memory cells 50A, 50B are provided for storage data of one bit, the memory cells 50A, 50B store data being inverted mutually. The memory cells 50A, 50B include electric charges compensation circuit 56A, 56B constituted respectively of inverters, the electric charges compensation circuits 56A, 56B include P channel TFTs 562, 566 which can be formed on upper layers of bulk transistors respectively. The electric charge compensation circuits 56A, 56B are cross-connected, and latch data stored in the memory cells 50A, 50B. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that stores stored information depending on whether or not a capacitor constituting a memory cell is charged.

  DRAM (Dynamic Random Access Memory), which is one of the typical semiconductor memory devices, has a memory cell configuration of one element type (one transistor and one capacitor), and the structure of the memory cell itself is simple. It is used in various electronic devices as the most suitable for high integration and large capacity of semiconductor devices.

  FIG. 9 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a DRAM.

  Referring to FIG. 9, memory cell 500 includes an N channel MOS transistor 502 and a capacitor 504. N channel MOS transistor 502 is connected to bit line 508 and capacitor 504, and has its gate connected to word line 506. The other end of capacitor 504 different from the connection end with N channel MOS transistor 502 is connected to cell plate 510.

  N channel MOS transistor 502 is driven by word line 506 activated only at the time of data writing and data reading, and is turned on only at the time of data writing and data reading, and is turned off at other times.

  The capacitor 504 stores binary information “1” and “0” depending on whether or not charges are accumulated. The voltage corresponding to the binary information “1”, “0” is applied to the capacitor 504 from the bit line 508 via the N-channel MOS transistor 502, whereby the capacitor 504 is charged / discharged and data is written. .

  That is, when data “1” is written, bit line 508 is precharged to power supply voltage Vcc, and word line 506 is activated to turn on N channel MOS transistor 502, and bit line 508 to N The power supply voltage Vcc is applied to the capacitor 504 through the channel MOS transistor 502, and electric charge is stored in the capacitor 504. The state where electric charge is stored in the capacitor 504 corresponds to data “1”.

  When data “0” is written, bit line 508 is precharged to ground voltage GND, and word line 506 is activated to turn on N channel MOS transistor 502, and capacitor 504 starts N channel. Charge is discharged to the bit line 508 via the MOS transistor 502. The state in which no charge is stored in the capacitor 504 corresponds to the stored data “0”.

  On the other hand, when data is read, bit line 508 is precharged to voltage Vcc / 2 in advance, and word line 506 is activated to turn on N channel MOS transistor 502, and bit line 508 and capacitor 504 are activated. Is energized. As a result, a minute voltage change corresponding to the storage state of capacitor 504 appears on bit line 508, and a sense amplifier (not shown) amplifies the minute voltage change to voltage Vcc or ground voltage GND. The voltage level of bit line 508 corresponds to the state of the read data.

  Since the data reading operation described above is destructive reading, word line 506 is activated again in a state where bit line 508 is amplified to voltage Vcc or ground voltage GND in accordance with the read data, and The capacitor 504 is recharged by the same operation as the data writing operation. As a result, the data once destroyed returns to the original state in accordance with the data reading.

  Here, in the DRAM memory cell, the charge of the capacitor 504 corresponding to the stored data leaks due to various factors and is gradually lost. That is, the stored data is lost with time. Therefore, in the DRAM, a refresh operation is performed in which data is once read and written again before the voltage change of the bit line 508 corresponding to the stored data can no longer be detected.

  DRAMs must always perform this refresh operation periodically for all memory cells. In this respect, DRAM has the disadvantage of higher speed and lower power consumption, and does not require a refresh operation SRAM (Static Random Access). Memory) is inferior from the viewpoint of higher speed and lower power consumption. However, since the DRAM has a simple memory cell structure and can be highly integrated as described above, the cost per bit is much lower than that of other memory devices, and the mainstream of the current RAM. It has become.

  On the other hand, an SRAM, which is one of typical semiconductor memory devices together with a DRAM, is a RAM that does not require a refresh operation that is essential in a DRAM, as described above.

  FIG. 10 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a 6-transistor SRAM.

  Referring to FIG. 10, memory cell 700 includes N channel MOS transistors 702 to 708, P channel MOS transistors 710 and 712, and storage nodes 714 and 716.

  Memory cell 700 includes two flip-flops in which an inverter made up of N-channel MOS transistor 702 and P-channel MOS transistor 710 and an inverter made up of N-channel MOS transistor 704 and P-channel MOS transistor 712 are cross-connected as transfer gates. The N-channel MOS transistors 706 and 708 are connected to the bit line pair 718 and 720.

  In memory cell 700, the voltage level state of storage nodes 714 and 716 corresponds to the storage data, for example, when storage nodes 714 and 716 are at the H level and the L level, respectively, corresponds to storage data “1”. The reverse state corresponds to the stored data “0”. The data on the storage nodes 714 and 716 that are cross-connected is in a bistable state, and the state continues to be maintained as long as a predetermined power supply voltage is supplied. It is fundamentally different from DRAM that disappears along with it.

  In memory cell 700, when data is written, opposite voltages corresponding to the write data are applied to bit line pair 718 and 720, word line 722 is activated and transfer gates 706 and 708 are turned on. As a result, the state of the flip-flop is set. On the other hand, to read data, the word line 722 is activated to turn on the transfer gates 706 and 708, and the potentials of the storage nodes 714 and 716 are transmitted to the bit lines 718 and 720. This is done by detecting changes.

  Although the memory cell 700 is configured by six bulk transistors, there is an SRAM including a memory cell that can be configured by four bulk transistors.

  FIG. 11 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a 4-transistor SRAM.

  Referring to FIG. 11, in memory cell 750, instead of P channel MOS transistors 710 and 712 in memory cell 700, P channel thin film transistors (P channel thin film transistors) are hereinafter referred to as “TFTs”. .) 730, 732 are provided. A high resistance may be used for the P-channel TFTs 730 and 732. Note that “four transistors” in the four-transistor SRAM is used to mean that one memory cell includes four bulk transistors. The term “bulk” is used to mean that a TFT is formed on a substrate, whereas a transistor is built in a silicon substrate. Hereinafter, a transistor built in a silicon substrate with respect to a thin film element formed on the substrate like a TFT is referred to as a “bulk transistor”.

  Since the operation principle of memory cell 750 is basically the same as that of memory cell 700, description thereof will not be repeated.

  Since the P-channel TFTs 730 and 732 are formed in the upper layer of the N-channel MOS transistors 702 and 704, the 4-transistor SRAM has an advantage that the cell area can be reduced as compared with the 6-transistor SRAM. Compared to the recent trend toward lower voltage required for semiconductor memory devices, the low voltage characteristics are inferior to those of the recent semiconductor memory devices.

  As described above, the currently mainstream DRAM of a single memory cell is suitable for high integration and large capacity because the structure of the memory cell is simple, but refresh operation is indispensable.

  In the conventional DRAM, when data is read, the voltage of the word line that drives the access transistor needs to be boosted from the power supply voltage in order to completely transmit the state of the charge held by the capacitor of the memory cell to the bit line. Therefore, the potential of the capacitor after data reading is close to the precharge voltage ½ Vcc of the bit line. Therefore, the data is read and destroyed, and after the data is read, a data rewrite operation is required.

  On the other hand, the SRAM does not require a refresh operation, but requires six or four bulk transistors. In addition, in order to stabilize the operation of the SRAM, a current drive capability ratio (referred to as a cell ratio) between N-channel MOS transistors 702 and 704 called driver transistors and N-channel MOS transistors 706 and 708 called access transistors in FIGS. 2) to 3 or more, and the gate width of the driver transistor needs to be designed to be large. Therefore, the SRAM has a large memory cell and cannot cope with high integration and large capacity.

  Thus, both conventional DRAM and SRAM have advantages and disadvantages in their characteristics and structure.

  However, in the future, coupled with further development of IT technology, there is a great expectation for a semiconductor memory device that satisfies both high performance (high speed and low power consumption) and high integration and large capacity.

  Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device including a memory cell that does not require a refresh operation and realizes high integration and large capacity. Is to provide.

  Another object of the present invention is to provide a semiconductor memory device including a memory cell that does not require a refresh operation, and further speeds up access to stored data and further increases the operation speed. .

  Furthermore, another object of the present invention is to provide a semiconductor memory device including a memory cell that does not require a refresh operation, can read data without destroying stored data, and further increases the operation speed. It is to be.

Means for Solving the Problems and Effects of the Invention

  According to the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix, a plurality of word lines and a plurality of bit line pairs arranged for each row and column of the memory cells. Each of the plurality of memory cells includes a first memory cell that stores 1-bit data of storage information represented by binary information, and a second memory cell that stores inverted data obtained by inverting the data And the first memory cell is driven by a voltage applied to the word line and the first capacitor element that holds a charge corresponding to the logic level of data, and the first memory cell A first access transistor that exchanges charges with one capacitive element, and a first charge compensation circuit that compensates for a charge leaked from the first capacitive element. A second capacitor element that holds charges according to the logic level of the inverted data and a voltage applied to the word line, and is charged between the other bit line of the bit line pair and the second capacitor element. It consists of a second access transistor that exchanges and a second charge compensation circuit that compensates for charge leaking from the second capacitor.

  In the semiconductor memory device according to the present invention, each of the plurality of memory cells includes first and second memory cells storing data inverted with respect to each other, and the first memory cell leaks from the first capacitive element. The first memory cell includes a first charge compensation circuit that compensates for charges, and the second memory cell includes a second charge compensation circuit that compensates for charges leaking from the second capacitor element.

  Therefore, according to the present invention, loss of stored information due to leakage of charges can be prevented without performing a refresh operation.

  Preferably, the first and second charge compensation circuits are configured by first and second inverters, respectively, and an output node of the first charge compensation circuit connects the first capacitive element to the first access transistor. Connected to the first storage node, and the input node of the first charge compensation circuit is connected to the second storage node connecting the second capacitor element to the second access transistor, and the second charge compensation circuit Are connected to the second storage node, and the input node of the second charge compensation circuit is connected to the first storage node.

  The first and second charge compensation circuits are configured by first and second inverters, respectively, and the first and second inverters are cross-connected.

  Therefore, according to the present invention, the first and second inverters constitute a latch function, and the storage information can be stably held in the first and second storage nodes.

  Preferably, each of the first and second access transistors is a first N-channel MOS transistor, and one of each of the first and second inverters is connected to the power supply node and the other is connected to the output node. And a second N-channel MOS transistor having one connected to the output node and the other connected to the ground node.

  Bulk transistors included in the first and second memory cells are all formed of N-channel MOS transistors, and a resistance element formed of polycrystalline polysilicon is provided in each of the first and second inverters. Used.

  Therefore, according to the present invention, it is not necessary to provide a well region of two conductivity types when forming a memory cell, and further, a resistance element made of polycrystalline polysilicon can be formed in the upper layer of the bulk transistor. The size of the memory cell can be further reduced.

  Preferably, the current driving capability of the second N-channel MOS transistor is not less than 1 and not more than twice the current driving capability of the first N-channel MOS transistor.

  Since this memory cell includes a capacitive element, the current driving capability of the second N-channel MOS transistor that is a driver transistor is not less than 1 and not more than twice that of the first N-channel MOS transistor that is an access transistor. However, the data reading operation is performed stably.

  Therefore, according to the present invention, the current drive capability of the second N-channel MOS transistor does not need to be 2 to 3 times or more that is normally required with respect to the current drive capability of the first N-channel MOS transistor. The second N-channel MOS transistor can be reduced in size, and the size of the memory cell can be reduced.

  Preferably, when data is read from each of the plurality of memory cells, a voltage equal to or lower than the power supply voltage is applied to the word line corresponding to each of the plurality of memory cells.

  Since this memory cell includes a charge compensation circuit, data can be read at a voltage lower than the power supply voltage without boosting the voltage of the word line that drives the access transistor.

  Therefore, according to the present invention, the potential change of the storage node can be reduced during data reading, and nondestructive reading is realized.

  Preferably, the voltage applied to the word line corresponding to each of the plurality of memory cells is such that the current driving capability of the first N-channel MOS transistor is more than half of the current driving capability of the second N-channel MOS transistor. Set to

  The current driving capability of the access transistor needs to be secured to some extent so as not to deteriorate the accessibility to data stored in the memory cell. On the other hand, the voltage applied to the word line is set so that the current driving capability of the access transistor is more than half of the current driving capability of the second N-channel MOS transistor which is the driver transistor. However, since this memory cell includes a capacitive element, the operation of the memory cell is stabilized.

  Therefore, according to the present invention, the operation of the memory cell is stable even if the cell ratio is 2 or less while securing the current drive capability of the access transistor so as not to deteriorate the accessibility to data.

Preferably, the resistance element is composed of a P-channel thin film transistor.
Therefore, according to the present invention, since the P-channel thin film transistor can be formed in the upper layer of the bulk transistor, the size of the memory cell can be reduced.

  Preferably, the resistance element has a current supply capability of 10 times or more of a leakage current leaking from the first and second storage nodes.

  The resistance element can supply a current necessary for sufficiently maintaining the charged state of the storage node, and stabilizes the state of the storage node.

  Therefore, according to the present invention, data can be stably stored in the memory cell.

  Preferably, each of the first and second charge compensation circuits includes first and second P-channel thin film transistors, and one of the first P-channel thin film transistors is connected to a power supply node, and the first capacitive element is The other is connected to the first storage node connected to the first access transistor, the gate is connected to the second storage node connecting the second capacitor element to the second access transistor, and the second P-channel thin film transistor One is connected to the power supply node, the other is connected to the second storage node, and the gate is connected to the first storage node.

  The first and second charge compensation circuits are configured by first and second P-channel thin film transistors, respectively, and the first and second P-channel thin film transistors are cross-connected.

  Therefore, according to the present invention, the first and second P-channel thin film transistors constitute a latch function, and the storage information can be held in the first and second storage nodes.

  Preferably, the first and second memory cells are arranged adjacent to each other, and one bit line and the other bit line are wired in parallel.

  Therefore, according to the present invention, noise of the bit line pair can be reduced during the data read operation.

  In addition, according to the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix, and a plurality of word lines and a plurality of bit lines arranged for each row and column of the memory cells. And a plurality of internal signal lines arranged for each row of memory cells, each of the plurality of memory cells depending on the logic level of data for one bit of storage information represented by binary information A capacitive element that holds charge, a first transistor that is driven by a voltage applied to the word line, and exchanges charges between the bit line and the capacitive element, and a charge that leaks from the capacitive element is a data logic level. And a second transistor connected between the storage node connecting the capacitor element to the first transistor and the charge compensation circuit. , The second transistor is driven by a voltage applied to the internal signal line, to isolate the charge compensating circuit in the read data and the storage node.

  In the semiconductor memory device according to the present invention, each of the plurality of memory cells is connected to a charge compensation circuit that compensates for a charge leaked from a capacitive element that retains a charge corresponding to a logic level of stored information, and the capacitive element is connected to an access transistor. And a second transistor connected between the storage node and the charge compensation circuit and separating the charge compensation circuit from the storage node when reading data.

  Therefore, according to the present invention, it is possible to prevent loss of stored information due to charge leakage without performing a refresh operation, and it is possible to read data nondestructively.

  Preferably, the charge compensation circuit includes a first inverter whose input node is connected to the second transistor, an input node connected to the output node of the first inverter, and an output node connected to the input node of the first inverter. The first and second transistors are first and second N-channel MOS transistors, respectively, and one of the first and second inverters is connected to the power supply node. The P channel thin film transistor is connected to the output node and the other is connected to the output node. The third N channel MOS transistor is connected to the output node and the other is connected to the ground node.

  All the bulk transistors included in the memory cell are composed of N-channel MOS transistors, and a P-channel thin film transistor is used as a part of each of the first and second inverters.

  Therefore, according to the present invention, it is not necessary to provide a well region of two conductivity types when forming a memory cell. Further, since the P-channel thin film transistor can be formed in the upper layer of the bulk transistor, the size of the memory cell is further reduced. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
1 is a schematic block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention.

  Referring to FIG. 1, the semiconductor memory device 10 includes a control signal terminal 12, a clock terminal 14, an address terminal 16, and a data input / output terminal 18. The semiconductor memory device 10 includes a control signal buffer 20, a clock buffer 22, an address buffer 24, and an input / output buffer 26. The semiconductor memory device 10 further includes a control circuit 28, a row address decoder 30, a column address decoder 32, a sense amplifier / input / output control circuit 34, and a memory cell array 36.

  FIG. 1 representatively shows only the main part related to data input / output of semiconductor memory device 10.

  Control signal terminal 12 receives command control signals of chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE. Clock terminal 14 receives external clock CLK and clock enable signal CKE. Address terminal 16 receives address signals A0 to An (n is a natural number).

  Clock buffer 22 receives external clock CLK, generates an internal clock, and outputs the internal clock to control signal buffer 20, address buffer 24, input / output buffer 26, and control circuit 28. Control signal buffer 20 takes in and latches chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE in accordance with the internal clock received from clock buffer 22 for control. Output to the circuit 28. Address buffer 24 takes in and latches address signals A0-An according to the internal clock received from clock buffer 22, generates an internal address signal, and outputs it to row address decoder 30 and column address decoder 32.

  The data input / output terminal 18 is a terminal for exchanging data read / written in the semiconductor memory device 10 with the outside, and receives data DQ0 to DQi (i is a natural number) input from the outside at the time of data writing to read data. At this time, data DQ0 to DQi are output to the outside.

  Input / output buffer 26 takes in and latches data DQ0 to DQi in accordance with an internal clock received from clock buffer 22 and outputs internal data IDQ to sense amplifier / input / output control circuit 34 at the time of data writing. On the other hand, input / output buffer 26 outputs internal data IDQ received from sense amplifier / input / output control circuit 34 to data input / output terminal 18 in accordance with an internal clock received from clock buffer 22 during data reading.

  The control circuit 28 takes in the command control signal from the control signal buffer 20 in accordance with the internal clock received from the clock buffer 22, and the row address decoder 30, the column address decoder 32, and the input / output buffer 26 based on the fetched command control signal. To control. As a result, the data DQ0 to DQ15 are read from and written to the memory cell array 36.

  The row address decoder 30 selects a word line on the memory cell array 36 corresponding to the address signals A0 to An based on an instruction from the control circuit 28, and activates the word line selected by a word driver (not shown). The column address decoder 32 selects a bit line pair on the memory cell array 36 corresponding to the address signals A0 to An based on an instruction from the control circuit 28.

  Sense amplifier / input / output control circuit 34 applies the bit line pair selected by column address decoder 32 to power supply voltage Vcc or ground voltage according to the logic level of internal data IDQ received from input / output buffer 26 at the time of data writing. Precharge to GND. As a result, on the memory cell array 36 connected to the word line activated by the row address decoder 30 and the bit line pair selected by the column address decoder 32 and precharged by the sense amplifier / input / output control circuit 34. Internal data IDQ is written into the memory cell.

  On the other hand, at the time of data reading, sense amplifier / input / output control circuit 34 precharges the bit line pair selected by column address decoder 32 to voltage Vcc / 2 before reading the data, and reads the selected bit line pair. A minute voltage change generated corresponding to the data is detected / amplified to determine the logical level of the read data and output to the input / output buffer 26.

  The memory cell array 36 is a storage element group in which memory cells to be described later are arranged in a matrix. The memory cell array 36 is connected to the row address decoder 30 via a word line corresponding to each row, and a bit line pair corresponding to each column. To the sense amplifier / input / output control circuit 34.

  FIG. 2 is a circuit diagram showing a configuration of memory cells arranged in a matrix on the memory cell array 36 in the semiconductor memory device 10.

  Referring to FIG. 2, the memory cell in semiconductor memory device 10 is assigned two memory cells 50 </ b> A and 50 </ b> B each storing 1-bit data and data obtained by inverting the data. It takes the structure of a twin memory cell. Memory cell 50A includes an N-channel MOS transistor 52A, a capacitor 54A, and a charge compensation circuit 56A. Memory cell 50B includes an N-channel MOS transistor 52B, a capacitor 54B, and a charge compensation circuit 56B.

  N channel MOS transistor 52A is connected to one bit line 68A and capacitor 54A of bit line pair 68A, 68B, and has its gate connected to word line 66. N-channel MOS transistor 52A is driven by word line 66 activated only at the time of data writing and data reading, and is turned on only at the time of data writing and data reading, and is turned off at other times.

  The capacitor 54A stores binary information “1” and “0” depending on whether or not charges are accumulated. Capacitor 54A has one end connected to N channel MOS transistor 52A and the other end connected to cell plate 70. Then, a voltage corresponding to the binary information “1”, “0” is applied to the capacitor 54A from the bit line 68A via the N-channel MOS transistor 52A, whereby the capacitor 54A is charged and discharged, and data is written. Done.

  The charge compensation circuit 56A is composed of an inverter composed of a P-channel TFT 562 and an N-channel MOS transistor 564, and an input node and an output node of this inverter are connected to nodes 64 and 62, respectively.

  N channel MOS transistor 52B is connected to the other bit line 68B and capacitor 54B of bit line pair 68A, 68B, and has its gate connected to word line 66. N-channel MOS transistor 52B is driven by word line 66 common to N-channel MOS transistor 52A, and is turned on only during data writing and data reading, and is turned off otherwise.

  The capacitor 54B stores binary information “1” and “0” depending on whether or not charges are accumulated. Capacitor 54B has one end connected to N channel MOS transistor 52B and the other end connected to cell plate 70. Then, by applying a voltage corresponding to the binary information “1” and “0” to the capacitor 54B from the bit line 68B via the N-channel MOS transistor 52B, the capacitor 54B is charged and discharged, and data is written. Done. Capacitor 54B stores data obtained by inverting the storage data stored in capacitor 54A.

  The charge compensation circuit 56B is composed of an inverter composed of a P-channel TFT 566 and an N-channel MOS transistor 568. The input node and output node of this inverter are connected to nodes 62 and 64, respectively.

  The configurations of N channel MOS transistor 52A and capacitor 54A, and N channel MOS transistor 52B and capacitor 54B are the same as those of a general DRAM.

The P-channel TFTs 562 and 566 are resistive elements having a switching function, which are made of polycrystalline polysilicon, and have an OFF resistance of T (terra, “T” represents 10 ¹² ) Ω and G (giga, “ “G” represents 10 ^9. ) A high resistance element having an ON resistance on the order of Ω.

  In the present invention, in the case of a resistance element, both the one having a switching function and the one having a constant resistance are shown.

  P-channel TFT 562 is connected to power supply node 72 and node 62, and the gate is connected to node 64. N channel MOS transistor 564 is connected to node 62 and ground node 74, and has its gate connected to node 64.

  P-channel TFT 566 is connected to power supply node 72 and node 64, and the gate is connected to node 62. N channel MOS transistor 568 is connected to node 64 and ground node 74, and has its gate connected to node 62.

  In the memory cell in the semiconductor memory device 10, they are mutually inverted by a latch function of the inverter constituted by the P channel TFT 562 and the N channel MOS transistor 564 and the inverter constituted by the P channel TFT 566 and the N channel MOS transistor 568. The leakage currents of the capacitors 54A and 54B that hold data are compensated, and the stored data is held without performing the refresh operation.

Hereinafter, the operation of the memory cell in the semiconductor memory device 10 will be described.
(1) Data writing In these memory cells 50A and 50B, the ON current of the bulk transistor is about 3 × 10 ⁻⁵ A (ampere), and the ON current and OFF current of the TFT are 1 × 10 ⁻¹¹ A, respectively. And about 1 × 10 ⁻¹³ A. The leakage current from the nodes 62 and 64 due to the OFF current of the bulk transistor is about 1 × 10 ⁻¹⁵ A. The current values shown here are not limited to these numerical values, but indicate orders of these degrees.

  If the current values are as described above, the ON currents of the P-channel TFTs 562 and 566 exceed the leakage currents from the nodes 62 and 64 by 4 digits, respectively, so that the nodes 62 and 64 can be charged from the power supply node 72 to the power supply voltage. it can.

  Now, when data “0” is written in the memory cell 50A, the voltage of the node 62 becomes 0V. However, the node 64 has the normal write operation time n only by the node 62 becoming 0V. (Nano, “n” represents 10 −9) The power supply voltage is not charged from the power supply node 72 in the order of seconds. This is shown in the following equation.

When the power supply voltage of the power supply node 72 is 2 V and the capacity of the node 64 is several fF (f (femto) farad, “f” represents 10 ⁻¹⁵ ), for example, 5 fF, the following equation is established at the node 64.

Charge Q = capacitance C × voltage V = 5f × 2 = 1 × 10 ⁻¹⁴
ON-current I of P-channel TFT 582 I = 1 × 10 ⁻¹¹ amperes Charging time t = Q / I = 1 × 10 ⁻³ seconds (i)
Therefore, in order to charge the node 64 only by the node 62 becoming 0 V, it takes a time on the order of μ (micro, “μ” represents 10 ⁻⁶ ) seconds to m (millisecond) seconds. Therefore, even if the voltage of the node 62 becomes 0V, the node 64 is not immediately charged, and the node 62 is charged again via the P-channel TFT 562.

  However, in the memory cell in the semiconductor memory device 10, data “1” is written into the memory cell 50B at the same time as data “0” is written into the memory cell 50A, and the node 64 is connected to the bit line 68B. The power supply voltage is immediately charged via the N-channel MOS transistor 52B in a write operation time on the order of n (nano) seconds. As a result, N-channel MOS transistor 564 is immediately turned ON, whereby node 62 is held at 0V. In addition, N channel MOS transistor 568 is turned off and maintained in accordance with the fact that node 62 immediately becomes 0 V and the state is maintained, so that node 64 is held at the power supply voltage.

  In this way, nodes 62 and 64 correspond to 0 V and the power supply voltage, respectively, corresponding to data “0” and “1” written in memory cells 50A and 50B, respectively. Latched by interlocking 56A and 56B, the state of the written data is maintained without performing a refresh operation thereafter.

  Since the memory cells 50A and 50B have the same circuit configuration, the data “1” is written in the memory cell 50A and the data “0” is written in the memory cell 50B correspondingly, as described above. Since the operations similar to those described above are performed only by switching the operations of memory cells 50A and 50B, the description thereof will not be repeated.

(2) Data Reading Data reading from the memory cells in the semiconductor memory device 10 is performed in the memory cells 50A and 50B by the same operation as a general DRAM. That is, the bit lines 68A and 68B are precharged to the voltage Vcc / 2 in advance, and when reading data, the boosted power supply voltage is applied to the word line 66 and the word line 66 is activated. As a result, the N channel MOS transistors 52A and 52B are turned on in the memory cells 50A and 50B, respectively, and the minute voltage changes appearing on the bit lines 68A and 68B according to the storage states of the capacitors 54A and 54B are caused by the sense amplifier (not shown). In comparison, the voltage of the bit line pair 68A, 68B is amplified to either the voltage Vcc or the ground voltage GND according to the direction of voltage change from the precharge voltage 1 / 2Vcc. The voltage level of bit line 68A corresponds to the state of stored data.

  Here, in semiconductor memory device 10 having a twin memory cell configuration, data can be read at a higher speed than a semiconductor memory device having a single memory cell. This is due to the following reason. In a semiconductor memory device having a single memory cell, the voltage of the bit line is compared with a precharge voltage ½ Vcc. On the other hand, in the semiconductor memory device 10, since the memory cells 50A and 50B each store inverted data, the voltage of the bit line pair 68A and 68B is the precharge voltage 1 / The voltage changes slightly in the opposite direction from 2 Vcc, and the potential difference between the bit line pairs 68A and 68B is directly compared by the sense amplifier. Therefore, in semiconductor memory device 10, data is detected with twice the amplitude by the sense amplifier as compared with the semiconductor memory device having a single memory cell, and data is read from the memory cell at high speed.

  When data is read, word line 66 is activated again while the voltage of bit line pair 68A, 68B is amplified to either voltage Vcc or ground voltage GND, and N channel MOS transistor 52A is activated. , 52B, capacitors 54A, 54B are recharged, respectively. In this way, data is rewritten by the same operation as (1) described above.

  Here, in the semiconductor memory device 10, the voltage applied to the word line 66 at the time of data reading can be set to a voltage equal to or lower than the power supply voltage without using the boosted power supply voltage.

  When the voltage applied to the word line 66 is a boosted voltage of the power supply voltage, the data stored in the memory cells 50A and 50B is destroyed when data is read, and the data needs to be rewritten. This is due to the following reason. That is, the potential of node 62 after data reading is determined by the capacitance of bit line 68A and the capacitance of capacitor 54A, and the potential of node 64 after data reading is determined by the capacitance of bit line 68B and the capacitance of capacitor 54B. Here, since the capacity of bit line pair 68A, 68B is more than 10 times the capacity of capacitors 54A, 54B, the potential of nodes 62, 64 after data reading is higher than the potential before data reading. This is because it is close to the potential of 68B.

  However, unlike a general DRAM, the memory cell in semiconductor memory device 10 includes charge compensation circuits 56A and 56B. Charge compensation circuits 56A and 56B each include an N-channel MOS transistor 564 and a node connected to node 62. 64 includes an N channel MOS transistor 568 connected to 64. By the action of these N-channel MOS transistors 564 and 568, the voltage of the word line 66 can be made lower than the power supply voltage without being boosted. The reason will be described below.

  When data “0” and “1” are stored in memory cells 50A and 50B, respectively, N channel MOS transistors 564 and 568 are ON and OFF, respectively, and N channel MOS transistor 564 is charged from node 62. N channel MOS transistor 568 does not extract charge from node 64.

  On the other hand, when data “1” and “0” are stored in memory cells 50A and 50B, N-channel MOS transistors 564 and 568 are OFF and ON, respectively, and N-channel MOS transistor 564 is connected to node 62. The N channel MOS transistor 568 draws charges from the node 64 without drawing charges from the node 64.

  Therefore, the charge compensation circuits 56A and 56B also have a function of whether or not the charges of the nodes 62 and 64 are extracted by the N-channel MOS transistors 564 and 568 when reading data. With this function, it is possible to read data without completely transmitting the charge states of the capacitors 54A and 54B to the bit lines 68A and 68B, respectively.

  Hereinafter, a case where data “0” and “1” are stored in memory cells 50A and 50B, respectively, and data is read will be described. In the case where data “1” and “0” are stored in memory cells 50A and 50B, respectively, the operation of memory cells 50A and 50B is simply switched, and the description in that case will not be repeated.

  At the time of reading data, in memory cell 50A, N channel MOS transistor 564 extracts the charge flowing from bit line 68A via N channel MOS transistor 52A. Therefore, even if the voltage on word line 66 is not boosted, The voltage of the line 68A drops from the precharge voltage ½ Vcc to such an extent that data “0” can be detected. On the other hand, the voltage change at node 62 is suppressed to a small range from 0 V because N-channel MOS transistor 564 has extracted the charge on node 62.

  On the other hand, in memory cell 50B, the change in voltage at node 62 is suppressed to a small range from 0 V due to the effect of extracting the charge on node 62 by N channel MOS transistor 564, so that N channel MOS transistor 568 maintains the OFF state. N channel MOS transistor 568 does not extract charge from node 64. Since the P-channel TFT 566 supplements the charge flowing out from the node 64 to the bit line 68B via the N-channel MOS transistor 52B, the voltage of the bit line 68B is not changed even if the voltage of the word line 66 is not boosted. The precharge voltage rises from 1/2 Vcc to such an extent that “1” can be detected.

  Since the ON current of the P-channel TFT 566 is smaller than the ON current of the N-channel MOS transistor 52B, the voltage at the node 64 is close to the precharge voltage 1/2 Vcc immediately after the N-channel MOS transistor 52B is turned on. Although the power supply voltage Vcc is 2V, the logic threshold voltage of the inverter constituting the charge compensation circuit 56A (the input voltage when the output voltage changes rapidly) is designed to be about 0.3V. N-channel MOS transistor 564 in memory cell 50A is not turned off. After the data read operation is completed and N channel MOS transistor 52B is turned off, P channel TFT 566 replenishes charge on node 64, so that node 64 returns to power supply voltage Vcc.

  Thus, even if the voltage of the word line 66 is not boosted, data can be read from the memory cells 50A and 50B without destroying the state of the data stored in the memory cells 50A and 50B. Data can be read out to bit lines 68A and 68B.

  As described above, data is read from and written to the memory cells in the semiconductor memory device 10, and data can be read nondestructively without boosting the voltage of the word line 66.

  Regarding the lower limit of the voltage applied to word line 66, the current drive capability of N channel MOS transistors 52A and 52B, which are access transistors, is the current of N channel MOS transistors 564, 568, which are driver transistors, because of the cell ratio described later. What is necessary is just to determine so that it may become more than half of a driving capability (cell ratio is 2 or less).

  In the memory cells 50A and 50B, the P-channel TFTs 562 and 566 are used because the P-channel TFTs 562 and 566 can be formed in the upper layer of the N-channel MOS transistors 564 and 568, and the cell area is increased by forming the twin memory cell It is for suppressing. As a result, the number of bulk transistors per bit is four, and the cell area is reduced as compared to a standard SRAM composed of six bulk transistors.

  Furthermore, as one of the features of the memory cells 50A and 50B, the cell ratio can be a value close to 1 (ratioless).

  The cell ratio refers to driver transistors in memory cells (N-channel MOS transistors 702 and 704 in SRAM memory cells 700 and 750 shown in FIGS. 10 and 11 and N-channel MOS transistors 564 in memory cells 50A and 50B shown in FIG. 2). , 568), N channel MOS transistors 706, 708 in the SRAM memory cells 700, 750 shown in FIGS. 10 and 11, and N channel MOS transistors 52A, 52B in the memory cells 50A, 50B shown in FIG. In general, in SRAM, the cell ratio is set to 2-3 or more in order to stabilize the operation of the memory cell. This means that in the SRAM, the gate width of the driver transistor needs to be larger than the gate width of the access transistor in order to ensure a certain cell ratio.

  On the other hand, memory cells 50A and 50B are provided with capacitors 54A and 54B connected to nodes 62 and 64, respectively. Therefore, the ability of access transistors 52A and 52B to drive nodes 62 and 64, respectively, is suppressed by capacitors 54A and 54B. That is, even if the driver transistors 564 and 568 and the access transistors 52A and 52B themselves are ratioless, the same effect as that obtained when the cell ratio is provided by the capacitors 54A and 54B is obtained. Therefore, unlike the conventional SRAM, it is not necessary to make the gate width of the driver transistor larger than the gate width of the access transistor in order to ensure the cell ratio, and the cell area can be reduced.

  In consideration of the stability of the operation of the memory cell, the memory cells 50A and 50B do not have to have the same cell ratio as that of the SRAM, but providing a slight cell ratio further enhances the stabilization of the operation. Is desirable.

  So far, the configuration using the TFTs in the charge compensation circuits 56A and 56B has been described. However, a memory cell having the same effect can be realized even if a high resistance is used instead of the TFT.

  FIG. 3 shows a circuit configuration of memory cells 50C and 50D provided with charge compensation circuits 56C and 56D including high resistances 3562 and 3566, respectively, instead of P-channel TFTs 562 and 566 in memory cells 50A and 50B of FIG. FIG. Since the circuit configurations of memory cells 50C and 50D other than high resistances 3582 and 3602 are the same as the circuit configurations of memory cells 50A and 50B, description thereof will not be repeated.

  In the following description, a state where data “0” and “1” are written in the memory cells 50C and 50D will be described. Since the states where data “1” and “0” are written in the memory cells 50C and 50D, respectively, can be considered in the same manner, the description in that case will not be repeated.

  Referring to FIG. 3, in a state where data “0” and “1” are written in memory cells 50C and 50D, respectively, the voltage at node 62 is 0V and the voltage at node 64 is power supply voltage Vcc. . Here, in memory cell 50C, a current always flows from power supply node 72 through high resistance 3562 and N-channel MOS transistor 564. Therefore, unless a resistor having a high resistance value is used as high resistance 3562, data is read / written. The current during the standby period during which the operation is not performed (hereinafter referred to as standby current) increases.

  On the other hand, if the resistance value of high resistance 3566 is too high, the leakage current leaking from N channel MOS transistor 568 at node 64 cannot be ignored, and the potential of node 64 decreases.

Therefore, it is necessary to supply at least about 10 times the leakage current from the high resistance 3566 in order to stabilize the state of the node 64. Assuming that the power supply voltage is 2 V and the leakage current is 1 × 10 ⁻¹⁵ A, the resistance value of the high resistance 3566 is 2 × in order to pass a current 1 × 10 ⁻¹⁴ A 10 times the leakage current through the high resistance 3566. It will suffice if it is 10 ¹⁴ Ω (ohms) or less.

  The above description also applies to the high resistance 3562 in consideration of a state where data “1” and “0” are written in the memory cells 50C and 50D, respectively.

On the other hand, the lower limit of the resistance value of high resistances 3562 and 3566 is determined by the specifications of the memory capacity and standby current of semiconductor memory device 10 in which memory cells 50C and 50D are mounted. For example, when the memory capacity is 4M (mega, “M” represents 10 ⁶ ) bits, in order to suppress the standby current to 10 μA, the current I flowing through the high resistance per memory cell is I = (10 × 10 ⁻⁶ A) / (4 × 10 ⁶ bits) = 2.5 × 10 ⁻¹² A Therefore, since the power supply voltage is 2V, the resistance values of the high resistances 3562 and 3566 are R = 2V / (2.5 × 10 ⁻¹² A) = 8 × 10 ¹¹ Ω. From the above, under the above conditions, the resistance values of the high resistances 3562 and 3566 may be 8 × 10 ¹¹ Ω to 2 × 10 ¹⁴ Ω.

  As described above, according to the semiconductor memory device 10 according to the first embodiment, the twin memory cells including the memory cells 50A and 50B including the charge compensation circuits 56A and 56B are provided, so that the refresh operation is performed as compared with the conventional DRAM. A memory cell that is unnecessary, can read data at high speed, and can read data nondestructively can be realized.

  Also, according to the semiconductor memory device 10 according to the first embodiment, TFTs or high resistances are used for a part of the charge compensation circuits 56A and 56B, and the cell ratio of the driver transistor and the access transistor is made ratioless. As a result, a memory cell having a reduced cell area can be realized.

[Embodiment 2]
Semiconductor memory device 110 according to the second embodiment includes memory cells that do not include N channel MOS transistors 564 and 568 in charge compensation circuits 56A and 56B in memory cells 50A and 50B of semiconductor memory device 10 according to the first embodiment.

  Since the entire configuration of semiconductor memory device 110 according to the second embodiment is the same as the entire configuration of semiconductor memory device 10 according to the first embodiment shown in FIG. 1, description thereof will not be repeated.

  FIG. 4 is a circuit diagram showing a configuration of memory cells arranged in a matrix on the memory cell array 36 in the semiconductor memory device 110.

  Referring to FIG. 4, the memory cell in semiconductor memory device 110 is formed of twin memory cells of memory cells 150A and 150B. The circuit configuration of the memory cells 150A and 150B is such that the N channel MOS transistors 564 and 568 are not provided in the charge compensation circuits 56A and 56B of the memory cells 50A and 50B described in the first embodiment, respectively. Since other circuit configurations of memory cells 150A and 150B are the same as those of memory cells 50A and 50B described in the first embodiment, description thereof will not be repeated.

  The configuration and function of N channel MOS transistors 52A and 52B and capacitors 54A and 54B, which are portions other than P channel TFTs 562 and 566 in memory cells 150A and 150B, and the connection configuration of nodes 62 and 64 are also the same as in the first embodiment. Since they are the same, their description will not be repeated.

  In memory cells 150A and 150B, leak currents from nodes 62 and 64 are compensated by P channel TFTs 562 and 566, and stored data is held without performing a refresh operation.

Hereinafter, the operation of the memory cells 150A and 150B will be described.
(1) Data Write In the following description, the case where data “0” and “1” are written in the memory cells 150A and 150B, respectively, the data “1” and “0” are written in the memory cells 150A and 150B, respectively. The case where "" is written can also be considered in the same way, and the description in that case is omitted.

  The operations or states of bit lines 68A and 68B, word line 66, N channel MOS transistors 52A and 52B, and capacitors 54A and 54B at the time of data writing are the same as in the first embodiment.

  When word line 66 is activated in writing data, N channel MOS transistor 52A is driven in memory cell 150A, and a voltage of 0 V is applied to node 62 from bit line 68A via N channel MOS transistor 52A. As a result, the P-channel TFT 566 of the memory cell 150B is turned ON.

  On the other hand, N-channel MOS transistor 52A is driven in memory cell 150A, and N-channel MOS transistor 52B is also driven in memory cell 150B. The power supply voltage is applied to node 64 from bit line 68B via N-channel MOS transistor 52B. By applying Vcc, the P-channel TFT 562 of the memory cell 150A is turned OFF.

  Therefore, after that, writing of data is completed, and word line 66 is deactivated, and even if N channel MOS transistors 52A and 52B are turned OFF, node 62 is maintained at L level and node 64 is set at H level. Maintained.

  Here, since the memory cell 150A is not provided with an N-channel MOS transistor that strongly pulls down the node 62 to L level, current leakage to the capacitor 54 due to the OFF current of the P-channel TFT 562 can be considered. By making the OFF current of the TFT 562 sufficiently smaller than the leakage current that affects the storage state of the capacitor 54, specifically, the OFF current of the P-channel TFT 562 is smaller than 1/10 of the leakage current from the node 62. By setting as described above, the node 62 is maintained at the L level even without an N-channel MOS transistor that strongly pulls down the node 62 to the L level.

(2) Data Reading Since the data reading operation is the same as that in the first embodiment with respect to the basic operation, the description thereof is omitted, but in the second embodiment, the memory cell in the first embodiment is used. Since N channel MOS transistors 564 and 568 included in 50A and 50B, respectively, are not provided, memory cells 150A and 150B in the second embodiment are nodes formed by N channel MOS transistors 564 and 568 as described in the first embodiment. In the second embodiment, the voltage of the word line 66 cannot be lowered as in the first embodiment. Therefore, in the semiconductor memory device 110, a voltage obtained by boosting the power supply voltage is applied to the word line 66 as in a general DRAM.

  As described above, the storage data is read from and written to the memory cells 150A and 150B.

  In the semiconductor memory device 110 according to the second embodiment, the number of bulk transistors per bit is two, and the cell area can be greatly reduced as compared with a standard SRAM composed of six bulk transistors.

  As described above, according to the semiconductor memory device 110 according to the second embodiment, the twin memory cells including the memory cells 150A and 150B including the P-channel TFTs 562 and 566, respectively, capable of charge compensation, are provided. Thus, a refresh operation is unnecessary, and in particular, a memory cell can be realized in which the cell area is greatly reduced as compared with a conventional SRAM.

[Embodiment 3]
While the memory cells of semiconductor memory devices 10 and 110 according to the first and second embodiments are configured by twin memory cells, the memory cell of semiconductor memory device 210 according to the third embodiment is configured by a single memory cell and data read Sometimes the charge compensation circuit is separated from the capacitor, thereby realizing nondestructive reading of data.

  FIG. 5 is a circuit diagram showing a configuration of memory cells arranged in a matrix on the memory cell array 36 in the semiconductor memory device 210.

  Referring to FIG. 5, memory cell 250 includes an N channel MOS transistor 52, a capacitor 54, a charge compensation circuit 256, and an N channel MOS transistor 76. Charge compensation circuit 256 includes inverters 58 and 60 and nodes 262 and 264. Inverter 58 includes P-channel TFT 582 and N-channel MOS transistor 584, and inverter 60 includes P-channel TFT 602 and N-channel MOS transistor 604. Become.

  N channel MOS transistor 52 is connected to bit line 68 and capacitor 54, and has its gate connected to word line 66. N channel MOS transistor 52 is an access transistor that is driven by data line 66 activated at the time of data writing and data reading, and electrically connects memory cell 250 to bit line 68 at the time of data writing and data reading. Its function and operation are the same as those of the N-channel MOS transistor 52A described in the first and second embodiments.

  Capacitor 54 has one end connected to N channel MOS transistor 52 and the other end connected to cell plate 70. The function of the capacitor 54 is also the same as that of the capacitor 54A described in the first and second embodiments.

  N channel MOS transistor 76 is connected to node 78 and node 262 connecting capacitor 54 to N channel MOS transistor 52, and has its gate connected to internal signal line 80. N-channel MOS transistor 76 is driven by internal signal / R output to internal signal line 80 from a control circuit (not shown), and isolates charge compensation circuit 256 from node 78 when internal signal / R is at L level.

FIG. 6 is a timing chart showing a state change of the internal signal / R.
Referring to FIG. 6, internal signal / R is at H level during a standby period (before timing T1) in which both chip select signal / CS and write enable signal / WE are at H level. Internal signal / R is at L level during a data read operation (timing T1 to T2) in which chip select signal / CS and write enable signal / WE are at L level and H level, respectively. Further, internal signal / R is at H level during a data write operation (timing T2 to T3) in which both chip select signal / CS and write enable signal / WE are at L level.

  Therefore, referring again to FIG. 5, N channel MOS transistor 76 is inactivated only during the data read operation, and isolates charge compensation circuit 256 from node 78 during the data read operation.

  P-channel TFT 582 is connected to power supply node 72 and node 264, and has its gate connected to node 262. N channel MOS transistor 584 is connected to node 264 and ground node 74, and has its gate connected to node 262.

  P-channel TFT 602 is connected to power supply node 72 and node 262, and has its gate connected to node 264. N channel MOS transistor 604 is connected to node 262 and ground node 74, and has its gate connected to node 264.

  In memory cell 250, the leakage function of capacitor 54 is compensated by the latch function constituted by inverter 58 and inverter 60, and the stored data is held without performing a refresh operation.

Hereinafter, the operation of the memory cell 250 will be described.
(1) Writing of Data “0” At the time of data writing, N channel MOS transistor 76 is turned on in response to internal signal / R, and charge compensation circuit 256 is electrically connected to node 78.

In this memory cell 250, the ON current of the bulk transistor is about 3 × 10 ⁻⁵ A (ampere), and the ON current and OFF current of the TFT are about 1 × 10 ⁻¹¹ A and 1 × 10 ⁻¹³ A, respectively. It is. The leakage current from the nodes 262 and 264 due to the OFF current of the capacitor 54 and the bulk transistor is about 1 × 10 ⁻¹⁵ A. The current values shown here are not limited to these numerical values, but indicate orders of these degrees.

  With each current value described above, the ON current of the TFT exceeds the leakage current from the nodes 262 and 264 by 4 digits, so that the power supply node 72 can charge the nodes 262 and 264 to the power supply voltage.

The capacitance of the node 262 depends on the capacitance of the capacitor 54, the gate capacitance of the transistor, the junction capacitance of the active region, etc. In order to stably read the stored data, the capacitance of the node 262 is at least 5fF (5f (Femto) Farad, “f” represents 10 ⁻¹⁵ ). On the other hand, the capacitance of the node 264 is due to the gate capacitance of the transistor, the junction capacitance of the active region, and the like, but the capacitance of the node 264 is about 1 fF as in a general SRAM. If the capacity of the node 262 is the minimum value of 5 fF described above and the capacity of the node 264 is 1 fF, the capacity ratio of the nodes 262 and 264 is 5.

  The degree to which the capacity ratio is preferably determined depends on the condition that data “0” can be written in the memory cell 250. Hereinafter, this condition will be described.

When data “0” is written in the memory cell 250, the voltage of the node 262 becomes 0 V, but in the normal write operation time n (nano, “n” represents 10 ⁻⁹ ) second order. Node 264 is not charged to the power supply voltage from power supply node 72. This is shown in the following equation.

  Now, when the power supply voltage of the power supply node 72 is 2V, the following equation is established at the node 264.

Charge Q = capacitance C × voltage V = 1f × 2 = 2 × 10 ⁻¹⁵
P-channel TFT 582 ON current I = 1 × 10 ⁻¹¹ amperes charge time t = Q / I = 2 × 10 ⁻⁴ seconds (ii)
Therefore, in order for node 264 to be charged, it takes μ (micro, “μ” represents 10 ⁻⁶ ) seconds. Then, even when the voltage of node 262 becomes 0V, node 264 is not immediately charged to the power supply voltage, and therefore node 262 starts to be charged from power supply node 72 via P-channel TFT 602. If the charging speed of the node 262 is higher than that of the node 264, the node 262 is charged and the node 262 is recharged before the P-channel TFT 602 is turned off. Data “0” eventually becomes data “1”, and a write error occurs.

  However, if the capacity ratio of the nodes 262 and 264 is large, the charging speed of the node 264 exceeds the charging speed of the node 262, the P-channel TFT 602 is turned off before the node 262 is recharged, and the N-channel MOS Since the transistor 604 is turned on, the node 262 is pulled down to 0 V by the N-channel MOS transistor 604, and no write error occurs.

  It is considered that the capacity ratio of the nodes 62 and 64 should be at least about 5 in consideration of variations in threshold voltage between the N channel MOS transistor 584 and the N channel MOS transistor 604. In order to more stably realize data writing, a capacitor 54 connected to the node 262 is provided. If the capacitance of the capacitor 54 is set to about 20 fF, which is equivalent to that of a general DRAM, the nodes 262 and 264 The capacity ratio is about 20, and data writing is further stabilized. Considering that the ratio of the ON current between the P-channel TFT 582 and the P-channel TFT 602 varies about 10 times and the threshold voltage between the N-channel MOS transistor 584 and the N-channel MOS transistor 604 varies, the nodes 62, The capacity ratio of 64 is desirably 20 or more.

  As described above, by providing the capacitance ratios at the nodes 262 and 264, even if the word line 66 is deactivated before the node 264 is charged to the power supply voltage, a write error occurs in writing data “0”. do not do. When the voltage at node 264 exceeds a predetermined voltage, N-channel MOS transistor 604 is turned on. As a result, node 262 is held at 0 V, and the state of written data “0” is not refreshed thereafter. Retained.

  In the third embodiment, the capacitor 54 is provided in order to stably write data. However, without providing the capacitor 54, the capacity ratio of the nodes 262 and 264 is sufficiently high due to the gate capacitance of the transistor. If secured, the capacitor 54 can be dispensed with.

(2) Writing of data “1” When data “1” is written to the memory cell 250, the node 262 is immediately charged from the bit line 68 via the N-channel MOS transistor 52, and accordingly, N-channel The MOS transistor 584 is immediately turned on, and the node 264 immediately becomes 0V. Therefore, the voltages of the nodes 262 and 264 are stabilized at an early stage, and are not affected by the performance of the TFT when data “1” is written.

  As described above, since the ON current of the P-channel TFT 602 exceeds the leakage current from the node 262 by four digits, the node 262 is held at the power supply voltage by the P-channel TFT 602 and then written without performing a refresh operation. The state of the data “1” is retained.

  7 and 8 are diagrams showing potential changes of the nodes 62 and 64 in the above-described write operation. FIG. 7 is a diagram showing potential changes at nodes 262 and 264 when data “0” is written to memory cell 250, and FIG. 8 shows nodes when data “1” is written to memory cell 250. It is a figure which shows the electric potential change of 262,264.

  First, a change in potential of nodes 262 and 264 when data “0” is written in memory cell 250 will be described.

  Referring to FIG. 7, a broken line indicates a potential change at node 262 and a solid line indicates a potential change at node 264. The power supply voltage is 2 V, and the logic threshold voltage of the inverter 60 (input voltage when the output voltage changes rapidly) is 0.3 V. It is assumed that the word line 66 is activated at time T1.

  When word line 66 is activated at time T1, the charge at node 262 is drawn to bit line 68 via N-channel MOS transistor 52, and the potential at node 262 immediately becomes 0V. Accordingly, the node 264 starts to be charged from the power supply node 72 via the P-channel TFT 582, but the ON current of the TFT is smaller than the ON current of the bulk transistor, and the node 264 is not immediately charged. Charging starts from the power supply node 72 via the P-channel TFT 602. However, due to the capacity ratio of the nodes 262 and 264, the charging speed of the node 262 is slower than the charging speed of the node 264. Then, the word line 66 is deactivated several tens of microseconds after the time T1.

  When the potential of node 264 exceeds logic threshold voltage 0.3V of inverter 60 at time T2 of about 30 μsec from time T1, N-channel MOS transistor 604 is turned on, and accordingly node 262 is set to 0V. The state of the inserted data “0” is stabilized. The time required for the potential of the node 264 to exceed the logic threshold voltage of 0.3 V of the inverter 60 is confirmed based on the following equation.

Charge Q of node 264 = capacitance C × voltage V = 1f × 0.3 = 3 × 10 ⁻¹⁶
P channel TFT 582 ON current I = 1 × 10 ^-11 A
Time to reach the logical threshold voltage 0.3V t = Q / I = 3 × 10 ⁻⁵ seconds (iii)
On the other hand, the node 264 continues to be charged by the P-channel TFT 582, and as shown by the above-described formula (ii), the power supply voltage is set to 2V at time T3 about 200 μs after the time when charging of the node 264 is started. Charged.

  Next, a change in potential of nodes 262 and 264 when data “1” is written in memory cell 250 will be described.

  Referring to FIG. 8, broken lines and solid lines indicate potential changes at nodes 262 and 264, respectively, and it is assumed that word line 66 is activated at time T1. When word line 66 is activated at time T1, node 262 is immediately charged to 2 V of the power supply voltage from bit line 68 via N-channel MOS transistor 52. As a result, N channel MOS transistor 584 is immediately turned ON, and node 264 immediately becomes 0V. Therefore, when data “1” is written, it is not affected by TFT characteristics.

(3) Data Reading As described above, since internal signal / R is at L level during data reading, N channel MOS transistor 76 is turned off and charge compensation circuit 256 is isolated from node 78. Then, the charge compensation circuit 256 maintains the internal state when separated.

  N channel MOS transistor 52 and capacitor 54 when charge compensation circuit 256 is isolated from node 78 have the same configuration as that of the conventional DRAM, and the data read operation can be performed in the same manner as the conventional DRAM. That is, the bit line 68 is precharged to the voltage Vcc / 2 in advance, and when reading data, the boosted power supply voltage is applied to the word line 66 and the word line 66 is activated. As a result, N channel MOS transistor 52 is turned on, and a minute voltage change of bit line 68 corresponding to the storage state of capacitor 54 is detected by a sense amplifier (not shown), and the voltage of bit line 68 is amplified to power supply voltage Vcc or ground voltage GND. Is done. The voltage level of bit line 68 corresponds to the state of stored data.

  Here, after data reading, the voltage at node 78 is close to precharge voltage Vcc / 2, and the voltage state at node 78 before data reading is not maintained. In the conventional DRAM, such a state means destruction of stored data. In a state where the voltage of the bit line 68 is amplified to the voltage Vcc or the ground voltage GND after data reading, the word line 66 is activated again. The capacitor 54 is recharged, and data is rewritten by the same operation as the above (1) or (2).

  In memory cell 250, on the other hand, after data reading is completed, internal signal / R becomes H level, and charge compensation circuit 256 is connected to node 78 again. As a result, since the charge compensation circuit 256 maintains the state before data reading, when the stored data is “1”, the node 78 becomes the power supply voltage from the power supply node 72 via the P-channel TFT 602. Charged.

  Immediately after the N-channel MOS transistor 76 is connected, the voltage at the node 262 once decreases to near 1/2 Vcc, but is higher than the logic threshold voltage 0.3 V of the inverter 58, so that the inverter 58 is inverted. No, the internal state of the charge compensation circuit 256 does not change. When the stored data is “0”, the charge of node 78 and capacitor 54 is immediately extracted by N channel MOS transistor 604, and node 78 becomes 0V without inverter 58 being inverted.

  Thus, in memory cell 250, during data reading, charge compensation circuit 256 is isolated from node 78 while maintaining the state before data reading, and the operation of N channel MOS transistor 52 and the operation of capacitor 54 in the data reading operation are separated. Although the state is exactly the same as that of the conventional DRAM, after completion of the data read operation, charge compensation circuit 256 is connected again to node 78, and the state of capacitor 54 and node 78 is charged or discharged by charge compensation circuit 256. Thus, since the state before data reading is restored, it is not necessary to rewrite the stored data from the outside of the memory cell by the rewriting operation as in the conventional DRAM, and nondestructive reading of data is realized.

  In this memory cell 250, the P-channel TFTs 582 and 602 are used because the P-channel TFTs 582 and 602 can be formed in the upper layer of the N-channel MOS transistors 584 and 604 as in the first embodiment. Compared to the above, the N-channel MOS transistors 584, 604 and 76, which are bulk transistors, have an increased cell area, but the number of bulk transistors in the memory cell is four, and a standard SRAM composed of six bulk transistors. This is because the cell area can be reduced as compared with FIG.

  Further, as one of the features of the memory cell 250, the cell ratio can be a value close to 1 (ratioless).

  As described above, in the memory cell 250, since the operation of the memory cell is stabilized by providing the capacitor 54, it is not necessary to set the cell ratio to 2 or more as in the case of SRAM. Can be ratioless. The fact that the cell ratio can be reduced means that the gate width of the driver transistor can be reduced as compared with the conventional SRAM, and further reduction of the cell area is realized from this point.

  In consideration of the stability of the operation of the memory cell, the memory cell 250 does not need to have the same cell ratio as that of the SRAM, but it is desirable to provide a certain cell ratio in order to further improve the stabilization of the operation. .

  As described above, according to semiconductor memory device 210 in accordance with the third embodiment, memory cell 250 is separated from capacitor 54 while maintaining the state before data reading at the time of data reading, and capacitor 54 again after the completion of data reading. Is provided, and the charge compensation circuit 256 for restoring the charge state of the capacitor 54 to the state before data reading is provided, so that nondestructive reading of data is possible and the refresh operation is not required.

  In the first embodiment, the memory cells 50A and 50B are arranged adjacent to each other. However, the memory cells 50A and 50B are arranged without being adjacent to each other due to the arrangement of sense amplifiers connected to the bit lines. You may do it.

  In this case, since the wiring capacity of the nodes 62 and 64 increases as the wiring length increases, if the capacity of the nodes 62 and 64 is about 5 fF or more by the wiring capacity, the capacitors 54A and 54B need not be specially provided. Also good. This simplifies the structure of the memory cell.

  On the other hand, when the memory cells 50A and 50B are arranged adjacent to each other, the bit lines 68A and 68B can be arranged close to each other in parallel, and even if external noise is applied to one of the bit lines, the bit lines 68A and 68B. Therefore, the noise is canceled out in the differential sense amplifier, and the resistance to noise is improved.

  Further, although the precharge voltage of the bit line at the time of data reading is ½ Vcc, the precharge voltage may be the power supply voltage Vcc. In this case, when the stored data is “1” and the voltage of the storage node is the power supply voltage Vcc, the potential of the storage node is not lowered by the data reading operation, so that more stable nondestructive reading can be realized.

  The description regarding the arrangement of the memory cells and the precharge voltage is the same as in the second embodiment.

  Furthermore, in the first to third embodiments, the bulk transistors are all formed of N-channel MOS transistors, but may be formed of all P-channel MOS transistors. In this case, N-channel TFTs are used instead of P-channel TFTs 562 and 566 in the first and second embodiments, and N-channel TFTs are used instead of P-channel TFTs 582 and 602 in the third embodiment. In the second embodiment, N-channel TFTs used in place of P-channel TFTs 562 and 566 are not connected to power supply node 72 but are connected to ground node 74.

  Further, semiconductor memory device 10 shown in FIG. 1 includes a terminal corresponding to each of row address strobe signal / RAS and column address strobe signal / CAS in control terminal 12, and corresponds to each of these signals. It is also possible to provide a row and column address at the same time without providing a terminal.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

1 is a schematic block diagram showing an overall configuration of a semiconductor memory device according to the present invention. 3 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in the semiconductor memory device according to the first embodiment; FIG. FIG. 6 is a circuit diagram showing another configuration of the memory cells arranged in a matrix on the memory cell array in the semiconductor memory device according to the first embodiment. FIG. 6 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in the semiconductor memory device according to the second embodiment. FIG. 10 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a semiconductor memory device according to a third embodiment. 6 is a timing chart showing a change in state of an internal signal / R on the internal signal line shown in FIG. FIG. 6 shows potential changes at nodes 262 and 264 when data “0” is written in the memory cell shown in FIG. 5. FIG. 6 shows potential changes at nodes 262 and 264 when data “1” is written in the memory cell shown in FIG. 5. 2 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a DRAM. FIG. 3 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a 6-transistor SRAM. FIG. 3 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a 4-transistor SRAM. FIG.

Explanation of symbols

  10, 110, 210 Semiconductor memory device, 12 control signal terminal, 14 clock terminal, 16 address terminal, 18 data input / output terminal, 20 control signal buffer, 22 clock buffer, 24 address buffer, 26 input / output buffer, 28 control circuit, 30 row address decoder, 32 column address decoder, 34 sense amplifier / input / output control circuit, 36 memory cell array, 50A-50D, 150A, 150B, 250, 500, 700, 750 memory cell, 52, 52A, 52B, 76, 502 , 564, 568, 702 to 708 N channel MOS transistor, 54, 54A, 54B, 504 capacitor, 56A to 56D, 256 charge compensation circuit, 58, 60 inverter, 62, 64, 78, 262, 264, 714, 716 66, 506, 722 Word line, 68, 68A, 68B, 508, 718, 720 Bit line, 70, 510 Cell plate, 72 Power node, 74 Ground node, 80 Internal signal line, 562, 566, 730, 732 P-channel TFT, 710, 712 P-channel MOS transistor, 3562, 3566 High resistance.

Claims (3)

A memory cell array including a plurality of memory cells arranged in a matrix;
A plurality of word lines and a plurality of first and second bit lines respectively arranged for each row and column of the memory cells;
Each of the plurality of memory cells includes
A first inverter comprising a first P-channel thin film transistor and a first N-channel MOS transistor connected between a first power supply node and a second power supply node having a lower potential than the first power supply node; ,
A second inverter comprising a second P-channel thin film transistor and a second N-channel MOS transistor connected between the first power supply node and the second power supply node;
An output node of the first inverter and an input node of the second inverter are connected to a first storage node;
An input node of the first inverter and an output node of the second inverter are connected to a second storage node, the word line is connected to a control electrode, the first bit line and the first node A third N-channel MOS transistor connected between the storage nodes;
A first capacitive element connected between a cell plate and the first storage node and holding a charge according to a logic level of the first storage node;
A fourth N-channel MOS transistor connected to the control electrode and connected between the second bit line and the second storage node;
A second capacitive element connected between the cell plate and the second storage node and holding a charge corresponding to a logic level of the second storage node;
The current drive capability of the first N-channel MOS transistor is 1 to 2 times the current drive capability of the third N-channel MOS transistor,
The semiconductor memory device, wherein the current drive capability of the second N-channel MOS transistor is 1 to 2 times the current drive capability of the fourth N-channel MOS transistor. A memory cell array including a plurality of memory cells arranged in a matrix;
A plurality of word lines and a plurality of first and second bit lines respectively arranged for each row and column of the memory cells;
Each of the plurality of memory cells includes
A first inverter comprising a first P-channel thin film transistor and a first N-channel MOS transistor connected between a first power supply node and a second power supply node having a lower potential than the first power supply node; ,
A second inverter comprising a second P-channel thin film transistor and a second N-channel MOS transistor connected between the first power supply node and the second power supply node;
An output node of the first inverter and an input node of the second inverter are connected to a first storage node;
An input node of the first inverter and an output node of the second inverter are connected to a second storage node, the word line is connected to a control electrode, the first bit line and the first node A third N-channel MOS transistor connected between the storage nodes;
A first capacitive element connected between a cell plate and the first storage node;
A fourth N-channel MOS transistor connected to the control electrode and connected between the second bit line and the second storage node;
A second capacitive element connected between the cell plate and the second storage node;
The current driving capability of the first N-channel MOS transistor is one times the current driving capability of the third N-channel MOS transistor,
The semiconductor memory device, wherein the current driving capability of the second N-channel MOS transistor is one times the current driving capability of the fourth N-channel MOS transistor. A memory cell array including a plurality of memory cells arranged in a matrix;
A plurality of word lines and a plurality of first and second bit lines respectively arranged for each row and column of the memory cells;
Each of the plurality of memory cells includes
A first inverter comprising a first P-channel thin film transistor and a first N-channel MOS transistor connected between a first power supply node and a second power supply node having a lower potential than the first power supply node; ,
A second inverter comprising a second P-channel thin film transistor and a second N-channel MOS transistor connected between the first power supply node and the second power supply node;
An output node of the first inverter and an input node of the second inverter are connected to a first storage node;
An input node of the first inverter and an output node of the second inverter are connected to a second storage node, the word line is connected to a control electrode, the first bit line and the first node A third N-channel MOS transistor connected between the storage nodes;
A first capacitive element connected between a cell plate and the first storage node;
A fourth N-channel MOS transistor connected to the control electrode and connected between the second bit line and the second storage node;
A second capacitive element connected between the cell plate and the second storage node;
The gate width of the first N-channel MOS transistor is the same as the gate width of the third N-channel MOS transistor,
The semiconductor memory device, wherein a gate width of the second N-channel MOS transistor is the same as a gate width of the fourth N-channel MOS transistor.

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