JPS62257698A - Semiconductor static memory cell - Google Patents

Abstract

PURPOSE:To prevent suitably the destruction of read due to stored electric charge by connecting respectively a capacitance between a constant potential and each drain of the 1st and 2nd FETs to utilize the discharge state of the capacitance thereby improving the read speed. CONSTITUTION:When a signal of H level is stored in a node N11 and a signal of L level is stored in a node N12, a capacitor 17 is discharged and a capacitor 18 is charged. In bringing the word line W to the H level, since the impedance of the capacitor 17 in the discharge state is low, the signal of the node N12 is read quickly. Since bit lines B, the inverse of B have a large wiring capacitance in general, when the FETs 13, 14 are conducted, the content of the nodes N11, N12 is changed by the momentary level of the bit lines B, the inverse of B, hat is, read destruction takes place, but the electric charge in the capacitors 17, 18 hardly cause read destruction.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor static memory cell.

(Prior art) Conventionally, as a technology in this field, there is IEEE TRANSACTIONS ON ELECTRON DEVICES (IEEE TRANSACTIONS ONEL).
Etll:TR0N DEVICE), ED-
32 [91 (1985-9) P, 1797-1801. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional semiconductor static memory cell.

This memory cell has a pair of bit lines B and f for inputting and outputting data and a word line W for transmitting address signals. ) 1, 2, 3, 4, and the resistance 5.6 is vck;c.

Here, the gates and drains of FETs 1 and 2 are cross-connected to form a flip-flop circuit.

Also, the drain of FETI is a node (connection point)
It is connected to the power supply voltage VDD via N1 and the resistor 5, and its source is connected to the ground potential VSS.

The FET 2 has its drain connected to the power supply voltage VDD via the node N2 and the resistor 6, and its source connected to the ground potential vss.

Next, the operation will be explained.

(i) Storage operation When word Bw is at L level, FETs 3 and 4 have high resistance, and the circuit composed of FETI, 2 and resistor 5.8 is separated from bit lines B, f. At this time, if node Nl is at H level and node N2 is at L level, node N1
FET2 becomes conductive due to the H level of node N
2, and also lowers the L level of node N2.
The level is set by setting FET 1 to a high resistance state and setting node Ml to H.
Try to level. Therefore, it acts to maintain the current state of the H level of the node M1 and the L level of the node N2, and operates as a memory circuit. Conversely, when the node N1 is at the L level and the node N2 is at the H level, the current state is similarly maintained.

(ii) Read operation When an H level signal is applied to the word line W, FET3,
4 becomes conductive, the number 0 of the node N1 appears on one bit line, and the signal of the node N2 appears on the other signal line ■, so that the contents held in this memory can be read out.

(iji) Write operation With an H level signal applied to the word line W, by externally applying an L level signal to one bit line B and an H level signal to the other bit line ■, the node An L level signal can be written to N1 and an H level signal can be written to note N2.

(Problems to be Solved by the Invention) However, the memory cell having the above configuration has the following problems.

In order to increase the operating speed of memory cells, FETI,
2. It is necessary to use an FET with a large gate width. In this case, there was a problem that the impedance of FET I, 2 when conductive was too small compared to the impedance of FET 3.4 when conductive, making writing impossible.

Conversely, if the gate widths of FETs 1 and 2 are made smaller to facilitate writing, the bit line B is used during reading.

(2) There is a problem in that the above-mentioned noise changes the memory contents, which makes it easy to cause so-called readout corruption.

The present invention provides a semiconductor static memory cell that solves the problems of the prior art, which are limited in operating speed and retention characteristics.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides first and second F.
In a semiconductor static memory cell having a clip-prop circuit in which the gate and drain of an ET are cross-connected, a capacitor is connected between each drain of the first and second FET and a constant potential.

(Function) According to the present invention, since the semiconductor static memory cell is configured as described above, the capacitors connected between the drains of the first and second FETs and a constant potential are controlled depending on their discharge states. In addition to improving the readout speed, the implanted charge acts to prevent readout damage, thus eliminating the above-mentioned problems.

(Embodiment) FIG. 1 is a circuit diagram of a semiconductor static memory cell showing an embodiment of the present invention.

This memory cell has a word line W and a pair of pins) mB,
L with 11r, Solerani FET11, 12, 13, 14
, resistors 15, 18, and capacitors i 17.18 are connected.

The FET (first FET) 11 has its drain connected to the power supply voltage VDD via the node 11 and the resistor 15, its source connected to the ground potential vSS, and its gate connected to the node N1.
2 are connected to each other. FET (second FET
) 12 has its drain connected to the 7-domain N12 and the resistor 1
B to the power supply voltage VDD through B, the source of which is connected to the ground potential V
SS and its gate are connected to node 11, respectively. These FET II and 12 constitute a flip-flop circuit.

The node old l is connected to the ground potential vSS via the capacitor 18, and is also connected to the source of the FET 13.

The node N12 is connected to the ground potential VSS via the capacitor 17, and is also connected to the source of the FET 14. The FET 13 has its drain connected to the bit line B, and its gate connected to the word line W. FE
T14 has its drain connected to the bit line (2) and its gate connected to the word line W.

The feature of this embodiment is that a capacitance of 17.18% is added to the conventional circuit.

Next, the operation will be explained.

The operation in which the signals on bit line B and ■ are stored in nodes Nil and N12 in this memory cell is the same as in the conventional circuit.
Assume that an L-level signal is stored in 12. At this time, one capacitor 17 is in a discharged state, and the other capacitor 18 is in a charged state.

Next, when the word line W is brought to the H level, the impedance of the capacitor 17 in the discharge state yE is low, compared to the conventional circuit which tried to bring the hit if to the L level only by the conductive impedance in the FET 12. The signal on node N12 can be read out faster.

In addition, since the bit lines B and ■ generally have a large wiring capacitance, the word line W is set to H level and the FETI3, 1
When node Nil, 812 is made conductive, the contents of node Nil, 812 change depending on the level of bit mB, H at that moment. So-called read corruption occurs, but the problem is zt7. Due to the presence of ta, read destruction is less likely to occur due to the charges stored in the capacitors 17 and 18.

In the case of a write operation to rewrite the contents of the memory cell, the capacitors 17 and 18 become high impedance as they are charged, so that writing is not disabled, unlike when the gate width of FETI, 2 is increased in the conventional circuit.

Regarding the write time, if we look only at the operation of this memory cell, the memory cell of this embodiment takes longer than the conventional circuit because it requires time to charge the capacitance of 17.18. However, the writing time to a memory cell is generally not a problem because the time required for peripheral circuitry is larger than the operating speed of the memory cell.

In this way, since the capacitors 17.18 are provided in this embodiment, not only the operating speed can be increased, but also the retention characteristics can be improved.

In the above embodiment, the capacitor 17.18 was connected between the drain of the FET 12°11 and the ground potential vSS.
Even if these capacitors 17 and 18 are connected between the drains of FETs 12 and 11 and the power supply voltage VDD, or they are connected to both the ground potential vSS and the power supply voltage voD, almost the same result as in the above embodiment can be obtained. Effects and effects can be obtained. In addition, FETs 13 and 14 and resistor 15 in FIG.
．． It is also possible to replace 16 etc. with other circuit elements or to modify their circuit arrangement.

(Effects of the Invention) As described in detail above, according to the present invention, since a capacitor is added, the readout speed can be improved by utilizing the discharge state of the capacitor, and the readout speed can be improved by using the charge stored in the capacitor. Destruction can be accurately prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor static memory cell showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor static memory cell. 11...first FET, 12...second FET
, 13.14...FET, 15.18...
Resistance, 17.18... Capacity, B, ■... Pit line, W... Word line.

Claims (1)

[Scope of Claims] In a semiconductor static memory cell having a flip-flop circuit in which the gates and drains of first and second field effect transistors are cross-connected, A semiconductor static memory cell characterized in that a capacitor is connected between each potential.