JPH06187781A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent loss of reading signal quantity by suppressing difference of voltage amplitude between a word line and a dummy word line at the time of reading out data. CONSTITUTION:When '0' is read out from a memory cell 101, a word line WL is shifted from a GND level to a (VCC+VT+alpha) level, a NMOS 12 in the memory cell 101 connected to the word line is turned on, stored '0' is outputted to a bit line BLb. At this time, a dummy word line DWL0 is shifted from a VCC level to the GND level, while a dummy word line DWL2 is shifted from the VCC level to (VCC+VT+alpha) level, offset voltage generated respectively in the bit line BLb and a bit line BLa is offset, and signal quantity transmitted from the memory cell 101 to the bit line BLb is not varied. Therefore, potential difference between the bit line BLa and the BLb is made sufficiently large until a sense amplifier 40 is operated, then correct information can be read out to data lines Da, Db.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as a dynamic random access memory (hereinafter referred to as DRAM), for example, a dummy word line driving system for DRAM.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there is one described in JP-A-60-242591, and the configuration thereof will be described below with reference to the drawings. Figure 2
FIG. 3 is a schematic circuit diagram showing a configuration example of a memory cell section in a DRAM described in the above-mentioned document or the like. In this memory cell section, complementary first and second bit lines BL _a ,
BL _b , a plurality of word lines WL ₀ and WL ₁ crossing the bit lines BL _a and BL _b , and the bit line B.
It has a plurality of dummy word lines DWL ₀ and DWL ₁ crossed with L _a and BL _b . Bit line B
A dynamic memory cell 10 ₁ is connected to the intersection of L _b and word line WL ₀ , and bit line BL
_The dynamic memory cell 10 ₂ is also connected to the intersection of _a and the word line WL ₁ . Each memory cell 1
Reference numerals 0 ₁ and 10 ₂ denote a charge storage capacitor 11 and a charge transfer N-channel MOS transistor (hereinafter referred to as NMOS).
12), which are connected in series between ½ · VCC (where VCC is the power supply potential) and the bit lines BL _b , BL _a .

Bit line BL _b and dummy word line DWL ₀
And the intersection of the dummy cell 20 ₁ is connected, further in intersection of the bit line BL _a dummy word line DWL _1, dummy cell 20 ₂ is connected. Each of the dummy cells 20 ₁ and 20 ₂ is composed of NMOS. At one end of the bit lines BL _a , BL _b , the bit lines BL _a ,
BL _b is equalized to 1/2 · VCC, for example.
The equalizing circuit 30 is connected. The equalizer circuit 30 includes an NMOS 31 connected between the bit line BL _a and ½ · VCC, and a bit line BL _b and ½ · VC.
It is composed of an NMOS 32 connected between C and an NMOS 33 connected between the bit lines BL _a and BL _b , which are turned on / off by an equalize signal EQ.

[0004] Bit line BL _a, the other end of the BL _b is the bit line BL _a, detects a potential difference on the BL _b, together with the sense amplifier 40 is connected to amplify the column line Y-DEC
Data transfer NMOS 5 that turns on and off depending on
Complementary data lines D _a and D _b are connected via 1, 52. The sense amplifier 40 includes bit lines BL _a and BL
PM and NMOS 41 and 42 connected between _b
OS 43, 44 and their NMOSs 41, 42
Is turned on and off by the activation signal φ _a , and its PMOS4
3, 44 are activation signals φ having _a phase opposite to that of the activation signals φ a
_It is turned on and off by _b .

FIG. 3 is a timing chart of the "0" information read operation of FIG. 2, and the operation of FIG. 2 will be described with reference to this figure. For example, an operation for reading "0" information stored in the memory cell 10 ₁ will be described. When the equalize signal EQ is at the VCC level, the NMOS lines 31, 32 and 33 in the equalize circuit 30 are in the ON state, so that the bit lines BL _a and BL _b are equalized to 1/2 · VCC. The sense amplifier activation signals φ _a and φ _b are also 1/2
-It is equalized to VCC. Equalize signal EQ
Is lowered from the VCC level to the ground GND level, the NMOSs 31, 32, 33 in the equalizing circuit 30 are
Is turned off, then the word line WL ₀ selected by a decoder (not shown) rises, the NMOS 12 in the memory cell 10 ₁ is turned on, and the “0” information stored in the capacitor 11 is output to the bit line BL _b . It At this time, the word line WL ₀ is changed from the GND level to (VCC + V _T + α)
Rises to the level (V _T ; NMOS threshold voltage), and the dummy word line DWL ₀ goes from the VCC level to GND.
Fall to the level. The dummy word line DWL ₁ remains at the VCC level.

Next, the sense amplifier activation signal φ _a becomes 1 /
While gradually increasing from the 2 · VCC level to the VCC level, the sense amplifier activation signal φ _b drops from the 1/2 · VCC level to the GND level. Then, the sense amplifier 40 operates and the bit line BL _a is amplified to the VCC level and the bit line BL _b is amplified to the GND level. After that, the column line Y-DEC rises from the GND level to the VCC level, the data transfer NMOSs 51 and 52 are turned on, and the information of the bit lines BL _a and BL _b is changed to the data line D _a ,
Transmitted to D _b . In such a half precharge type memory cell portion, the dummy cell 2 which is originally unnecessary
By providing 0 ₁ , 20 ₂ , the word lines WL ₀ , W
It is possible to avoid the imbalance of the potential of the bit line pair generated by the coupling voltage to the bit lines BL _a and BL _b due to L _{1, and} increase the operation margin to prevent malfunction.

[0007]

However, the apparatus having the above structure has the following problems. Memory cell 1
When the information of 0 ₁ is read, the word line WL ₀ makes a transition from the GND level to the (VCC + V _T + α) level, and when the dummy word line DWL ₀ makes a transition from the VCC level to the GND level, there is a voltage amplitude difference ΔV = V _T + α. Therefore, the word line W
An offset voltage ΔVs is generated between the bit lines BL _a and BL _b due to capacitive coupling of the gate capacitance between L ₀ and the bit line BL _b and between the dummy word line DWL ₀ and the bit line BL _b . Therefore, there is a problem that the read signal amount is lost and the sense amplifier 40 malfunctions.

In a DRAM using a voltage level lower than VCC = 3.3V used in a 16Mbit DRAM, for example, when VCC = 1.5V, the activation levels of the word lines WL ₀ and WL ₁ are increased. Occupy (V _T + α)
Will be higher. Therefore, there is a problem that the loss of the amount of read signals is further increased and the conventional dummy word line driving method cannot be used, and it is difficult to solve them. The present invention has the problem that the selected word line WL ₀ changes from the GND level to the (VCC + V _T + α) level and the dummy word line DWL ₀ changes from the VCC level to the GND level. The present invention provides a semiconductor integrated circuit device such as a DRAM, which solves the problem that the voltage amplitude difference ΔV = V _T + α is generated and the read signal amount is lost.

[0009]

In order to solve the above-mentioned problems, a first aspect of the present invention is to arrange complementary first and second bit lines and intersect with the first and second bit lines. Connected to the intersection of the first word line and the first or second bit line, and the first dummy word line crossing the first and second bit lines. Memory cell, the first or second bit line and the first
A first dummy cell connected to an intersection of the dummy word line and the second dummy word line, and a second dummy word line cross-arranged with respect to the first and second bit lines. , A second dummy cell connected to the intersection of the second or first bit line and the second dummy word line. Then, when data is read from the memory cell, the word line is set to an activation level, and the first dummy word line is set to a first level from a precharge level.
To the power supply potential level (for example, GND level) of the second dummy word line from the precharge level to the activation level of the word line. In the second invention, the second dummy word line and the second dummy cell are provided as in the first invention. Then, at the time of reading data from the memory cell, the word line is set to a level approximately twice the second power supply potential level (for example, the VCC level), and the first dummy word line is set to the second power supply potential level from the second power supply potential level. The second dummy word line is configured to transition from the first power supply potential level to the second power supply potential level, respectively, to the first power supply potential level.

[0010]

According to the first aspect of the invention, since the semiconductor integrated circuit device is configured as described above, there is a voltage amplitude difference between the word line and the first dummy word line during data reading. And the second bit line, and between the first dummy word line and the second bit line by capacitive coupling.
An offset voltage is generated on the bit line. At this time, the second
The capacitive coupling between the word line and the first bit line causes an offset voltage on the first bit line. Therefore, the offset voltages generated in the first and second bit lines cancel each other out, and there is no change in the amount of signal transmitted from the memory cell to the bit line.

According to the second invention, similarly to the first invention, at the time of data reading, between the word line and the second bit line,
And an offset voltage of the second bit line caused by capacitive coupling between the first word line and the second bit line;
And the offset voltage of the first bit line caused by the capacitive coupling between the dummy word line and the first bit line cancel each other out, and there is no change in the amount of signal transmitted from the memory cell to the bit line. Therefore, the above problem can be solved.

[0012]

1 is a schematic circuit diagram of a memory cell portion in a DRAM showing an embodiment of the present invention, in which elements common to those in FIG. 2 of the prior art are designated by common reference numerals. In this memory cell portion, a plurality of second dummy word lines DWL ₀ and DWL ₁ crossing the complementary first and second bit lines BL _a and BL _b are provided in the vicinity of a plurality of second dummy word lines DWL ₀ and DWL ₁ .
Dummy word lines DWL ₂ and DWL ₃ are provided. First dummy word line DWL ₀ and second bit line B
At the intersection with L _b , the gate has the dummy word line DW.
At L ₀ , the NMO whose source is connected to the bit line BL _b
A first dummy cell 20 ₁ made of S is provided.
The first dummy word line DWL ₁ and the first bit line BL _a
At the intersection of the gate and the dummy word line DWL ₁
Is provided with a _first dummy cell 20 ₁ made of an NMOS whose source is connected to the bit line BL _a .

Similarly, at the intersection of the second dummy word line DWL ₂ and the first bit line BL _a , the gate is connected to the dummy word line DWL ₂ and the source is connected to the bit line BL _a . A second dummy cell 20 ₃ is provided.
The second dummy word line DWL ₃ and the second bit line BL _b
At the intersection of the gate and the dummy word line DWL ₃
, A second dummy cell 20 ₄ whose source is connected to the bit line BL _b is provided. Other configurations are the same as those of the conventional FIG.

That is, the first and second bit lines BL _a , BL
_At the intersection of _b and the plurality of word lines WL ₀ and WL ₁ ,
The memory cells 10 ₁ and 10 ₂ are connected to each other.
In the memory cell 10 ₁ , a charge storage capacitor 11 and a charge transfer NMOS 12 are connected in series between ½ · VCC and a bit line BL _b, and the gate of the NMOS 12 is connected to a word line WL _0. ing. Memory cell 10
_{2 is} also a capacitor 11 for charge storage and an NM for charge transfer
And OS12 is connected in series between the 1/2 · VCC and the bit line BL _a, the gate of the NMOS12 word line W
It is connected to L ₁ . The first and second bit lines BL _a ,
An equalizing circuit 30 including NMOSs 31, 32, and 33 is connected to one end of BL _b , and the bit lines BL _a and B
At the other end of L _b , NMOS 41, 42 and PMOS 4
A sense amplifier 40 composed of 3 and 44 is connected, and complementary data lines D _a and D _b are connected via NMOSs 51 and 52 for data transfer.

FIG. 4 is a timing chart of the operation of reading the "0" information stored in the memory cell 10 ₁ when the boost level of the word lines WL ₀ and WL ₁ is (VCC + V _T + α). FIG. 5 is a timing chart of the read operation of the “0” information stored in the memory cell 10 ₁ when the boost level of the word lines WL ₀ and WL ₁ is 2 VCC. The read operations (1) and (2) in FIG. 1 will be described with reference to these drawings.

(1) Operation of FIG. 4 When the equalize signal EQ is at the VCC level, the bit lines BL _a and BL _b are equalized to ½ · VCC because the NMOSs 31, 32 and 33 in the equalize circuit 30 are in the ON state. Has been done. In addition, sense amplifier activation signals φ _a and φ
_{Since b is} also equalized to 1/2 · VCC, the NMOS 41 and 42 and the PMOS 4 in the sense amplifier 40 are
3,44 are off. Equalize signal EQ
Transition from the VCC level to the GND level, the NMOSs 31, 32 and 33 in the equalize circuit 30 are turned off, and then the word line WL ₀ selected by the decoder (not shown) rises to the “H” level and is connected to it. The NMOS 12 in the memory cell 10 ₁ is turned on, and the “0” information stored in the memory cell 10 ₁ is output to the bit line BL _b .

At this time, the word line WL ₀ makes a transition from the GND level to the (VCC + V _T + α) level, and the dummy word line DWL ₀ makes a transition from the VCC level to the GND level. At this time, the word line WL ₀ and the dummy word line DWL
_{Since 0} has a voltage amplitude difference ΔV = V _T + α, the word line WL ₀ and the bit line BL _b , and the dummy word line DW.
The capacitive coupling of the gate capacitance between L ₀ and the bit line BL _b causes an offset voltage ΔVs on the bit line BL _b . Further, since the dummy word line DWL ₂ makes a transition from the VCC level to the (VCC + V _T + α) level with respect to the dummy word line DWL ₀ , capacitive coupling of the gate capacitance between the dummy word line DWL ₂ and the bit line BL _a An offset voltage ΔVs is generated on the bit line BL _a . for that reason,
Offset voltage Δ occurring on the bit lines BL _b and BL _a
Vs are offset from each other, there is no change in the amount of the signal transmitted from the memory cell 10 ₁ to the bit line BL _b.

Therefore, the potential difference between the bit lines BL _a and BL _b becomes sufficiently large before the operation of the sense amplifier 40, and then the sense amplifier activation signal φ _a becomes 1/2 · V.
As the CC level rises from the CC level to the VCC level, the sense amplifier activation signal φ _b changes from ½ · VCC level to
The voltage goes down to the D level, the sense amplifier 40 operates, and the potential difference between the bit lines BL _a and BL _b is amplified. And
The column line Y-DEC rises from the GND level to the VCC level, the data transfer NMOSs 51 and 52 are turned on, and the read information “0” on the bit lines BL _a and BL _b.
Are accurately read to the data lines D _a and D _b .

(2) Operation of FIG. 5 When the equalizing signal EQ is at the VCC level, the equalizing circuit 30 causes the bit lines BL _a and BL _{b to} be ½ · V.
CC is equalized to sense amplifier activation signal φ _a ,
φ _{b is} also equalized to 1/2 · VCC, and the sense amplifier 40 is in the off state. Equalize signal EQ is V
When the level is changed from the CC level to the GND level, the equalizer circuit 30 is turned off, then the word line WL ₀ selected by the decoder (not shown) rises to the “H” level, and the NM in the memory cell 10 ₁ connected to it.
The OS 12 is turned on, and the "0" information stored in the memory cell 10 ₁ is output to the bit line BL _b .

At this time, the word line WL ₀ transits from the GND level to the 2VCC level, and the dummy word line DWL _0.
Changes from the VCC level to the GND level. The voltage amplitude difference ΔV = between the word line WL ₀ and the dummy word line DWL ₀
Since there is VCC, word line WL ₀ and bit line BL
_An offset voltage ΔVs is generated on the bit line BL _b due to capacitive coupling of the gate capacitance between the _b and the dummy word line DWL ₀ and the bit line BL _b . At this time, since the dummy word line DWL ₂ makes a transition from the GND level to the VCC level with respect to the dummy word line DWL ₀ , the bit line is capacitively coupled between the dummy word line DWL ₂ and the bit line BL _a. An offset voltage ΔVs is generated at BL _a . Therefore, the offset voltages ΔVs generated on the bit lines BL _b and BL _a cancel each other out, and the memory cell 1
There is no change in the amount of signal transmitted from 0 ₁ to the bit line BL _b . Therefore, the potential difference between the bit lines BL _a and BL _b becomes sufficiently large before the sense amplifier 40 operates, and then the sense amplifier 40 operates to operate the bit lines BL _a and B _b .
The potential difference between L _b is amplified, the NMOS 51 and 52 are turned on by the column line Y-DEC, and the bit line B
The read information “0” on L _a and BL _{b corresponds} to the data lines D _a and
Exactly read to D _b .

As described above, this embodiment has the following advantages. (A) The word line WL ₀ changes from the GND level to (VCC +
When transitioning to the V _T + α) level, the first dummy word line DWL ₀ is transitioned from the VCC level to the GND level, and the second dummy word line DWL ₂ is transitioned from the VCC level to the (VCC + V _T + α) level. Since this is done, the offset voltage ΔVs generated between the bit lines BL _a and BL _b is canceled and becomes zero. As a result, there is no change in the amount of signal transmitted from the memory cell 10 ₁ to the bit line BL _b , and correct information can be read.

(B) When the word line WL ₀ changes from the GND level to 2VCC, the first dummy word line DW
The L ₀ is changed from the VCC level to the GND level, and the second
Since the dummy word line DWL ₂ is changed from the GND level to the VCC level, the bit lines BL _a and BL
_The offset voltage ΔVs generated between _b is canceled and becomes 0. As a result, from the memory cell 10 ₁ to the bit line BL _b
There is no change in the amount of signal transmitted to, and correct information can be read.

(C) In the above (a) and (b), since the offset voltage ΔVs generated between the bit lines BL _a and BL _b becomes 0, a DRAM using a low voltage, for example, VC
Even when C = 1.5 V, correct information can be read without loss of the read signal amount. In addition,
The present invention is not limited to the above embodiment, and various modifications can be made. For example, the bit line BL _a of the memory cell portion of FIG.
BL _b , word lines WL ₀ and WL ₁ , and dummy word lines DWL ₀ , DWL ₁ , DWL ₂ and DWL ₃ can be set to any number, and memory cells 10 ₁ and 10 ₂ and dummy cells 2
0 ₁ , 20 ₂ , 20 ₃ , 20 ₄ may be configured by other circuits, or the equalizing circuit 30, the sense amplifier 40,
The data transfer NMOSs 51 and 52 may have other transistor configurations. Further, the above embodiment can be applied to other semiconductor integrated circuit devices such as semiconductor memories.

[0024]

As described in detail above, according to the first aspect of the present invention, when the word line is transitioned to the activation level when data is read from the memory cell, the first dummy word line is set to the precharge level. From the first power supply potential level to the second dummy word line from the precharge level to the activation level of the word line, the offset voltages generated in the first and second bit lines cancel each other out. Is set to 0. As a result, there is no change in the amount of signal transmitted from the memory cell to the bit line, and correct information can be read. Moreover, since the offset voltage generated in the first and second bit lines becomes 0, DR using a low voltage is used.
Even in a semiconductor integrated circuit device such as AM, correct information can be read without loss of read signal amount.

According to the second aspect of the present invention, when data is read from the memory cell, the first dummy word line is set to the second power supply when the word line is transitioned to a level approximately twice the second power supply potential level. Since the transition from the potential level to the first power supply potential level is made and the second dummy word line is made to transition from the first power supply potential level to the second power supply potential level, the first and second bit lines are The resulting offset voltage is canceled and becomes zero. Therefore, as in the first aspect of the invention, the amount of signal transmitted from the memory cell to the bit line does not change, and not only correct information can be read but also in a semiconductor integrated circuit device such as a DRAM using a low voltage. Also, correct information can be read without loss of the read signal amount. Therefore, it can be applied to various semiconductor integrated circuit devices such as semiconductor memories.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of a memory cell portion in a DRAM showing an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a memory cell portion in a conventional DRAM.

FIG. 3 is a timing chart of a “0” information read operation of FIG.

FIG. 4 is a timing chart of the “0” information read operation of FIG. 1.

5 is a timing chart of a "0" information read operation of FIG.

[Explanation of symbols]

10 ₁ , 10 ₂ Memory cell 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ Dummy cell 30 Equalize circuit 40 Sense amplifier 51, 52 NM for data transfer
OS BL _a, BL _b first, second bit line D _a, D _b data line DWL _0, DWL ₁ first dummy word line DWL _2, DWL ₃ second dummy word line

Claims (2)

[Claims] 1. A complementary first and second bit line, a word line cross-arranged with respect to the first and second bit line, and a complementary bit line with respect to the first and second bit line. First dummy word lines arranged in a cross manner, memory cells connected to an intersection of the first or second bit line and the word line, the first or second bit line and the first A first dummy cell connected to an intersection of the first dummy cell and the second dummy word line, and a second dummy word line cross-arranged with respect to the first and second bit lines. , A second dummy cell connected to an intersection of the second or first bit line and the second dummy word line is provided, and when the data is read from the memory cell, the word line is activated at an activation level. To the first dummy word line From Jireberu to the first power supply potential level, said the level of activation of the second dummy word line the word line from the precharge level, the semiconductor integrated circuit device being characterized in that the arrangement for shifting respectively. 2. The second dummy word line and the second dummy cell according to claim 1, wherein the word line is set to a level approximately twice the second power supply potential level when data is read from the memory cell. , The first dummy word line transitions from the second power supply potential level to the first power supply potential level, and the second dummy word line transitions from the first power supply potential level to the second power supply potential level. A semiconductor integrated circuit device having a configuration.