KR920010342B1 - Mdram p.c.p. sensor amplifier - Google Patents

Abstract

In the P.C.P (PMOS latch cut-off voltage level precharge scheme) sense amplifier for decreasing the size and the interconnection line of mega DRAM, the equalizing signal is applied to the equalizing transistor (Q18) and the precharge driving transistor (Q17). The source and the drain of the equalizing transistor is connected to the bit line and the bit line, respectively. The source and the drain of the precharge driving transistor is connected to the ground and the common source of PMOS latch transistor (Q14,Q15), respectively. The cut-off voltage level of PMOS latch transistor is used in t of precharging.

Description

PMOS latch cut-off voltage level precharge scheme (P.C.P.) sense amplifiers for mega DRAM

1 is a circuit diagram showing the configuration of a conventional CMOS sense amplifier.

2 shows P.C.P. of the present invention. Sense Amplifier Schematic.

3a, b, c are graphs showing the operating characteristics of the conventional and the sense amplifier of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier for mega DRAM, and is particularly used for ultra-high-density large-capacity DRAM and invents a new precharge method to reduce the time required for data sensing. A sense amplifier for one mega DRAM. Currently, single-transistor memory cell structures used in DRAMs have more than half the number of elements per unit of structure compared to three-transistor memory cell structures. Because of the charge redistribution effect between the storage capacitance Ca of the capacitor and the capacitance Cb existing on the bit line, the size of the effective information is reduced by several tens of mV.

In addition, since the storage capacitance of the cell is a passive element, an undesirable result is that the information stored in the storage capacitor is destroyed during reading.

In order to solve this problem, a sense amplifier that detects and amplifies a small minute voltage difference and puts an amplified signal back into a cell must be used in a DRAM to prevent information from being destroyed. This conventional sense amplifier circuit, which plays an important role in DRAM, has an equalizing signal along with the precharge to the gates of transistors Q ₇ , Q ₈ , and Q _{9 as} shown in FIG. When applied, the bit line and bit line are equalized with the precharge voltage with the precharge voltage.

)과 전압차(△V)가 발생한다.Then, when the word line is selected (assuming WL ₁ is selected), the information stored in the storage capacitance is applied to the bit line so that as much as ΔV (about 200 mV when Cs is 30fp), the bit line (

) And a voltage difference DELTA V.

This ΔV turns on the transistor Q ₆ to operate the NMOS latch transistors Q ₄ and Q ₅ to pull down ΔV and turns on the transistor Q ₃ to turn on the PMOS latch transistor. It is sense-amplified by a pull-up operation that completely restores to the desired level by (Q ₁ ), (Q ₂ ).

)을 1/2V_DD로 프리차지 하는 기존의 방법은 4메가 비트 DRAM 이후 부터는 소자의 크기를 축소에 감에 따라 소자 신뢰성에 대한 문제가 야기되어, V_DD를 5V에서 3.3V로 줄여 나가는 실정이기 때문에 1/2V_DD방식은 성능이 저하되는 단점이 있다.However, as above, two bit lines (

The conventional method of precharging) to 1 / 2V _DD causes device reliability problems as the size of the device decreases after 4 megabit DRAM, reducing V _DD from 5V to 3.3V. Therefore, the 1 / 2V _DD method has a disadvantage in that performance is degraded.

Thus, a method of precharging the precharge voltage to 2 / 3V _DD in the case of using a PMOS array (array) and 1 / 3V _DD in the case of the NMOS array has been experimentally attempted.

However, this approach improves the sensing speed for 1 / 2V _DD , but causes many problems such as high bit line capacitance and increased power consumption, and it takes some time to precharge the bit line.

In addition, according to the conventional sense amplifier technology using the aforementioned 1 / 2V _DD , 2 / 3V _DD or 1 / 3V _DD as the precharge voltage, the internal operating characteristics have advantages and disadvantages, respectively. Of course, there are disadvantages such as a separate configuration for supplying a precharge voltage and a wiring for applying a precharge voltage.

Accordingly, an object of the present invention is to provide a sense amplifier for a mega DRAM, which is applied to an ultra-high-density large-capacity DRAM and has a simple structure and a fast information sensing speed. To this end, the present invention precharges the bit line and the bit line using the cut-off voltage level of the latch transistor of the PMOS, so that the sensing speed is faster than that of the 2 / 3V _DD , and the number of transistors and wirings is reduced. This reduces the size of the circuit and eliminates the need for a precharge constant voltage generator.

The present invention will be described in detail with reference to the accompanying drawings as follows.

The precharge and equalizing signals are applied to the gates of the equalizing transistor Q ₁₈ and the precharge driving transistor Q ₁₇ , and the source and drain of the equalizing transistor Q ₁₈ are bit lines and bit lines. The precharge driving transistor Q ₁₇ is connected to the bit line, and the source is connected to the ground using the NMOS, and the drain is connected to the common source of the PMOS latch transistors Q ₁₄ and Q ₁₅ .

)에 연결하고 PMOS 래치 구동 트랜지스터(Q₁₆)는 소오스를 V_DD공급선에 연결하고 드레인을 PMOS 래치 공통 소오스에 연결한다. NMOS 래치 트랜지스터(Q₁₁),(Q₁₂)등 다른 트랜지스터들의 연결은 기존의 방법과 같다.In addition, the PMOS latch transistors Q ₁₄ and Q ₁₅ have respective gates connected to bit lines and bit lines.

), And the PMOS latch drive transistor Q ₁₆ connects the source to the V _DD supply line and the drain to the PMOS latch common source. The connection of other transistors such as the NMOS latch transistors Q ₁₁ and Q ₁₂ is the same as the conventional method.

P.C.P. of the present invention configured in this way The operation of the sense amplifier is described in detail as follows.

)이 각각 높은 상태(“1”)와 낮은 상태(“1”)로 유지되어 있다고 하면 프리차지와 이퀄라이징 신호가 이퀄라이징 트랜지스터(Q₁₈)와 프라차지 구동 트랜지스터(Q₁₇)의 게이트로 인가되어 두 트랜지스터(Q₆)과 (Q₇)를 ON시키는데 이때 비트라인(Bit line)의 높은 상태 전압은 이퀄라이징 트랜지스터(Q₁₈)을 통하여 비트라인에(

)에 프리차지되고 동시에 PMOS 래치 트랜지스터(Q₁₄),(Q₁₅)중 게이트가 비트라인(

)에 연결된 트랜지스터(Q₁₅)는 ON상태를 유지하여 프라차지 구동 트랜지스터(Q₁₇)를 통하여 방전(discharge)된다. 그러다가 PMOS 래치 트랜지스터의 단락 전압 레벨에서 트랜지스터(Q₁₅)가 OFF되어 비트라인(Bit line)과 비트라인(

)은 PMOS 래치 전압 레벨로 프리차지와 이퀄라이징 된다.First bit line and bit line (

) Is maintained at a high state ("1") and a low state ("1"), respectively, and the precharge and equalizing signals are applied to the gates of the equalizing transistor Q ₁₈ and the precharge driving transistor Q ₁₇ . The transistors Q ₆ and Q _{7 are turned on} , and the high state voltage of the bit line is transferred to the bit line through the equalizing transistor Q ₁₈ .

) And the gates of the PMOS latch transistors Q ₁₄ and Q ₁₅ are simultaneously

The transistor Q ₁₅ connected to) is maintained in the ON state and discharged through the precharge driving transistor Q ₁₇ . Then, at the short-circuit voltage level of the PMOS latch transistor, transistor Q ₁₅ is turned off to turn off bit line and bit line (

) Is precharged and equalized to the PMOS latch voltage level.

)에 △V가 인가되면 트랜지스터(Q3)과 (Q₆)을 ON시켜 NMOS 래치 트랜지스터(Q₁₁),(Q₁₂)와 PMOS 래치 트랜지스터(Q₁₄),(Q₁₅)를 구동하여 감지한 정보를 원하는 레벨까지 증폭한다.After that, the word line is selected (assuming WL ₁ is selected) and the bit line and bit line (

) In △ V is applied when the transistor (Q3) and (Q _6), the ON to detect drives the NMOS latch transistor _{(Q 11), (Q 12} ) and a PMOS latch transistor _{(Q 14), (Q 15} ) the information Amplify to the desired level.

) 풀업되는 단락 전압 레벨에 이르는 속도가 1/2V_DD의 경우(제3a도)와 2/3V_DD의 경우(제3b도)보다 빨라지도록 한 것이다.Therefore, the PCP sense amplifier of the present invention is to ensure the correct operation even if a separate precharge voltage is not applied to 1 / 2V _DD, as well as the bit line (Bit) as shown in comparison with FIGS. 3a, b, and c. line is pulled down,

The speed up to the pulled-up short-circuit voltage level is faster than that of 1 / 2V _DD (Figure 3a) and 2 / 3V _DD (Figure 3b).

In addition, since the precharge driving transistor to which the equalizing signal is applied to the gate is reduced from two to one, it can be seen that the size and number of wirings that are most problematic in large-capacity high-density DRAM can be reduced.

Claims (1)

The equalizing signal is applied to the gates of the equalizing transistor Q ₁₈ and the precharge driving transistor Q _17. The source and drain of the equalizing transistor Q ₁₈ are divided into a bit line and a bit line.

Are connected to the common source of the PMOS latch transistors Q ₁₄ and Q ₁₅ , and the precharge driving transistor Q ₁₇ is connected to the common source of the PMOS latch transistors Q ₁₄ and Q ₁₅ . Q ₁₅ ) A PCP sense amplifier for mega DRAMs, which is configured using a cut-off voltage level.

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