JPS6161479B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and in particular to a one-transistor type dynamic memory.

Please note that the following explanations are all for N channel for convenience.
Although MOS transistors are used as examples, the present invention is essentially equally applicable to P-channel MOS transistors or any other type of insulated gate transistor.

A block diagram of a conventional one-transistor type dynamic memory is shown in FIG. In Figure 1, 1
is an X decoder that selects one of n word lines according to the X address signals X ₀ , X ₁ , ......X _l , and 2 and 2' are memory cells arranged in m rows and o columns. , a memory cell matrix consisting of m bit lines and n word lines, 3 a sense amplifier group provided corresponding to each bit line, 4 Y address signals Y ₀ , Y ₁ , etc. . . . A Y decoder selects one row of m bit lines according to Y _r . 5 is an input/output circuit that receives an output signal from the Y decoder and controls input/output signals from the bit line. . Further, a circuit block diagram of the i-th line circuit of FIG. 1 is shown in FIG. 2. In FIG. 2, 20 and 20' are the i-th bit lines B _i and _i
j representing a large number of memory cells connected and arranged in
The memory cells 21 and 21' connected to the word lines W _j and W _k of the th and kth columns serve as standards for generating a potential between high and low binary levels read from the memory cells on the bit line B _i or _i . potential generation circuit,
30 is a sense amplifier that amplifies the minute difference signal read from the memory cells to the bit lines B _i and _i at the timing of the clock signal P2; 50 is the bit line B _i
Input/output circuits 60 and 60' control the reading of the above amplified difference signal and the writing to the bit line by the output signal PY _i from the Y decoder, and 60 and 60' are clock signals P1.
C _B is the bit line parasitic capacitance added to bit lines _{B i and i .}

FIG. 3 shows a conventional memory cell using a MOS structure as the cell capacitance _CSO3 . At this time
Since the capacitance of the MOS structure has a threshold voltage, the gate electrode of the cell capacitor _CSO3 is connected to the highest voltage power supply _VDD used in this memory, and the source and drain electrodes are connected to the node S, which is as high as possible. It was used to store electrical potential. However, if this is done, fluctuations in the power supply V _DD will fluctuate the potential stored at the node S through the cell capacitance C _SO3 , resulting in malfunction.

Therefore, recently we have used multilayer polysilicon technology,
In some cases, a capacitor having no threshold voltage is created between these polysilicon layers and used as a cell capacitor.
This memory cell is shown in FIG. Here, the cell capacitance _CSO4 is the same as an ordinary capacitance that does not have a threshold voltage, so the other electrode connected to the node S must be kept at a constant potential, and normally the potential changes. This is the lowest ground potential.

In addition, in Figures 3 and 4, cell capacitance C _SO3 and C _S
All other parts have the same structure except for the structure of _O4 . That is, the gate of the selection gate GT is connected to the word line W, the drain is connected to the bit line B, and the source is connected to the node S. Further, the parasitic capacitance added to the node S is represented by C _S1 . Here, the following description will be made assuming that the total capacitance attached to the node S, which is the sum of the cell capacitance C _SO3 or C _SO4 and the parasitic capacitance C _S1 , is referred to as the storage capacity C _S .

In FIG. 2, after operating the precharge circuits 60 and 60' with the clock signal P1, when the word line selected by the X decoder becomes high potential, the bit lines provided in pairs on the left and right sides of the sense amplifier 30 The cell information stored in one of the many memory cells connected to B _i and _i is read out to the bit line to which that memory cell belongs,
On the other bit line, a potential intermediate between the two high and low levels generated on the bit line is generated by the reference potential generation circuit in accordance with "H" and "L" of the cell information.
For example, when word line W _j is selected, cell information of memory cell 20 is read onto bit line B _i , and a reference potential is generated on bit line _i by reference potential generation circuit 21'. Conversely, when word line W _k is selected, the cell information of memory cell 20' is transferred to bit line _i.
The reference potential generation circuit 21 generates a reference potential on the bit line B _i . As a result,
A minute potential difference is generated between the bit lines B _i and _i , which is determined by the capacitance division between the storage capacitance C _S of the memory cell and the parasitic capacitance C _B of the bit line. Here, the minute potential difference is amplified by activating the sense amplifier 30 by the clock signal P2. Thereafter, the information on the bit line B _i is outputted through the input/output circuit 50 selected by the output signal PY _i from the Y decoder, and reading of the cell information is completed. Also, in writing, information is written to the bit line and memory cell through the input/output circuit 50.

FIG. 5 shows voltage waveforms at various parts when a conventional dynamic memory is driven by a normal driving method and word line W _j is selected. In order to drive a semiconductor memory with the conventional structure, first, the clock signal P1 is set to a low level and the word line W is driven.
The cell information of the memory cell 20 is read out to the bit line B _i by setting the potential of _j to a high level. At the same time, reference potential generation circuit 2 is applied to bit line _i .
1' generates a reference potential, so the sense amplifier 30 activated by the clock signal P2 generates a minute potential difference between B _i and _i as a result.
The potential of the bit line B _i at that time is rewritten into the memory cell 20 as refreshed information. In this case, the minute potential difference ΔV read from the memory cell to the bit line
If the precharge potential of the bit line is V _BO and the storage potential at node S in the memory cell is V _SO , then C _S =C _SO3 +C _S1 or C _S +C _SO4 +C _S1 △=(C _S /C _S + C _B )・(V _SO −V _BO ). Furthermore, if the potentials of the node S representing "H" and "L" of cell information stored in a memory cell are V _H and V _L , then the read signal difference between "H" and "L" cell information is △ V _HL is △V _HL = (C _S /C _S +C _B )・{(V _H −V _BO )−(V _L −V _BO )}=(1/1+C _B /C _S )・(V _H −V _L ). Therefore, the cell information read signal difference ΔV _HL is approximately inversely proportional to the division ratio C _B /C _S between the parasitic capacitance C _B of the bit line and the storage capacity C _S of the memory cell.
The “H” information potential V _H and the “L” information potential V _L stored in the storage capacitor C _S in the memory cell
It can be seen that it is proportional to the potential difference (V _H - V _L ) between the two.

As mentioned above, in the conventional one-transistor type dynamic memory explained in detail using each figure from FIG. 1 to FIG. 5, a large number of memory cells are connected to one bit line, so the memory is large. As the capacitance increases, the number of memory cells coupled to the bit line increases, the parasitic capacitance C _B of the bit line increases, and the division ratio C _B / _{CS of the memory cell with respect to the storage capacity C S also} increases. Then, as shown in the previous calculation, the cell information read signal difference △V _HL is
Since it is almost inversely proportional to the division ratio C _B /C _S , it becomes very small. In order to compensate for this, it is sufficient to increase the potential difference (V _H - V _L ) between the potentials V _H and V _L of the "H" and "L" cell information in the memory cell, but the "H" cell information The potential V _H is set to be slightly lower than the voltage of the power supply that supplies the highest voltage used in this conventional memory device, and the potential V _L of "L" cell information is set to the ground potential. , the increase in segmentation C _B /C _S is expressed as the cell information potential difference (V _H −
It was difficult to compensate by increasing V _L ). Therefore, as the power supply voltage used for this memory becomes lower, the potential of "H" cell information in the memory cell V _H
As the voltage decreases, the read signal difference ΔV _HL from the memory cell becomes smaller, and a sense amplifier with higher sensitivity becomes necessary. This was a serious drawback of the conventional example.

An object of the present invention is to provide a semiconductor memory device that can increase the capacity without using a highly sensitive sense amplifier, and another object of the present invention is to provide a semiconductor memory device with a large storage capacity and a small chip area. It is another object of the present invention to provide a semiconductor memory device in which memory cell refresh intervals are long and the memory can be used with high efficiency.

According to the present invention, as shown in FIGS. 6 to 9, bit lines are arranged as rows and word lines are arranged as columns, and memory cells are attached near each intersection between the rows and columns. A first storage word line provided substantially parallel to the word line to form a pair with the word line.
and a second memory cell matrix, and a number equal to the number of rows arranged in columns in which the first and second memory cell matrices are arranged on the left and right thereof, and each is connected to the corresponding bit line on the left and right, respectively. a sense amplifier, an a decoder, wherein the memory cell includes at least one selection gate and one cell capacitor, a control terminal of the selection gate is connected to the word line, and a first input/output terminal is connected to the word line. The second input/output terminal is connected to the bit line, the second input/output terminal is connected to the first electrode of the cell capacitor, and the second electrode of the cell capacitor is connected to the storage word line. There are two signal levels at the time, a first level of high potential and a second level of intermediate potential, that is, the first level is the level of the selected signal when reading the binary information expressed by the charge level accumulated in the capacitor. The gate is completely conductive, and the potential of the bit line and the first voltage of the cell capacitance are
The second level is set to a potential that substantially equalizes the potentials of the electrodes, and when the potential of the bit line after activating the sense amplifier is at a high level, the selection gate is made non-conductive and the second level is set at a low level. When , the selection gate is set to a potential that makes it conductive, and the potential of the storage word line changes from a high potential to a low potential after the word line is at the first level and the sense amplifier is activated. There is obtained a semiconductor memory device characterized in that the word line is set to change from a low potential to a high potential after being set to the second level.

The present invention mainly improves the latter of the selection gate and the information storage capacitor that constitute the memory cell, and when storing the potential of cell information "H" at the node S in the memory cell, the conventional cell The "H" and "L" cells stored in the memory cell are designed to store a higher potential than the potential of the information "H" and maintain the potential of the cell information "L" at the same potential as before. This succeeded in increasing the potential difference of information.

The present invention will now be described in detail using typical examples to aid understanding.

FIGS. 6 to 9 show an embodiment of the present invention in the same manner as FIGS. 1 to 5.
Equivalent parts are given the same reference numerals for convenience of comparison.

FIG _. 6 is a block diagram, and the difference from the conventional example shown in FIG. storage word line Z _j (j=1, 2,...
Although the X decoder 10 does not look much different from the conventional X decoder (1 in Figure 1), it always connects the word line and the newly installed storage word line to 2. It has been changed to select in pairs.

FIG. 7 is a diagram taken out of the i-th line of the circuit in FIG. 6, and corresponds to FIG. 2 of the conventional example. 7th
The embodiment of the present invention shown in the figure _is different from the conventional configuration shown in FIG _. That's true.

FIG. 8 is a diagram showing in more detail an example of the configuration of a memory cell suitable for the present invention, which corresponds to the memory cells 22, 22' of FIG. 7. This configuration differs from the conventional example shown in FIGS. 3 and 4 as follows:
This is because the electrode of cell capacitor C _SO8 , which was conventionally used as a power supply level or ground level, is connected to storage word line Z. The structure of cell capacitor C _SO8 is the same as that of cell capacitor C _SO4 shown in Fig. 4, and it has a threshold voltage. It has a capacitor structure.

FIG. 9 shows the operating waveforms of FIGS. 7 and 8, and corresponds to FIG. 5 of the conventional example.

Here, as an example, the read operation and cell information storage operation when the memory cell shown in FIG. 8 is inserted into the circuit shown in FIG. 7 are selected when the i-th row and j-th memory cell shown in FIG. This will be explained using the operating waveforms.

In the present invention, as shown in FIG. 9, the operation is the same as that of the conventional example until the sense amplifier 30 is activated by the clock signal P2 and the minute difference signal read out from the memory cell onto the bit line is amplified. . After this amplification operation is completed, the storage word line _Zj , which had been kept at the potential of _VZ , is brought to a low potential. At this time, the potential at the node S decreases due to the coupling of the cell capacitance C _SO8 , but this decrease is replenished from the bit line B _i because the word line W _j is at a high level and the selection gate GT is conductive. Ru. Therefore, the potential at node S hardly changes. Next, the word line W _j is set to an intermediate level V' _W , that is, when the level of the bit line is high after the amplification operation by the sense amplifier is completed, the selection gate GT is made non-conductive, and when the level of the bit line is low, the selection gate is turned off.
Set to a level that makes GT conductive. Thereafter, when the storage word line Z _j is returned from the low potential to the high potential again, the potential at the node S in the memory cell rises due to the coupling of the cell capacitance C _SO8 . The increase in the potential of the node S at this time ΔV' becomes ΔV'=V _Z /1+C _S1 /C _SO8 , where V _Z is the amount of change in the potential of the storage word line Z _j . However, this only holds true when the selection gate GT is non-conductive, and when the selection gate GT is conductive, this increase in potential △V' is absorbed by the bit line B _i and becomes the node S. The potential remains low and does not rise. If the word line W _j is set to a low level, the selection gate GT becomes completely non-conductive, and cell information is stored in the storage capacitor C _S in the memory cell. At this time, the potential of the cell information "H" stored in the node S can be higher than the conventional one by △ _V ', and the potential of the cell information "L" is the same as that of the conventional one, so as a result, the cell The potential difference between information "H" and "L" can now be increased by ΔV'.

Moreover, the X decoder 10 used in the present invention has 1
It is sufficient to adopt a configuration that outputs two signals with different timings for the set of X address signals X ₀ , X ₁ , .........X _l , and the output of the conventional A model that branches into two may also be used. In addition, two conventional X decoders are provided, and each
The word line and storage word line may be driven separately by the decoder.

As described in detail above, the present invention uses a capacitor whose cell capacitance does not have voltage dependence, which constitutes a memory cell, and drives the capacitor with a newly provided storage word line, thereby transmitting cell information. The effect of increasing the potential difference between "H" and "L" is obtained. Therefore, if it is sufficient to read a signal of the same size as before from a memory cell, the cell capacitance can be made smaller than before, and a large capacity can be achieved without using a particularly sensitive sense amplifier. You may think that it will be possible to
If the storage capacity of the memory device is considered fixed, then the effect of reducing the chip area will be obtained. In addition, since the potential difference between the cell information "H" and "L" stored in the cell can be increased, in the case where it is thought that there is a leakage current of the same level as before, the potential difference between the cell information "H" and the cell information "H" is higher. You can lengthen the refresh interval. In other words, this can be interpreted as an effect of increasing the usage efficiency of the memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional semiconductor memory device, FIG. 2 is a block diagram showing the i-th row of the circuit in FIG. 1, and FIGS. 3 and 4 are diagrams showing a conventional memory cell. The circuit diagram shown in FIG. 5 is an operating waveform diagram of the conventional circuit. FIG. 6 is a block diagram showing an embodiment of the present invention, FIG. 7 is a block diagram showing the i-th line of FIG. 6, and FIG. 8 is a circuit diagram showing a memory cell of the present invention. FIG. 9 is an operational waveform diagram of the circuit of the present invention. In the figure, 1 and 10 are X decoders, 2 and 2'
is a memory cell matrix, 3 and 30 are sense amplifiers, 4 is a Y decoder, 5 and 50 are input/output circuits, 2
0, 20', 22, 22' are memory cells, 21, 2
1' is a reference potential generation circuit, 60, 60' are precharge circuits, W _j , W _k , W are word lines, B _i , _i ,
B is a bit line, Z _j , Z _k , Z are storage word lines, X ₀ , X ₁ , ......, X _l are X address signals, Y ₀ , Y ₁ , ......, Y _r is the Y address signal, GT is the selection gate, C _SO3 , C _SO4 , C _SO8 are the cell capacitances, C _B is the parasitic capacitance added to the bit line, C _S
1 indicates the parasitic capacitance distributed within the memory cell.

Claims (1)

[Claims] 1. A memory cell is provided with a plurality of word lines and bit lines, and has a capacitor and a selection transistor that turns on and off depending on the potential of the word line to open and close a connection between one electrode of the capacitor and the bit line. In a semiconductor memory device arranged at an intersection of bit lines, after the selection transistor is selected and the bit line reaches a predetermined high or low potential, the potential of the other electrode of the capacitor is lowered once again. By raising the other electrode of the capacitor again, when one electrode of the capacitor is at a high potential, this high potential is increased, and when one electrode of the capacitor is at a low potential, the high potential is increased substantially. A semiconductor memory device characterized in that the selection transistor is operated so as not to change this potential.