JP2765856B2 - Memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a memory circuit that simultaneously satisfies low power consumption and high S / N of a MOS-DRAM.

[Conventional technology]

A conventional DRAM circuit includes a memory array (memory cell matrix) composed of a plurality of memory cells for storing signals and one of a plurality of memory cells as described in JP-B-61-61479.
And a sense amplifier for amplifying a signal read from a memory cell. The memory cell matrix is composed of bit lines (data lines), word lines provided so as to intersect them, and memory cells provided at the intersections. Memory cell is one MOS-F
The MOS-FET has a drain terminal connected to a data line, a source terminal connected to one end of the capacitor, and a gate terminal connected to a word line. Writing of signals to the memory cells in these circuits is performed as follows. A certain word line voltage is set to a high potential, and a signal (hereinafter, referred to as a memory cell signal) stored in a memory cell is read out to a data line. The read signal is amplified by a sense amplifier, and a pair of data lines is set to a high potential and a low potential. This voltage is written again to the selected memory cell, and the same signal is written again to the memory cell. Thereafter, the potential of the selected word line is slightly lowered from the high potential. The amount of decrease in the potential is such that the transfer gate (MOS-FET) of the memory cell in which the high potential is written is turned off. Thereafter, the potential of a terminal (here, referred to as a plate) not connected to the source terminal of the MOS-FET of the capacitor constituting the memory cell is changed from a low potential to a high potential. As a result, among the memory cell signals, those having a high potential further increase the potential. On the other hand, the potential of a low potential does not change because the potential is held by the sense amplifier. Therefore, the signal amount stored in the memory cell can be increased, and high S / N
Can be achieved. Also, plate wirings arranged for each word line include known examples of Japanese Patent Application Laid-Open Nos. 55-45170, 58-62893, 58-62894 and 62-62894. No. 223884, JP 63237287 as prior application
There is an official gazette.

In recent years, the number of data lines to be charged / discharged at one time has increased along with the high integration of memories, and an increase in power consumption due to the increase has become a problem. However, the above-mentioned memory circuit has not considered these points.

[Problems to be solved by the invention]

The prior art described above does not take into account the increase in power consumption caused by the high integration of memories, and has problems such as a decrease in information retention time of the memory, an increase in noise, and a decrease in reliability.

As a measure against the increase in power consumption, there is a method of lowering the voltage used in the memory. However, the voltage stored in the memory cell cannot be unnecessarily reduced due to the relationship between the information retention time and the α-ray soft error. Therefore, the voltage used in the memory cannot be reduced so much, and it is difficult to greatly reduce the power consumption.

An object of the present invention is to significantly reduce power consumption while sufficiently securing a storage voltage of a memory cell.

[Means for solving the problem]

The object is to provide a plurality of data lines, a plurality of word lines arranged to cross the plurality of data lines, and an intersection of the plurality of data lines and the plurality of word lines. Switching means whose on / off is controlled by the voltage of the corresponding word line of the word line, and a capacitor whose one electrode is connected to the corresponding data line of the plurality of data lines via the switching means. In a memory circuit having a plurality of memory cells and a control circuit for controlling the potential of the other electrode of each capacitor of the plurality of memory cells, a maximum voltage amplitude of an output of the control circuit is a maximum voltage amplitude of the plurality of data lines. Voltage amplitude or more, and during the standby period of the read / write operation to the plurality of memory cells, the potential of each data line of the plurality of data lines becomes the potential of the plurality of data lines. Is achieved by a memory circuit, characterized in that a substantially intermediate potential between the Ureberu potential and high level potential.

Further, the object is to provide a plurality of data lines, a plurality of word lines arranged to intersect the plurality of data lines,
A switching means disposed at an intersection of the plurality of data lines and the plurality of word lines, each of which is controlled to be turned on / off by a voltage of a corresponding word line of the plurality of word lines, and one of the electrodes is connected to the switching means; A plurality of memory cells each having a capacitor connected to a corresponding one of the plurality of data lines via a means, a control circuit for controlling the potential of the other electrode of each capacitor of the plurality of memory cells, A memory circuit having a plurality of sense amplifiers for amplifying a signal read to each of the plurality of data lines to a first potential or a second potential lower than the first potential; The potential of 2 is achieved by a memory circuit characterized in that the potential is higher than the potential when the plurality of word lines are not selected by the maximum voltage amplitude of the output of the control circuit or more.

Further, the object is to provide a plurality of data lines, a plurality of word lines arranged to intersect the plurality of data lines,
A first switching means disposed at an intersection of the plurality of data lines and the plurality of word lines, each of which is turned on / off by a voltage of a corresponding word line of the plurality of word lines, and one electrode thereof; A plurality of memory cells each having a capacitor connected to the corresponding data line of the plurality of data lines via the first switching means, and the other electrode of each capacitor of the plurality of memory cells is connected to the plurality of memory cells. A memory circuit having a control circuit divided for each word line of the word lines and controlling the potential of the other electrode corresponding to the selected word line; and characterized in that the connection between the city of output and said plurality of word lines of the voltage generating circuit further includes a plurality of switching means (T _P63, T _P65) that is controlled by the output of the control circuit It is achieved by that the memory circuit.

[Action]

By controlling the potential of one electrode of the capacitor constituting the memory cell by controlling the potential of the other electrode by the control circuit, the data line voltage amplitude at the time of the memory cell signal can be reduced, and the charge / discharge current of the data line can be significantly increased. In addition to being able to reduce, even if the data line voltage amplitude is reduced, the information retention time, the α-ray soft error resistance, and the S / N are not reduced.

Further, since the low-level potential of the data line is made higher than the potential of the word line when the word line is not selected by the maximum voltage amplitude of the output of the control circuit, the signal of the memory cell connected to the non-selected word line is not destroyed. Absent.

Further, one end of the electrode of the capacitor constituting the memory cell is divided for each word line, and the connection between the word line and the output of the voltage generation circuit is controlled by the output of the control circuit for controlling the potential of the divided electrode. By switching means,
At about the same time that the control circuit drives the other electrode of the capacitor, the corresponding word line is also selected. as a result,
The speed of the memory can be increased.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. In FIG. 1 (a), MA is a memory cell array and a plurality of data lines.
D ₀ , ▼ to D _n , ▼, word lines W _{0 to} W _m , and memory cells MC. XD selects one of a plurality of word lines by an X decoder. YD selects one of a plurality of data pairs in a Y decoder. Y ₀ conveys the output signal of the Y decoder in the data line selection signal lines. PD is a plate drive circuit which controls the one side of the terminal voltage (referred to herein as plate) P ₀ to P _m of the capacitor constituting the memory cell. Plate wiring P ₀ to P _m are arranged for each word line.
SA ₀ -SA _n amplifies the signal read from the memory cell by the sense amplifier. 1 is a signal line for transmitting the data line Purichiyaji voltage V _DP, 2 conveys Purichiyaji signal ▲ ▼ the data line Purichiyaji signal line. Reference numerals 3 and 4 denote sense amplifier drive signal lines, which are sense amplifier drive signals φ _SP and ▲, respectively.
Tell ▼ I / O and ▲ ▼ are data input / output lines for transmitting write signals to memory cells and read signals from memory cells. Here, a precharge circuit to the data input / output line is omitted. AMP is an output amplifier that amplifies a signal read from the memory cell and sets it as an output signal D _out . DiB is a circuit for converting an external input signal (write signal) into a signal level in the chip by a data input buffer. φ _W is a write control signal.

The read operation of the circuit shown in FIG. 1A will be described with reference to the operation waveforms shown in FIG. FIG. 1B shows an example of the voltage value of each waveform for ease of description.

The data line precharge signal ▼ is at a high potential, here 4 V, while the data lines D ₀ , （(D _n , ▼) are at the precharge potential, here 1 V. At this time, the sense amplifier drive signals φ _SP and ▲ ▼ are 1V,
The sense amplifier is off. The word line is selected after ▲ ▼ has reached a low potential, here 0V. Word line
It is assumed that W ₀ is selected. When W ₀ goes from low potential (0 V) to high potential (4 V), a memory cell signal appears on each data line. Here, it is assumed that a high-potential signal is accumulated in each of the memory cells connected to the data lines D ₀ and D _n . Therefore, the potential of the data line D ₀ (D _n ) becomes slightly higher than ▲ ▼ (▲ ▼). Next, φ _SP changes from 1V to 2V, ▲ ▼
When changes to 0V from 1V, to amplify the memory cell signal sense amplifier SA ₀ -SA _n is operated. As a result, the data line D ₀ is set to 2 V
▲ ▼ becomes 0V. Thereafter, 1 is set by the Y decoder YD.
A pair of data lines is selected. Here, it is assumed that D ₀ and ▲ ▼ are selected. The potential of the but connexion data line selection signal lines Y ₀ is a high potential (4V), and the data input and output line I / O, ▲
The memory cell signal is read at ▼. This signal is amplified by the output amplifier AMP and becomes an output signal D _out . Next, an operation of rewriting a signal to a memory cell will be described. After the sense amplifier is operated, the potential of the storage terminal 10 is a side terminal of the capacitor constituting the memory cell is the same potential as the D ₀ 2V
(When the terminal 10 is at a high potential in FIG. 1B). At this time, the potential of the plate P ₀ is changed to 0V from 4V, the potential of the word line W ₀ is because it is 4V data line, the potential of the storage terminal is by connexion held in the sense amplifier. Then the potential of the word line W ₀ is decreased from 4V to 2V. Here, assuming that the threshold voltage of the transistor constituting the memory cell is 1 V, at this time, the potential of the storage terminal 10 is 2 V, and the potential of the data line D ₀ is 2 V, so that the transistor T ₀ is turned off. It was but connexion, then the potential of the plate P ₀ is the potential of the storage terminal 10 replaces 4V from 0V to rise to approximately 6V from 2V.
As a result, almost 6 V is written to the memory cell. On the other hand, when a low-potential signal is stored in the memory cell, the following operation is performed. The operation will be described with reference to an operation waveform when the terminal 10 in FIG. 1B is at a low potential. Data lines D ₀ after the sense amplifier is operated is 0V, the storage terminal 10 is also summer and 0V. After the go-between, but this, 2V potential of the word line W ₀ is from 4V
The transistor T ₀ constituting the memory cell is
ON state. Therefore, the potential of the plate P0 is then ₀ V
, The potential of the storage terminal 10 is maintained at 0 V by the sense amplifier. As a result, 0 V is written to the memory cell.

Next, the word line W ₀ is re-writing to 0V next to the memory cells is completed. Thereafter, φ _SP and ▲ ▼ become 1V. Also, ▲ ▼ becomes 4V and the data line is precharged to 1V.

Next, the write operation will be described with reference to the operation waveforms of FIG. After the memory cell signal is amplified by the sense amplifier in the same manner as in the read operation, the write signal D _in (not shown in FIG. 1C) is incorporated into the data input buffer. Next, when the write control signal φ _W (not shown in FIG. 1 (c)) becomes 4V, the data input / output line I / O,
High potential potential of in accordance with the D _in, divided into low potential. Here, it is assumed that I / O becomes 0V and ▲ ▼ becomes 2V. Thereafter, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ have been selected. The While connexion data line selection signal lines Y ₀ becomes 4V. This changes ▲ ▼ to 2
V and D ₀ become 0 V, and the storage terminal 10 of the memory cell
0V is written (operation waveform when the terminal 10 is at a high potential). On the other hand, the operation of writing a high potential to a memory cell storing a low potential is performed as follows. D ₀ after the sense amplifier is operated is 0V, ▲ ▼ is 2V and summer. I / O, ▲
▼'s potential is by D _in each 2V, to 0V. Then Y ₀ becomes 4V
Rose to, D ₀ is 2V, ▲ ▼ is 2V is written in the storage terminal 10 becomes 0V, the memory cell (operation waveform when the terminal 10 is a low potential).

The operation after the signal is written to the memory cell as described above is the same as the read operation. That is, among the signals of the memory cells, those having a high potential are boosted and stored at approximately 6V, and those having a low potential are stored at 0V.

As described above, according to the present embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Accordingly, by reducing the voltage amplitude of the data line related to the power consumption of the memory and increasing the voltage amplitude of the plate related to the memory cell signal, the power consumption and the S / N of the memory can be reduced. In this embodiment, the voltage amplitude of the plate is larger than the voltage amplitude of the data line. In this way, most of the memory cell signal can be written from the plate, so that the voltage amplitude of the data line can be reduced to near the operating limit of the sense amplifier. As a result, power consumption can be significantly reduced while sufficiently securing the signal voltage of the memory cell.

In this embodiment, the potential of the data line at the time of precharging is set between the high potential and the low potential of the voltage amplitude of the data line. This can further reduce power consumption. Note that the voltage amplitude of the data line is the MOS-F that constitutes the sense amplifier.
N-MOS Tr and P-MOS that make up the sense amplifier can be reduced to near the threshold voltage of ET, but considering the stability of operation.
It is better to be slightly larger than the sum of the absolute values of the threshold voltages of the Trs. Here, the threshold voltages of N-MOSTr and P-MOSTr are set to 0.7
V, −0.7V, and if the data line voltage amplitude is 2V, 5V
The charge / discharge current can be reduced to 1 / 2.5 compared to the case of the amplitude. It is possible to increase the power consumption by driving the plate.However, when considering an array of 256 word lines × 1024 data pairs, the data line capacity that is charged and discharged at one time is
The plate capacity is 2-3 pF, whereas 200-300 pF, and can be ignored.

As described above, according to the present embodiment, the voltage amplitude of the data line can be reduced while securing the write voltage to the memory cell, so that both low power consumption and high S / N of the memory can be achieved.

As shown in FIGS. 1 (b) and 1 (c), when the potential of the plate is set at a potential between two kinds of storage potentials of the memory cell during standby of the memory, the potential of the capacitor constituting the memory cell is reduced. The applied electric field becomes smaller. Therefore, the reliability of the capacitor is improved.

In this embodiment, the signal stored in the memory cell is higher on the high potential side than on the low potential side. To increase the information retention time and the margin for α-ray soft error, it is necessary to increase the memory cell signal on the high potential side. Therefore, according to the present embodiment, a memory having a large margin can be obtained.

Another embodiment of the present invention will be described with reference to FIG. In the present embodiment, the voltage amplitude of the data line and the voltage amplitude of the plate are the same. Other operations and circuit configurations are the same as those of the embodiment shown in FIG. 2A shows a read operation of the memory, and FIG. 2B shows a write operation. In this embodiment, the voltage amplitude of the data line and the voltage amplitude of the plate are set to be the same, and the potential of the plate is set to an intermediate potential between the two kinds of storage potentials of the memory cell during standby of the memory. As a result, the voltage applied to the capacitor of the memory cell becomes the same when the potential stored in the memory cell is high and low, and the reliability of the capacitor can be improved.

FIG. 3 shows an embodiment of a memory cell configuration in which a plate wiring is provided for each word line. In the figure, (a) shows an equivalent circuit, and (b) shows a planar structure. Conventional memory cell configurations include: I, S, S, C, C 86, Digest, Ob, Technical, Paper, page 263 (ISS
CC86, Digest of Technical Papers P263) and Eye, S, S, S, C, Sea 85, Digest, Ob, Technical Papers, p. 245 (ISSCC85, Digest of Technical Papers)
Papers P245). In a memory cell array using these memory cells, the blade is not separated for each word line. FIG. 3 (b) shows a plate in which the plate is separated for each word line based on the conventional memory cell. In the figure, reference numeral 1 denotes an n ⁺ diffusion layer serving as a source (drain) terminal of a transistor constituting a memory cell, which is connected to a data line via four through holes. Here, data lines are not shown to avoid complicating the drawing. The data lines are arranged perpendicular to the word lines in, for example, the AL layer. 2
Is a plate formed of a first polysilicon layer and is separated corresponding to each word line as shown in FIG. The portion 5 is a capacitor portion. Reference numeral 3 denotes a word line formed of a second polysilicon layer, and reference numeral 6 denotes a transistor portion.
As is apparent from the memory cell configuration shown in FIG. 3, if a plate wiring is provided for each word line, a space is required between the plate wirings and the chip size becomes large. Next, a method of sharing a plate wiring with a plurality of word lines will be described.

Another embodiment of the present invention will be described with reference to FIG. 4th
The memory configuration shown in FIG. 1A is the same as that shown in FIG. 1A except that the configuration of the plate wiring is different. First
The same reference numerals as those in FIG.

In the embodiment shown in FIG. 1, a plate wiring is provided for each word line. However, in this embodiment, one plate wiring is shared by two word lines.

The read operation of the circuit shown in FIG. 4A will be described with reference to the operation waveforms shown in FIG.

While the data line precharge signal ▼ (not shown in FIG. 4B) is at a high potential, the data lines D ₀ , ▼
(D _n , ▲ ▼) is precharged to 4V. At this time, the sense amplifier drive signals φ _SP and ▲ ▼ are at 4 V, and the sense amplifier is in the OFF state. ▲ ▼ is 0
After going to V, the word line is selected. Here, it is assumed that the word line W ₀ is selected. W ₀ is the memory cell signal appears on the data line to become 7V from 0V. Here is the data line
It is assumed that a high-potential signal is stored in each of the memory cells connected to D ₀ and D _n . Accordingly, the potentials of D ₀ and D _n are slightly higher than ▲ ▼ and ▲ ▼. Next, when φ _SP changes from 4 V to 5 V and ▲ changes from 4 V to 3 V, the sense amplifiers SA _{0 to} SA _n operate to amplify the memory cell signal. Thus, the data lines D ₀ is 5V, ▲ ▼ it becomes 3V. Thereafter, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ are selected. Accordingly, the data line selection signal line Y ₀ (not shown in FIG. 4 (b))
Becomes high potential, and the data input / output line I / O,
The memory cell signal is read out as shown in FIG. This signal is amplified by the output amplifier AMP and becomes an output signal D _out (not shown in FIG. 4B). Next, an operation of rewriting a signal to a memory cell will be described. When the sense amplifier to operate D ₀ is of high potential 5V, ▲ ▼ is summer to the low potential 3V. At this time, the storage terminal 10 of the memory cell is
The potential is 5 V, which is the same high potential as D ₀ (when the terminal 10 is at a high potential in FIG. 4B). Next, the plate P ₀ ′ changes from 6V to 3V, but does not change because the potentials of the data line and the storage terminal are held by the sense amplifier. Then the potential of the word line W ₀ is reduced from 7V to 5V. Here, assuming that the threshold voltage of the transistor constituting the memory cell is 1 V, the accumulation terminal 10
Is 5 V and the data line D ₀ is 5 V, so that the transistor T ₀
Is turned off. Therefore, the plate P ₀ ′ is then set to 3V
When the voltage changes from 5V to 6V, the potential of the storage terminal 10 increases from 5V to almost 8V. As a result, a high potential of approximately 8 V is written to the memory cell. On the other hand, when a low-potential signal is stored in the memory cell, the following operation is performed. This will be described with reference to an operation waveform when the terminal 10 in FIG. 4B is at a low potential. Data lines D ₀ after the sense amplifier is operating is at a low potential
3V and the storage terminal 10 are also at 3V. It was but connexion, transistor T ₀ that constitutes the memory cell the potential of the word line W ₀ After this is reduced from 7V to 5V is ON state. Therefore, the potential of the storage terminal 10 is maintained at 3 V by the sense amplifier even when the plate P ₀ ′ changes from 3 V to 6 V next time. As a result, the low potential of 3 V is written into the memory cell again. In this embodiment, the potential of the plate of the memory cell connected to the unselected word line also changes. Next will be described the behavior of the storage terminal 11 of the memory cells connected to the unselected word lines W _1. First, the operation when a high potential is written to the storage terminal 11 is as follows. Standby, plate
P ₀ ′ is 6 V, and the storage terminal 11 is 8 V. After P ₀ ′ becomes 3 V after the sense amplifier amplifies the memory cell signal, the storage terminal 11 becomes 5 V. At this time, the word line W ₁ is 0V, the data line ▲
▼ transistor T ₁ is never signal in the memory cell not be turned ON is destroyed because the 3V or 5V. Thereafter, P ₀ ′ becomes 6V, and the potential of the storage terminal 11 returns to 8V. The operation when a low potential is written to the storage terminal 11 is as follows. During standby, pret P ₀ ′ is 6V,
The storage terminal 11 is at 3V. After the sense amplifier amplifies the memory cell signal, when P ₀ ′ becomes 3V, the storage terminal 11 becomes 0V
Becomes At this time, the word line W ₁ is 0V, the data line ▲ ▼ is 3V
Or not the signal in the memory cell never transistor T ₁ is turned ON is destroyed since the 5V.
Thereafter, P ₀ ′ becomes 6V, and the potential of the storage terminal 11 returns to 3V.

Next, the word line W ₀ is re-writing to 0V next to the memory cells is completed. After that, φ _SP and ▲ ▼ become 4V. In addition, ▲ ▼ becomes high potential and the data line is precharged to 4V.

Next, the write operation will be described with reference to the operation waveforms of FIG. After amplifying memory cell signals in the sense amplifier in the same manner as the read operation, a write signal D _in is taken into the data input buffer. Next, the write control signal φ
When _{W (in} Fig. 4 (c) not shown) becomes a high potential, the high potential data input line in response to D _in, divided into a low potential. Here, it is assumed that I / O becomes 3V and ▲ ▼ becomes 5V. Thereafter, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ have been selected. The While connexion data line selection signal lines Y ₀ is 6V. This makes ▲
▼ becomes 5 V, D ₀ becomes 3 V, and a low potential of 3 V is written to the storage terminal 10 of the memory cell (operation waveform when the terminal 10 is at a high potential). On the other hand, the operation of writing a high potential to a memory cell storing a low potential is performed as follows. D ₀ after the sense amplifier is operated is 3V, ▲ ▼ is summer and 5V. I / O, ▲
▼ potential is by D _in each 5V, to 3V. afterwards
Y ₀ becomes 6V, D ₀ becomes 5V, and ▲ ▼ becomes 3V. Therefore, 5 V is written to the storage terminal 10 of the memory cell (operation waveform when the terminal 10 is at a low potential).

The operation after the signal is written to the memory cell as described above is the same as the read operation. That is, of the memory cell signals, the high potential signal is boosted and stored at approximately 8V, and the low potential signal is stored at 3V.

As described above, in this embodiment, the data line voltage amplitude during the operation of the cancel amplifier is reduced, so that the data line charge / discharge current can be reduced and the power consumption can be reduced. Further, since a sufficient voltage is written to the memory cell by writing from the plate, the information retention time and the α-ray soft error resistance can be improved. Further, since one plate wiring is shared by two word lines, the space between the plate wirings is reduced, and the chip size can be reduced. As shown in this embodiment, when a plate wiring is shared by a plurality of word lines,
If the low potential of the data line is higher than the low potential of the word line by at least the plate voltage amplitude, the signal of the memory cell connected to the unselected word line will not be destroyed.

Another embodiment of the present invention will be described with reference to FIG. In the present embodiment, the voltage amplitude of the data line and the voltage amplitude of the plate are the same. Other operations and circuit configurations are the same as those of the embodiment shown in FIG. FIG. 5A shows a memory read operation, and FIG. 5B shows a write operation. In the present embodiment, the voltage amplitude of the data line and the electric amplitude of the plate are set to be the same, and the potential of the plate is set to an intermediate potential between the two types of storage potentials of the memory cell during standby of the memory. As a result, the voltage applied to the capacitor of the memory cell becomes the same when the potential stored in the memory cell is high and low, and the reliability of the capacitor can be improved.

FIG. 6 shows an embodiment of the memory cell configuration in the case where one plate wiring is shared by two word lines. In the figure, reference numeral 1 denotes an n ⁺ diffusion layer serving as a source (drain) terminal of a transistor constituting a memory cell, which is connected to a data line via a through hole 4. Here, the data lines are not shown to avoid complicating the drawing. Data line is for example AL
The layers are arranged perpendicular to the word lines. Reference numeral 2 denotes a plate wiring formed of the first polysilicon layer, which is shared by two word lines as shown in FIG. Reference numeral 3 denotes a word line formed of the second polysilicon layer. By sharing one plate wiring with two word lines as shown in this embodiment, the number of spaces between the plate wirings can be reduced, and the chip size can be reduced.

FIG. 7 shows an embodiment of a memory cell configuration in which one word line is shared by four word lines. According to this embodiment, the number of spaces between the plate wirings can be further reduced, and the chip size can be reduced.

FIG. 8 shows one sub-array (for example, 128 word lines,
This is an embodiment in which plate wiring is shared by 512 pairs of data lines). In the figure, a special wiring area is provided at the end of the sub-array. If a low-resistance metal wiring is passed through this region in parallel with the word line and connected to the first polysilicon layer of the plate wiring, the resistance of the plate wiring can be reduced. Thereby, the response speed in the plate wiring can be increased.

FIG. 9 shows an embodiment of a memory cell configuration in which a plate wiring is provided for each word line. In the figure, reference numeral 1 denotes a source (drain) terminal of a transistor constituting a memory cell.
The n ⁺ diffusion layer is connected to the data line through the through hole 4. Also in this embodiment, data lines are omitted in order not to complicate the drawing. Note that the data lines are arranged perpendicular to the word lines as in the embodiment described above. Reference numeral 2 denotes a plate wiring formed of the first polysilicon layer, which is separated for each word line. 3 is a word line formed of the second polysilicon layer. In the case of this memory cell configuration, two data line configurations are possible. One is an open type data line (bit line) configuration, and the other is a return type data line (bit line) configuration. FIG. 9 (b) shows an open data line configuration in which adjacent data lines are connected to different sense amplifiers. FIG. 9 (c) shows a flip-back data line configuration in which adjacent data lines are connected to the same sense amplifier. In this case, when one word line is selected, a memory cell connected to each paired data line is selected. That is, a memory cell array configuration of 1 bit 1/2 cell is obtained. Therefore, the memory cell signal appearing on the data line is 1
It is possible to obtain twice as many signals as a bit / cell memory cell array.

Another embodiment of the present invention will be described with reference to FIG. No.
FIG. 10 is an operation waveform showing another driving method of the plate wiring of the memory circuit shown in FIG. 4 (a). The operation shown in FIG. 10 is the same as the embodiment shown in FIG. 5 in the read operation until the output signal D _out is output, and the rewrite operation is different. The rewriting operation is performed as follows. When the sense amplifier operates, D ₀
Indicates a high potential of 4V, and ▲ ▼ indicates a low potential of 2V. Storage terminal 10 in this case the memory cell is 4V of the same high potential as the D ₀ (if terminal 10 is a high potential in Figure 10). Then word line
Potential of W ₀ is reduced from 5V to 4V. Here, assuming that the threshold voltage of the transistor constituting the memory cell is 1 V, the storage terminal 10 is at 4 V and the data line D ₀ is at 4 V, so that the transistor T ₀ is in the OFF state. Therefore, the plate
When P ₀ ′ changes from 2V to 4V, the potential of the storage terminal 10 increases from 4V to almost 6V. On the other hand, when a low-potential signal is stored in the memory cell, D ₀ after the sense amplifier operates.
Is 2V and the storage terminal 10 is 2V, so the word line is 4V
The transistor that is composed of memory cells
T ₀ is in the ON state. Therefore, even if P ₀ ′ changes from 2 V to 4 V, the potential of the storage terminal is maintained at 2 V by the sense amplifier. Then after word line W ₀ has decreased to 0V, the plate P ₀ 'is changed from 4V to 2V. As a result, the potential of the storage terminal of the memory cell changes from approximately 6 V to 4 V when a high potential is stored, and from 2 V to 0 V when a low potential is stored.
Therefore, the memory cell has 4 V on the high potential side and 4 V on the low potential side.
The potential of 0 V will be accumulated. Next, unselected word line
The behavior of the storage terminal 11 of the memory cells connected to W ₁ will be described. When a high potential is written to the storage terminal 11, the plate P ₀ ′ is at 2V and the storage terminal 11 is at 4V during standby. After the sense amplifier amplifies the memory cell signal, P ₀ ′
Becomes 4V, the storage terminal 11 becomes almost 6V. afterwards,
P ₀ ′ becomes 2V, and the potential of the storage terminal 11 returns to 4V. During this time the word lines W ₁ to 0V, since the data lines ▲ ▼ is summer and 2V or not the transistor T ₁ is turned ON, no signal in the memory cell is destroyed. When a low potential is written to the storage terminal 11, the plate P ₀ ′
Is 2V and the storage terminal 11 is 0V. After the sense amplifier amplifies the memory cell signal, when P ₀ ′ becomes 4V, the storage terminal
11 is almost 2V. Thereafter, P ₀ ′ becomes 2V, and the potential of the storage terminal 11 returns to 0V. During this time, the word line W ₁ is 0V, the data line ▲ ▼ the transistor T ₁ is ON so that more and summer 2V
No state occurs, and no signal in the memory cell is destroyed.

As described above, also in this embodiment, since the data line voltage amplitude can be reduced, power consumption can be reduced. In the case of this embodiment, the memory cell signal on the low potential side can be made larger than the memory cell signal on the high potential side.

Another embodiment of the present invention will be described with reference to FIG. No.
FIG. 11 shows a connection relationship between a data line and a data input / output line in the memory circuit, and other circuit configurations are shown in FIG.
Is the same as the circuit shown in FIG. The circuit of FIG. 11 includes data lines D ₀ ,
▲ ▼ The above signal is received by the gate of MOS-FET, T ₂ , T ₃ ,
Using that as the drain current, the data I / O line I / O, ▲
▼ To increase the signal to transmit to the data output line is important to use T _2, T ₃ with a large area of g _m. In the embodiment shown in FIG. 4 T _2, T ₃ since the high potential of the data line can be increased signal it would operate at a large area of g _m. Therefore, in a memory operated by increasing the potential of the data line, the use of the circuit method of this embodiment can achieve a high S / N.

 Another embodiment of the present invention will be described with reference to FIG. Real truth
In this embodiment, the voltage of the word line is binary. Other than this
The operation and circuit configuration are the same as those of the embodiment shown in FIG.
You. While the data line precharge signal ▲ ▼ is 4V,
The line is precharged to 1V. ▲ ▼ became 0V
Later, word line W₀Is 2V + V_t(V_tIs the threshold voltage of the MOS-FET
To rise. This allows the memory cell signal to be read on the data line.
Is spilled out. Next, the sense amplifier drive signal φ_SPFrom 1V to 2
V and ▲ ▼ change from 1V to 0V, increasing the memory cell signal
Width. In this case, the word line W₀Memory cells that lead to
If a high-potential signal is stored, the data line D
₀(D_n) Is 2V, ▲ ▼ (▲ ▼) becomes 0V. this
Hour, word line W₀Potential is 2V + V_t, Data line D₀Is 2V, note
Since the storage terminal 10 of the recell becomes 2 V, it constitutes a memory cell.
Transistor T₀Becomes OFF. Then plate P₀Potential of
Decreases from 4V to 0V, the potential of the terminal 10 slightly decreases,
The above transistor T₀Turns ON, and the 2V potential at terminal 10 is
Held by the sense amplifier. Then plate P₀No electricity
When the voltage rises from 0V to 4V, the transistor T₀Is off
As a result, the potential of the terminal 10 rises to approximately 6V. Meanwhile, memory
The operation when a low-potential signal is stored in the cell is as follows.
(The waveform when the terminal 10 is at a low potential in FIG. 12).
After the memory cell signal is amplified by the sense amplifier, the data line
D₀Is 0 V, the storage terminal 10 of the memory cell is 0 V, the word line W₀Is 2V
+ V_tTransistors that make up memory cells
T₀Turns ON. Therefore, plate P₀Potential of
Even if the voltage changes from 4V to 0V or from 0V to 4V,
The position holds 0V. As described above, the signal is applied to the memory cell.
Is accumulated, the word line W₀Becomes 0V. And then
▲ ▼ is 4V, φ_SP, ▲ ▼ becomes 1V, data line
Is precharged to 1V.

As described above, according to this embodiment, the word line voltage is 2
The same operation as the embodiment shown in FIG. 1 can be performed with the value. Accordingly, the word line voltage control circuit is simplified, and the design is facilitated.

Another embodiment of the present invention will be described with reference to FIG. This embodiment is different from the embodiment shown in FIG. 1 in that dummy word lines WD ₀ , WD ₁
Is different. Other circuit configurations and operations are the same as those of the embodiment shown in FIG. In the embodiment shown in FIG.
The signal (memory cell signal) when the memory cell signal is read to the data line with the word line at a high potential is higher when the high potential is stored in the memory cell than when the low potential is stored in the memory cell. It becomes bigger. Therefore, in this embodiment, the difference is reduced. For example, the word lines W ₀ is selected and Natsuta to a high potential. In this case, data line D
_A memory cell signal appears at ₀ (D _n ). At this time, the high potential of the dummy word line WD ₀ from the low potential. As a result, the potential of the data line ▲ ▼ (▲ ▼) serving as a reference signal slightly increases. As a result, when a high potential is stored in the memory cell, the memory cell signal is equivalently reduced, and when a low potential is stored, the signal is increased. Therefore, the difference between the memory cell signal when the high potential is stored and the memory cell signal when the low potential is stored can be reduced. As a result, noise merge can be averaged, and S / N can be improved. Incidentally, when the word line W _m is selected, the dummy word line WD ₁ is made from a low potential to a high potential.

FIG. 14 is an example of a circuit for generating the sense amplifier drive signal φ _SP , ▲ ▼. A ₁ in the figure by a differential amplifier circuit, determines the high potential of the transistor T _211, resistor R _211, V _r1 with phi _SP. A ₂ in the differential amplifier circuit, the transistors T _212, resistor
Determine the low potential of ▲ ▼ together with R ₂₁₂ and V _r2 . The operation of this circuit will be described with reference to the operation waveform of FIG. While the signal ▲ ▼ is 5V, the transistors T ₂₆₁ , T ₂₆₂ ,
T ₂₆₃ is turned ON and φ _SP and ▲ ▼ are set to 3V. At this time, the signal phi ₂ is 5V, phi ₃ the transistor T _22, T ₂₄ in 0V is
OFF. ▲ ▼ After has decreased to 0V, φ ₂ is 0V, φ ₃
Becomes 5V. As a result, φ _SP has the same potential as V _r1 of 4 V,
▲ ▼ is the 2V of the same potential as the V _r2. Then φ ₂ is 5
V, phi ₃ to 0V transistor T _22, T ₂₄ is turned OFF.
Next, ▲ ▼ becomes 5V, and the transistors T ₂₆₁ , T ₂₆₂ , T
₂₆₃ turns ON, and φ _SP and ▲ ▼ are set to 3V.

As described above, in this circuit, the high potential of φ _SP and the low potential of ▲ ▼ can be arbitrarily determined by changing the magnitudes of V _r1 and V _r2 .

FIG. 15 is an example of a word line voltage generation circuit. In the figure
33 is a word line, 36 is an X decoder, and 34 is an address signal line. A ₃ is a differential amplifier circuit, which includes a transistor T ₃₀ and a resistor
Together with R _30, V _r3 are determined an intermediate potential of the word line voltage. The operation of this circuit will be described with reference to the operation waveform of FIG. When the memory is on standby, the output terminal 35 of the X decoder is at a high potential of 5V. At this time, the signal phi ₄ is a low potential
It is 0V. Therefore, transistors T ₃₁₁ and T ₃₅₂
Is ON, T ₃₁₂ and T ₃₅₁ are OFF, and the word line is at 0V.
Thereafter the word line W ₀ is selected terminal 35 becomes 0V. Thus the transistor T ₃₅₁ is ON, T ₃₅₂ is the voltage of the turned OFF, the word line is raised to 5V. Then φ ₄ and is 5V,
Transistor T ₃₁₁ is OFF, next T ₃₁₂ is ON, the voltage of the word line is the same 4V and V _r3. After that, the potential of terminal 35 becomes 5V
Then, the word line voltage becomes 0V.

As described above, the ternary level of the word line voltage can be produced by the circuit as shown in FIG.

One embodiment of the present invention will be described with reference to FIG. In FIG. 16A, MA is a memory cell array, and a plurality of data lines D ₀ ,
▲, 〜D _n , ▼, word lines W _{0 to} W _m , dummy word lines ▼, ▼, plate wires P _{0 to} P _m, and memory cells MC. XD selects one of a plurality of word lines by an X decoder. YD selects one of a plurality of data pair lines by a Y decoder. Y ₀ to Y _n conveys the output signal of the Y decoder in the data line selection signal lines. PD is a plate drive circuit which controls the one side of the terminal voltage (referred to herein as plate) P ₀ to P _m of the capacitor constituting the memory cell. This circuit also selects one of a plurality of plate lines according to an address signal, similarly to the X decoder.
SA _{0 to} SA _n are sense amplifiers, which are configured as a circuit as shown in FIG. 16 (b), and amplify signals read from the memory cells. In this embodiment, the transistor with an arrow is a P-channel MOSFET (P-MOSFET), and the transistor without an arrow is an N-channel MOSFET (N-MOSFET). 1 is a signal line for transmitting the data line Purichiyaji voltage V _dP. Reference numeral 2 denotes a data line precharge signal line for transmitting a precharge signal ▲. Reference numerals 3 and 4 denote sense amplifier drive signal lines for transmitting sense amplifier drive signals φ _SP and ▲ ▼, respectively. I / O, ▲
▼ denotes a data input / output line for transmitting a write signal to the memory cell and a read signal from the memory cell. In addition,
Although not shown here, FIG. 16 (c) shows data input / output lines.
The precharge circuit IOP and the bias circuit IOB shown in FIG. AMP is an output amplifier that amplifies the signal read from the memory cell and sets it as an output signal D _out . _Dib is a data input buffer for converting an external input signal (write signal) into a signal level in the chip. φ _w is the write control signal.

The reading operation of the circuit shown in FIG. 16A will be described with reference to the operation waveforms shown in FIG. Fig. 16 (d)
Here, for ease of explanation, an example of the voltage value of each waveform is shown.

While the data line precharge signal ▲ ▼ is 4V, the data lines D ₀ , ▲ ▼ (D _n , ▲ ▼) are at the precharge potential,
It is 1V. At this time, the sense amplifier drive signal φ _SP , ▲
▼ is 1 V, and the sense amplifier is in the OFF state. ▲ ▼ it is after has decreased to 0V, and the plurality of plate signal line, and P ₀ is selected. When P ₀ is changed to 0V from 4V, the memory cell signal appears on the data lines. Here the memory cells connected to the data lines D ₀ and the signal 0V of low potential is accumulated. When P ₀ changes from 4V to 0V, 0V of the memory cell decreases toward −4V. At this time the word line
Since W ₀ is 0 V, when the amount of decrease exceeds the threshold voltage of the MOS-FET, the storage terminal 10 of the memory cell is connected to the data line. Thus current flows from the data line to the memory cell, the memory cell signal appears on the data line D _0. At this time,
The dummy word line ▲ ▼ changes from 4V to 0V. As a result, a reference signal appears on the data line ▲ ▼. In addition,
If the signal 6V high potential is accumulated in the storage terminal 10, the potential of 10 becomes 2V by the voltage change of the P _0. This does not change the potential of the data line for the transistor T ₀ in the memory cell is in the OFF state when.

Now, the memory cell signal to the data lines, after the reference signal appears, the 2V phi _SP from 1V, ▲ ▼ is changed to 0V from 1V. Thus the sense amplifier SA ₀ -SA _n operates to amplify the memory cell signal. Therefore, the data line D ₀ is set to 0 V,
▲ ▼ becomes 2V. Thereafter, the word line W0 changes from ₀ V to 4 V, and 0 V (2 V in the case of high potential reading) is written to the memory cell. Next, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ have been selected. The While 4V potential of connexion data line selection signal lines Y ₀
And the memory cell signal is read out to the data input / output line I / O, ▲ ▼. This signal is amplified by the output amplifier AMP and becomes an output signal D _out . Next, the word line W ₀ from 4V
Reduce to 2V. The plate P ₀ after this to 4V from 0V.
Transistor T ₀ that constitutes the memory cell because of low potential 0V is written in this case the memory cell is in the ON state. Therefore, the voltage 0V of the memory cell does not change. The transistor T ₀ if 2V high potential is written into the memory cell is in the OFF state. Therefore, the potential of the memory cell is 2V
To 6V. Then word line W ₀ is to write to the memory cell to 0V to the end. Also, the dummy word line ▲
▼ changes from 0V to 4V. Next, φ _SP and ▲ ▼
1V, ▲ ▼ becomes 4V, and the data line is precharged to 1V.

Next, a write operation to the memory cell will be described using operation waveforms shown in FIG. After amplifying memory cell signals in the sense amplifier in the same manner as read operation, the write signal D _in is taken into the data input buffer. Next, when the write control signal phi _w is 4V, the data input and output lines I /
O, ▲ ▼ of potential is in accordance with the D _in high-potential, divided into low potential. Here, it is assumed that I / O becomes 2V and ▲ ▼ becomes 0V. Thereafter, a pair of data lines is selected by the Y decoder YD. Here, the D _{0, 0} is selected. The While connexion data line selection signal lines Y ₀ becomes 4V. D ₀ is 2V, ▲
▼ becomes 0V and the high potential 2V is applied to the storage terminal 10 of the memory cell.
Is written (operation waveform when the terminal 10 is at a low potential).
On the other hand, an operation of writing a low potential to a memory cell storing a high potential is performed as follows. D ₀ after the sense amplifier operates
Is 2V and ▲ ▼ is 0V. I / O, ▲ ▼ potentials are respectively 0V, 2V by D _in. Then Y ₀ is increased to 4V, D ₀ is 0V, ▲ ▼ is 0V is written to the storage terminal 10 of 2V, and the memory cells (operation waveform when the terminal 10 is high potential).

The operation after the signal is written in the memory cell as described above is the same as the read operation. That is, of the memory cell signals, those with high potential are boosted and accumulated at 6V, and those with low potential are accumulated at 0V.

As described above, according to the present embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Accordingly, the voltage amplitude of the plate for determining the voltage of the high potential signal of the memory cell related to the information retention time of the memory cell is increased, and the voltage amplitude of the data line related to the power consumption of the memory (the voltage during the sense amplifier operation). Voltage amplitude)
Can be reduced. In this embodiment, the voltage amplitude of the data line is smaller than the voltage amplitude of the plate. As a result, the power consumption can be significantly reduced while sufficiently securing the signal voltage of the memory cell. Therefore, both low power consumption and high S / N of the memory can be achieved. In this embodiment, the potential of the data line at the time of precharging is set to an intermediate value between the high potential side and the low potential side of the voltage amplitude of the data line. This can further reduce power consumption. The voltage amplitude of this data line can be reduced to the sum of the absolute values of the threshold voltages of the N-NOS transistor and the P-MOS transistor constituting the sense amplifier. Since the threshold voltage is usually 0.5V to 1V, if the voltage amplitude of the data line is 2V, the charging / discharging current is smaller than that of 5V amplitude.
It can be reduced to 1 / 2.5. Further, in the present embodiment are read out signal from the memory cell by a 0V plate P ₀ from 4V. Normally, when a signal line is driven by a MOSFET, the discharging operation is faster than the charging operation.
Accordingly, the speed of the read operation from the memory cell can be increased as compared with the read operation of changing the word line from a low potential to a high potential.

FIG. 17 shows an embodiment of the word line drive circuit. In the figure
MA is a memory cell array, D ₀ , ▲ ▼ are data lines,
W ₀ and W _m are word lines, and P ₀ and P _m are plates. WD is an intermediate potential setting circuit of the word line, the differential amplifier A _20, the transistor T _60, resistors R _60, sets the intermediate value of the word line voltage with the reference voltage V _r10. The operation of this circuit will be described with reference to the operation waveform of FIG. During memory standby, signal φ ₂₀
Is 0 V, φ ₂₁ is 4 V, and the plate drive signals φ _P10 and φ _Plm are 4 _V. Therefore, the transistors T ₆₁₁ , T ₆₃ , T ₆₅
Is ON, T ₆₁₂ , T _p63 , T _p65 are OFF, and the word lines W ₀ , W _m
Is 0V and the terminal 64 is 4V. After that, the signal φ ₂₁ becomes 0V
Thus, the transistors T ₆₃ and T ₆₅ are turned off. Next, φ _pl0
Becomes 0V, the transistor _Tp63 turns on and the word line
Voltage of W ₀ is to 4V. Next, when the signal phi ₂₀ is 4V, the transistor T ₆₁₁ is OFF, T ₆₁₂ is turned ON. This allows
Voltage at terminal 64 and word line W ₀ becomes 2V. Then, φ
_Pl0 becomes 4V, then phi ₂₁ is the voltage of the word line W ₀ comes to 4V becomes 0V.

As described above, according to the present embodiment, a word line can be selected by selecting a plate.
The word line selection circuit becomes unnecessary. Further, since the plate and the word line can be selected almost simultaneously, the speed of the memory can be increased.

Another embodiment of the present invention will be described with reference to FIG. This memory circuit is the same as the circuit shown in FIG. 16 (a) except that it has 2 cells / bit and that there is no dummy word line. Since there are 2 cells / bit, a memory cell signal is read out simultaneously to each pair of data lines. Since these two signals are always in a complementary relationship, a dummy cell is not required. The operation of this circuit will be described with reference to the operation waveform of FIG.

While the data line precharge signal ▼ is 4 V, the data lines D ₀ , （(D _n , ▼) are precharged to 1 V. At this time, the sense amplifier drive signal φ _SP , ▲
▼ is 1 V, and the sense amplifiers SA _{0 to} SA _n are in the OFF state. Then, the plate P ₀ becomes 0V from the selected 4V. Thus the signal of the memory cells connected to P ₀ is read out to the data lines. For example, the storage terminal of a memory cell
Suppose that a high potential of 6 V is stored in 10 and a low potential of 0 V is stored in 11. When the plate P ₀ changes from 4V to 0V, the potential of the terminal 10 becomes 6V
To 2V. At this time, the data line D ₀ is 1 V, and the word line W ₀ is
Since 0V and has summer transistor T ₀₁ is the voltage of is the data line D ₀ is OFF does not change. On the other hand, the potential of the terminal 11 decreases from 0 V to −4 V. At this time, the data lines ▲ ▼
1V, the word lines W ₀ is the potential of the terminal 11 is lower than the threshold voltage V _t of the MOSFET transistor T ₀₂ is turned ON, and One unsuitable data line ▲ from ▼ to terminal 11 current flows because at 0V. This slightly lowers the potential of the data line ▲ ▼. This means that the memory cell signal has been read out to both the data lines D ₀ and ▲ ▼. Next, 2V sense amplifier driving signal phi _SP from 1V, ▲ ▼ becomes 0V from 1V, the sense amplifier operates, D ₀ to 2V, ▲ ▼ becomes 0V. Then, the voltage of the word line W ₀ becomes 4V, 2V is the accumulation terminal 10 of the memory cell, 0V is rewritten to 11.
Thereafter, the data lines D ₀ and ▲ are selected by the Y decoder YD, and the data line selection signal line Y ₀ is set to 4V. Thereby, the memory cell signal is read out to the data input / output line I / O, ▲ ▼. This signal is amplified by the output amplifier AMP and becomes an output signal D _out . After this, the potential of the word line W ₀ is reduced to 2V. At this time, the potential of the data line D ₀ is 2V, ▲ ▼ is potential 0V, the potential the potential of 2V, 11 of the storage terminal 10 of the memory cell transistor T ₀₁ because it is 0V OFF, T ₀₂ is turned ON . Then, when the plate P ₀ is increased to 4V from 0V, the potential of the storage terminal 10 of the memory cell is approximately 6V, 11 the potential 0V
Hold. Thereafter, the potential of the word line becomes 0 V, and the writing to the memory cell ends. Therefore, when about 6 V is written to the storage terminal 10 of the memory cell and 0 V is written again to 11, the data line precharge signal
4V, the sense amplifier drive signal φ _SP becomes 1V, and ▲ ▼ becomes 1V, and the data line is precharged to 1V.

Next, a write operation to the memory cell will be described using operation waveforms shown in FIG. In the same manner as the read operation, after amplifying memory cell signals in the sense amplifier, a write signal D _in is taken into the data input buffer. Next, when the write control signal phi _w is 4V, the data input and output lines I / O, ▲ ▼ potentials in response to D _in, divided high potential, a low potential. Here, it is assumed that I / O becomes 0V and ▲ ▼ becomes 2V. Thereafter, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ have been selected. Accordance connexion, the data line selection signal lines Y ₀ is 4V. Thus D ₀ is 0V, ▲ ▼ it becomes 2V, the storage terminal 10 of the memory cell 2V is written 0V is the accumulation terminal 11. The subsequent operation is the same as the reading operation. That is, the potential of the storage terminal 11 of the memory cell is boosted to 6 V, and the storage of the potential of 10 is kept at 0 V.

As described above, also in this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, the data line charge / discharge current can be reduced,
The power consumption of the memory can be reduced. The decrease in the write voltage to the memory cell due to the reduction in the data line voltage amplitude is compensated by writing from the plate. Accordingly, the information retention time and the α-ray soft error resistance can be improved. Since the present embodiment uses the configuration of 2 bits / cell, the read signal of the memory cell is doubled as compared with 1 bit / cell, and a high S / N can be achieved. Further, a dummy cell becomes unnecessary.

Another embodiment of the present invention will be described with reference to FIG. This circuit differs from the circuit shown in FIG. 16A in that a bipolar transistor is used to read a memory cell signal from a data line. Accordingly, two types of data input / output lines are provided: a signal reading wiring O and a signal writing wiring I. Here, only the relationship between the data lines and the data input / output lines is shown, but the other circuit configuration is the same as that shown in FIG. 16 (a). The operation of this circuit uses a bipolar transistor to read out the memory cell signal.
It is the same as that shown in FIG. The reading operation of this circuit will be described with reference to the operation waveform of FIG. 19 (b).

Assuming that the forward voltage between the base and the emitter of the bipolar transistor is VBE, the data line precharge signal ▲
While ▼ is 4V, the data line D, is precharged to 2 · VBE. At this time, the sense amplifier drive signal φ _SP , ▲
▼ indicates 2 · VBE, and the sense amplifier is in the OFF state. Next, the plate P changes from 4V to 0V, and the signal of the memory cell is read out to the data line. It is assumed that low potential VBE has been stored in the storage terminal 10 of the memory cell. When the plate P changes from 4V to 0V, the potential of the terminal 10 decreases from VBE toward − (4-VBE). At this time, since the data line D is 2 · VBE and the word line W is 0 V, the terminal 10
When the potential of lower than -V _t transistor T constituting a memory cell current flows One unsuitable turned ON, the data line D to the terminal 10. As a result, a memory cell signal is read out to the data line D. On the other hand, at this time, the dummy word line ▲
▼ changes from 4V to 0V, and a reference signal appears on the data line. Here, for the sake of simplicity, only the dummy word line is shown, but the actual memory is also provided for D. Also, a high potential 3 · VBE is applied to the storage terminal 10 of the memory cell.
When +4 V is stored, when P changes from 4 V to 0 V, the potential of the terminal 10 becomes 3 · VBE. At this time, the data line D is 2
Since VBE and the word line W are at 0 V, the transistor T is OFF and the potential of the data line D does not change. Now, after the memory cell signal and the reference signal appear on the data line, the sense amplifier drive signal φ _SP is changed from 2 · VBE to 3 · VBE.
▲ ▼ changes from VBE to VBE. As a result, the sense amplifier operates, and D becomes VBE and becomes 3 · VBE.
Next, the potential of the word line W becomes 4 V, and VBE is written to the terminal 10 again. Thereafter, Y _r of the data line selection signal lines 4V
, And the memory cell signal on the data line is read out to the signal readout wiring O, via the bipolar transistor. This signal is amplified by the output amplifier and the output signal D _out
Becomes Thereafter, the potential of the word line W drops to 3 · VBE. At this time, the potential of the data line D is VBE, and the potential of the terminal 10 is also VBE.
Since it is BE, the transistor T is in the ON state, and the potential of the terminal 10 does not change with VBE even when the plate P changes from 0V to 4V. When a high-potential signal is stored in the memory cell, when the potential of the word line becomes 3 · VBE, the potential of the data line D is 3 · VBE and the potential of the terminal 10 is 3 · VBE.
Therefore, when the transistor T is turned off and the plate P changes from 0V to 4V, the potential of the terminal 10 becomes 3 · VBE + 4V
To rise. Thereafter, the potential of the word line becomes 0 V, and the writing to the memory cell ends. Also, the dummy word line ▲
▼ changes from 0V to 4V. Thereafter, the data line Purichiyaji signal ▲ ▼ is 4V, the sense amplifier driving signal φ _SP is 2 ·
VBE and ▲ ▼ become 2 · VBE, and the data line is precharged to 2 · VBE.

Next, a write operation to the memory cell will be described using operation waveforms shown in FIG. In the same manner as the read operation, after amplifying memory cell signals in the sense amplifier, a write signal D _in is taken into the data input buffer. In accordance with this signal, the potential of the signal writing wiring I, is divided into a high potential and a low potential. Here, I is 3 · VBE and VBE
Let's say Thereafter, the data line selection signal lines Y _w becomes 4V by Y decoder YD. This gives D 3 · VBE,
Becomes VBE, and 3 · VBE is written to the terminal 10. The subsequent operation is the same as the reading operation. That is, the potential of the storage terminal 10 of the memory cell is boosted to 3 · VBE + 4V and stored.

As described above, also in this embodiment, since the data line voltage amplitude can be reduced while securing a sufficient memory cell signal, the power consumption of the memory can be reduced. Further, in this embodiment, since the potential of the data line is determined based on the forward voltage between the base and the emitter of the bipolar transistor, it becomes easy to design a memory LSI in which MOSFETs and bipolar transistors are mixed.

Another embodiment of the present invention will be described with reference to FIG. This embodiment is another operation example of the circuit shown in FIG. This embodiment shows operation waveforms when a signal of a write command from the outside of the chip is input to the chip with a considerable delay with respect to the address strobe signal. This embodiment is different from the operation waveform shown in FIG. 4C in that the storage terminal of the memory cell is boosted twice by a plate. Others are 4th
This is the same as the operation waveform in FIG. Note that in FIG.
▼ is a row (X) address strobe signal, ▲
▼ is a column (Y) address strobe signal, and ▲ is a write command signal.

The operation from the reading of the memory cell signal to the boosting by the plate of the storage terminal is the same as the operation shown in FIG. In this embodiment, after the voltage is boosted by the plate, the signal changes from a high potential to a low potential, and a write operation is performed.
As a result, the potential of the word line W ₀ is increased to again 7V. On the other hand, the data line selection signal lines Y ₀ is changed to 6V from 0V, through the data input and output lines, the data lines D _0, ▲ ▼ the signal is written. Here, it is 3V, ▲ ▼ to 5V is written into D _0. As a result, 3 V is written to the storage terminal 10 of the memory cell. Next, the plate P ₀ ′ changes again from 6V to 3V. Storage terminal for the potential of this time word line W ₀ is 7V
The potential of 10 is held by the sense amplifier. Then word line
Potential of W ₀ is reduced to 5V. Next, plate P ₀ ′ is changed from 3V to 6V
Changes to In this case, the potential of the word line W ₀ is 5 V and the potential of the data line D ₀ is 3 V, so that the transistor T ₀ constituting the memory cell is in the ON state, and the potential 3 V of the storage terminal 10 is held by the sense amplifier. . Incidentally, if the 5V high potential is written to the storage terminal 10, the transistor T ₀ is turned OFF by the potential of the word line W ₀ is to 5V. Accordingly, when the plate P ₀ ′ changes from 3 V to 6 V, the potential of the storage terminal 10 rises from 5 V to almost 8 V (when the terminal 10 is at a low potential in FIG. 20). Potential of the word line W ₀ After the above operation is 0V and the write signal to the memory cells is completed. Thereafter, the data lines D ₀ and ▲ ▼ are precharged to 4V. Φ _SP and ▲ ▼ also become 4V.

As described above, according to the present embodiment, the voltage amplitude of the data line can be reduced even in the operation mode in which the write command is almost input, so that the power consumption can be reduced.

Another embodiment of the present invention will be described with reference to FIG. 21st
The operation waveforms in the figure differ from the operation waveforms in FIG. 20 in that the voltage waveform of the word line is binary, and are otherwise the same.
When the potential of the word line is binary, as shown in the embodiment of FIG. 12, the potential on the high potential side is higher than the high potential of the data line by MO.
If the value is set higher by the threshold voltage of the SFET, the storage terminal can be boosted by the plate. Therefore, in this embodiment, even if a write command is input shortly, only the boosting of the storage terminal by the plate is performed again without changing the voltage of the word line. Therefore, according to the present embodiment, it is not necessary to boost the word line voltage at the time of writing, and the circuit design becomes easy.

Another embodiment of the present invention will be described with reference to FIG. In FIG. 22 (a), MA is a memory cell array, and a plurality of data lines D ₀ ,
, 〜D _n , ▼, word lines W ₀ , W _{1 to} W _m , dummy word lines WD ₀ , WD ₁ , plate wires P ₀ , P _{1 to} P _m , dummy cells DMC and memory cells MC. MC is composed of storage capacity C _S of the MOS transistor T _0. DMC is a dummy cell for generating a reference voltage and is a MOS transistor T ₃ , T ₄
To be composed of storage capacity C _SD. Reference numeral 8 denotes a signal line for writing the storage voltage DV to the dummy cell, and supplies a dummy cell write signal DC. XD is an X decoder that selects one of a plurality of word lines and a dummy word line according to an external address signal. The relationship between the word line and the dummy word line, when the word line W ₀ of the memory cell is connected to the data line D ₀ is selected and connected to the dummy cell ▲ ▼
DW ₁ is now selected. YD selects one of a plurality of data pair lines by a Y decoder. Y ₀ to Y _n conveys the output signal of the Y decoder in the data line selection signal lines. PD
Is a plate drive circuit which controls the one side of the terminal voltage (referred to herein as plate) P ₀ to P _m of the capacitor constituting the memory cell. This circuit also selects one of a plurality of plate lines according to an address signal, similarly to the X decoder. SA ₀ -SA _n is the normal sense amplifier composed of flip-flops of the P-channel MOS transistor and N-channel MOS transistor, it amplifies a signal read from the memory cell. 1 is the data line precharge voltage V
Signal line that communicates _dP . Reference numeral 2 denotes a data line precharge signal line for transmitting a precharge signal ▲. Reference numerals 3 and 4 denote sense amplifier drive signal lines, which are sense amplifier drive signals φ _SP and
Tell ▲ ▼. I / O and ▲ ▼ are data input / output lines for transmitting write signals to memory cells and read signals from memory cells. Although not shown here, a precharge circuit is provided for the data input / output line. AMP is an output amplifier that amplifies the signal read from the memory cell and sets it as an output signal D _out . _Dib is a data input buffer for converting an external input signal (write signal) into a signal level in the chip. φ _w is the write control signal.

The read operation of the circuit shown in FIG. 22A will be described with reference to the operation waveforms shown in FIG. FIG. 22 (b)
Here, for ease of explanation, an example of the voltage value of each waveform is shown. The voltage value of each waveform is not limited to this value.

While the data line precharge signal ▲ ▼ is 4V, the data lines D ₀ , ▲ ▼ (D _n , ▲ ▼) are at the precharge potential,
It is 2V _BE (1.6V). At this time, the sense amplifier drive signals φ _SP and ▲ ▼ are at 2V _BE, and the sense amplifier is in the OFF state. It is assumed that _W0 is selected from a plurality of word lines after ▲ ▼ becomes 0V. W ₀ is 5V from 0V
_{When the} signal changes to _BE (4 V), a memory cell signal appears on each data line. Here the storage terminal 10 of the memory cells connected to the data lines D ₀ to the high potential _{3V BE + 5V BE = 8V BE} (6.4V) is accumulated. If W ₀ is changed to 5V _BE (4V) from 0V, the signal voltage read corresponding to the data line capacitance C _D and the storage capacitance C _S appears on the data line D _0. The read signal amount [Delta] V _{S is, ΔV S ( '1')} = C S / (C D + C S) × V S ( '1') where, C _S: storage capacity C _D: Data line capacitance V _BE: Forward voltage between base and emitter of bipolar transistor (0.8V) V _S ('1'): Storage voltage (8V _BE -2V _BE = 6V _BE (4.8
V)) The read signal voltage ΔV _S ('0') when the low potential signal V _BE is stored in the storage terminal 10 is ΔV _S ('0') = C _S / (C _D + C _S ) × V _S ('0') V _S ('0'): Storage voltage (2V _BE -V _BE = V _BE (0.8
V)).

With such a voltage relationship, as described above, the read signal voltage greatly differs between '1' and '0'. A dummy cell is provided to eliminate this imbalance. The cell connected to the data line opposite to the memory cell is selected as the dummy cell. That is, if it is word line W ₀ selected, the dummy word line WD ₁ is selected, the data line ▲ ▼ signal voltage [Delta] V _SD read reference appears to.
The value of ΔV _SD is determined by the storage voltage of the dummy cell, that is, the voltage value of DV. Usually, the voltage value of DV is' 1 'and'
The intermediate value of 0 ', that is, 4.5V _BE (3.6V) is set. If it is desired to increase the margin on the '1' side due to the problem of α-ray soft error or refresh, the voltage value of VD may be lowered.

Now, after the memory cell signal and the reference signal appear on the data line, φ _SP changes from 2V _BE (1.6V) to 3V _BE (2.4V), and ▲
▼ changes from 2V _BE to V _BE . Thus the sense amplifier SA ₀ -SA _n operates to amplify the memory cell signal. The While connexion data lines D ₀ to 3V _BE, ▲ ▼ becomes V _BE.
Then lowered to 0V and the plate P ₀ from 5V _BE (4V). At this time, the word line voltage is 5V _BE (4V), so even if the plate voltage changes, the terminal 10 of the memory cell remains at 3V _BE (2.4V).
Data line voltage. Next, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ have been selected. It was but connexion, potential 4V next data line selection signal lines Y _0, the data input and output lines I / O, ▲ ▼ memory cell signal is read out to. This signal is amplified by the output amplifier AMP and becomes an output signal D _out . Next, the word line W ₀ 5
Reduce V _BE (4V) to 3V _BE (2.4V). The plate P ₀ after this to 5V _BE (4V) from 0V. Transistor T ₀ in the memory cell because 3V _BE high potential is written in this case the memory cell is in the OFF state. Therefore, the voltage at the terminal 10 of the memory cell is changed from 3V _BE to 3V _BE + 5V _BE (6.4
V) to rise. The transistor T ₀ if the low potential V _BE is written in the memory cell is in the ON state. Therefore, the potential of the terminal 10 of the memory cell remains at V _BE . Then word line W ₀ is to write to the memory cell to 0V to the end. Next, φ _SP , ▲ ▼ becomes 2V _BE and ▲ ▼ becomes 4V, and the data line is precharged to 2V _BE .

Next, a write operation to a memory cell will be described using operation waveforms shown in FIG. After amplifying memory cell signals in the sense amplifier in the same manner as read operation, the write signal D _in is taken into the data input buffer. Next, when the write control signal phi _w is 4V, the data input and output lines I /
O, ▲ ▼ of potential is in accordance with the D _in high-potential, divided into low potential. Here I / O is V _BE, ▲ ▼ is to Natsuta to 3V _BE. Thereafter, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ have been selected. Data line selection signal lines Y ₀ is 4V when D ₀ is V _BE, ▲
▼ becomes 3V _BE , and the low and high potential V _BE is written to the storage terminal 10 of the memory cell (operation waveform when the high potential is stored in the terminal 10 first). On the other hand, an operation of writing a high potential to a memory cell in which a low potential is stored is performed as follows. After the sense amplifier operates, D ₀ is V _BE and ▲ ▼ is 3 V
_{Be connected} with _BE . The potentials of I / O and ▲ ▼ are set to 3V _BE and V _BE respectively by D _in . Then Y ₀ rises to 4V and D ₀
Is 3V _BE , ▲ ▼ is V _BE , and the storage terminal of the memory cell
3V _BE is written to 10 (operation waveform when a low potential is stored in the terminal 10 first).

The operation after the signal is written in the memory cell as described above is the same as the read operation. That is, the high potential of the memory cell signal is boosted to 3V _BE + 5V _BE =
8V _BE (6.4V), those with low potential are stored in V _BE . Further, the dummy cell, a constant voltage DV is written by the dummy cell write signal DC via the MOS transistor T _3.

As described above, according to the present embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Accordingly, the voltage amplitude of the plate for determining the voltage of the high potential signal of the memory cell related to the information retention time of the memory cell is increased, and the voltage amplitude of the data line related to the power consumption of the memory (the voltage during the sense amplifier operation). Voltage amplitude)
Can be reduced. In this embodiment, the voltage amplitude of the data line is smaller than the voltage amplitude of the plate. As a result, the power consumption can be significantly reduced while sufficiently securing the signal voltage of the memory cell. Therefore, both low power consumption and high S / N of the memory can be achieved. In this embodiment, the potential of the data line at the time of precharging is set to an intermediate value between the high potential side and the low potential side of the voltage amplitude of the data line. This can further reduce power consumption. The voltage amplitude of this data line can be reduced to the sum of the absolute values of the threshold voltages of the N-MOS transistor and the P-MOS transistor forming the sense amplifier. Since the threshold voltage is usually 0.5 V to 1 V, if the voltage amplitude of the data line is 2 V _BE (1.6 V) V, the charge / discharge current can be reduced to about 1/3 as compared with the case of 5 V amplitude. Also,
In the present embodiment, the dummy cell is provided so that the storage voltage thereof can be freely controlled, so that the read signal amount of "1""0" can be freely controlled, which is resistant to α-ray soft error and adversely affects the refresh characteristic. Therefore, it is possible to design a memory with low power consumption. Further, in the present embodiment, since each operating voltage such as the potential of the data line is determined based on the forward voltage between the base of the bipolar transistor and the emitter, it becomes easy to design the memory LSI in which the MOSFET and the bipolar transistor are mixed.

FIG. 23 is a specific embodiment of the dummy cell write voltage DV. It comprises a bipolar transistor Q ₀ and resistors R ₁ , R ₂ and R ₃ . The voltage value DV of the terminal 21 is V _BE : expressed as the voltage between the base and emitter of Q ₀ , and the voltage value can be set freely by the resistance values of R ₂ and R ₃ .

Another embodiment of the present invention will be described using a memory circuit shown in FIG. This memory circuit is the same as the circuit shown in FIG. 22 (a) except that the plate electrode of the storage capacity of the memory cell is common for every two word lines. Since the plate electrode is shared by the two word lines, higher integration can be achieved than in the case of FIG. The operation of this circuit will be described with reference to the operation waveform of FIG.

While the data line precharge signal ▼ is 4V, the data lines D ₀ , ▲ (D _n , ▼) are precharged to 4V _BE (3.2V). At this time, the sense amplifier drive signal φ
_SP and ▲ ▼ are 4V _BE and sense amplifier SA ₀
~ SA _n is in the OFF state. After ▲ ▼ becomes 0V, the word line is selected. Here, it is assumed that the word line W ₀ is selected. Signal of the memory cells connected to W ₀ when the word line W ₀ is 5.5V from the selected 0V is read out to the data lines. Here, the memory cells connected to the word line W ₀ is both a signal of a high potential (8 _BE) is accumulated. Therefore, D ₀ and D _n contain “1” information, ▲ ▼,
At ▲ ▼, the reference voltage is read from the dummy cell.
Next, the sense amplifier drive signal φ _SP is changed from 4V _BE to 5V _BE ,
▲ ▼ becomes 3V _BE from 4V _BE, sense amplifier operates, D ₀ to 5V _BE, ▲ ▼ Thereafter be amplified 3V _BE, the data lines D ₀ of a pair by the Y decoder YD, ▲ ▼ is is selected, the data line selection signal Y ₀ is the number potential, data input and output line I / O, ▲ ▼ memory cell signal is read out to. This signal is amplified by the output AMP and the output signal D
_out and output to the outside.

Next, an operation of rewriting a signal to a memory cell will be described. By the sense amplifier D ₀ is in the high-potential 5V _BE ▲ ▼
Has a low potential of 3V _BE . The same 5V and D ₀ for storing terminal 10 at this time memory cell word lines W ₀ is high potential
_BE . Next, plate P ₀ ′ is changed from 5.5V _BE (4.4V) to 2.
Although it changes to 5V _BE (2V), the potential of the data line and the storage terminal 10 does not change because it is held at 5V _BE by the sense amplifier. Then, 5V potential of the word line W ₀ is from 5.5V
_It drops to _BE . Here, assuming that the threshold voltage of the transistor constituting the memory cell is 1 V, the storage terminal 10 has 5 V _BE ,
Since the data line D ₀ is 5 V _BE and the word line W ₀ is 5 V _BE , the transistor T ₀ is in the OFF state. Therefore, then P ₀ ′
Changes from 2.5V _BE to 5.5V _BE , the potential of the storage terminal 10 becomes 5V
_It rises from _BE to almost 8V _BE (6.4V). As a result, a high potential of approximately 8 V _BE is written to the memory cell. On the other hand, when the low potential signal of the memory cell is stored, the following operation is performed. Description will be made using operation waveforms when the terminal 10 in FIG. 24B is at a low potential. Data lines D ₀ after the sense amplifier is operated is low potential 3V _BE, and the potential of the terminal 10 also and 3V _BE summer. It was but connexion, thereafter, transistors T ₀ the potential of the word line W ₀ constitute a memory cell is also reduced from 5.5V to 5V _BE (4V) is in the ON state. Therefore, no matter how the plate P ₀ ′ changes, the potential of the storage terminal 10 is maintained at 3 V _BE because the data line potential is fixed by the sense amplifier. As a result, a low potential of 3V _BE is written into the memory cell again. In this embodiment, the potential of the memory cell connected to the unselected word line also changes. The behavior of the storage terminal 11 of the memory cells connected to the unselected word lines W ₁ will be described. First, the operation when a high potential is written to the storage terminal 11 is as follows. During standby, plate P ₀ ′ is 5.5V
_BE , the storage terminal 11 is at 8V _BE . After P ₀ ′ becomes 2.5 V _BE after the sense amplifier amplifies the memory cell signal, the storage terminal 11 becomes 5 V _BE . At this time the word lines W ₁ to 0V, information of the data line ▲ ▼ in the memory cell never transistor T ₁ is turned ON since it is 3V _BE is not adversely be destroyed. Thereafter, P ₀ ′ becomes 5.5 V _BE , and the potential of the storage terminal 11 returns to 8 V _BE . The operation when a low potential is written to the storage terminal 11 is as follows. During standby, the plate P ₀ ′ is at 5.5 V _BE and the storage terminal 11 is at 3 V _BE . After the sense amplifier amplifies the memory cell signal, P ₀ ′ becomes 2.5V
_When it comes to _BE , the area rushes and 11 becomes 0V. At this time the word line
W ₁ to 0V, data lines ▲ ▼ transistor T ₁ is never the information in the memory cell not to become ON state is destroyed since the 5V _BE. Thereafter, P ₀ ′ becomes 5.5 V _BE and the potential of the storage terminal 11 returns to 8 V _BE . Next, the word line W ₀ is set to 0
V, and the rewriting to the memory cell is completed. Thereafter, φ _SP and ▲ ▼ become 4V _BE , and ▲ ▼ becomes high potential and precharges to the data line 4V _BE .

Next, a write operation to a memory cell will be described using operation waveforms shown in FIG. First, an operation of writing a low potential to a memory cell storing a high potential will be described. In the same manner as the read operation, after amplifying memory cell signals in the sense amplifier, a write signal D _in is taken into the data input buffer. Next, the write control signal φ
_{When w} becomes a high potential, the potentials of the data input / output lines I / O and ▼ are divided into a high potential and a low potential according to D _in . Here, it is assumed that I / O is 3V _BE and ▲ ▼ is 5V _BE .
Thereafter, a pair of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and ▲ ▼ have been selected. Accordance connexion, the data line selection signal lines Y ₀ is at a high potential. This
D ₀ becomes 3V _BE and ▲ becomes 5V _BE , and the low potential 3V _BE is written to the storage terminal 10 of the memory cell. The subsequent operation is the same as the reading operation.

As described above, also in this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, the data line charge / discharge current can be reduced,
The power consumption of the memory can be reduced. The decrease in the write voltage to the memory cell due to the reduction in the data line voltage amplitude is compensated by writing from the plate. Accordingly, the information retention time and the α-ray soft error resistance can be improved. Further, in this embodiment, a dummy cell is provided so that its storage voltage can be freely controlled.
It is possible to freely control the readout signal amount of 1 "0", and it is possible to design a low power consumption memory which is resistant to α-ray soft error and has no adverse effect on the refresh characteristics. Further, in the present embodiment, since each operating voltage such as the potential of the data line is determined based on the forward voltage V _BE between the base of the bipolar transistor and the emitter, it is easy to design a memory LSI in which MOSFETs and bipolar transistors are mixed. Become.

Further, since the plate is commonly wired by the two word lines W ₀ and W ₁ , the chip area can be reduced.

〔The invention's effect〕

According to the present invention, the data line voltage amplitude during the operation of the sense amplifier can be greatly reduced compared to the conventional case, so that the data line charge / discharge current can be reduced and the power consumption in the memory cell array can be reduced.
It can be reduced to 1/2 to 1/3. In addition, by boosting a high-potential memory cell signal from the plate, the memory cell signal can be increased. Therefore, the present invention is effective in reducing the power consumption and increasing the S / N of the memory. That is, it is possible to improve the information retention time, the α-ray soft error characteristic, the noise, and the reliability.

[Brief description of the drawings]

FIG. 1 is a circuit diagram and an operation waveform diagram of one embodiment of the present invention, and FIG.
FIG. 3 is an operation waveform diagram of one embodiment of the present invention, FIG. 3 is a diagram showing a memory cell configuration of one embodiment of the present invention, FIG. 4 is a circuit diagram and operation waveform diagram of one embodiment of the present invention, 5 is an operation waveform diagram of one embodiment of the present invention, FIG. 6 is a diagram showing a memory cell configuration of one embodiment of the present invention, FIG. 7 is a diagram showing a memory cell configuration of one embodiment of the present invention, FIG. 8 is a diagram showing a memory cell configuration of one embodiment of the present invention, FIG. 9 is a diagram showing a memory cell configuration of one embodiment of the present invention, and FIG. 10 is an operation waveform diagram of one embodiment of the present invention. FIG. 11 is a circuit diagram of one embodiment of the present invention, FIG. 12 is an operation waveform diagram of one embodiment of the present invention, FIG. 13 is a circuit diagram of one embodiment of the present invention, and FIG. FIG. 15 is a circuit diagram and operation waveform diagram of one embodiment of the present invention, FIG. 16 is a circuit diagram and operation waveform diagram of one embodiment of the present invention,
FIG. 17 is a circuit diagram and an operation waveform diagram of one embodiment of the present invention, and FIG.
FIG. 19 is a circuit diagram and operation waveform diagram of one embodiment of the present invention, FIG. 19 is a circuit diagram and operation waveform diagram of one embodiment of the present invention, FIG. 20 is an operation waveform diagram of one embodiment of the present invention, FIG. 21 is an operation waveform diagram of one embodiment of the present invention, FIG. 22 is a circuit diagram and operation waveform diagram of one embodiment of the present invention, FIG. 23 is a circuit diagram of one embodiment of the present invention, and FIG. FIG. 2 is a circuit diagram and an operation waveform diagram of one embodiment of the present invention. MA: memory cell array, XD: X decoder, YD: Y
Decoder, PD ...... plate drive circuit, AMP ...... output amplifier, DiB ...... data input buffer, P _0, P _m ...... plate _{wiring, D 0, ▲ ▼, D} n, ▲ ▼ ...... data line, W ₀ ,
W _m ... word line.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-25882 (JP, A) JP-A-56-14091 (JP, A) Eto et al., "Proposal of low-voltage operation method for DRAM" Proceedings of the National Meeting of Spring Meeting (1989) C-360 (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/407

Claims (7)

(57) [Claims] A plurality of data line pairs; a plurality of word lines arranged to intersect with the plurality of data line pairs; and a plurality of data line pairs arranged at intersections of the plurality of word lines. A switching unit whose on / off is controlled by a voltage of a corresponding word line of the plurality of word lines, and one electrode of the switching unit is connected to a corresponding data line of the plurality of data line pairs via the switching unit; A plurality of memory cells having a plurality of capacitors, a control circuit for controlling the potential of the other electrode of each capacitor of the plurality of memory cells, and a plurality of sense circuits provided for each of the plurality of data line pairs. And a maximum amplitude of the control circuit is larger than a maximum potential difference between the plurality of data line pairs. The potential difference between the corresponding data line pair at the time of amplification is slightly larger than the sum of the absolute values of the respective threshold voltages of the N-type MOS transistor and the P-type MOS transistor constituting the sense amplifier. During the standby period during the read / write operation to the plurality of memory cells, the potential of each data line of the plurality of data line pairs is substantially intermediate between the low level potential and the high level potential of the plurality of data lines. A memory circuit having a potential. 2. The memory circuit according to claim 1, wherein a potential difference between a corresponding pair of data lines when amplified by said plurality of sense amplifiers is 2V. A plurality of data lines, a plurality of word lines arranged to intersect with the plurality of data lines, and an intersection of the plurality of data lines and the plurality of word lines;
Switching means, each of which is turned on / off by a voltage of a corresponding word line of the plurality of word lines, and one electrode thereof is connected to a corresponding data line of the plurality of data lines via the switching means. A plurality of memory cells having a capacitor, a control circuit for controlling the potential of the other electrode of each capacitor of the plurality of memory cells,
A memory circuit having a plurality of sense amplifiers for amplifying a signal read out to each of the plurality of data lines to a first potential or a second potential lower than the first potential; The memory circuit according to claim 1, wherein the second potential is higher than a potential when the plurality of word lines are not selected by a maximum voltage amplitude of an output of the control circuit. 4. The method according to claim 3, wherein an absolute value of a difference between said first potential and said second potential is 2V.
The memory circuit according to the paragraph. 5. An apparatus according to claim 3, wherein an absolute value of a difference between said first potential and said second potential is smaller than a maximum voltage amplitude of an output of said control circuit. The memory circuit according to any one of the above items. 6. The semiconductor device according to claim 3, further comprising a precharge circuit for supplying a substantially intermediate potential between said first potential and said second potential to said plurality of data lines. The memory circuit according to any one of the above items. 7. A plurality of data lines, a plurality of wort lines arranged so as to intersect with the plurality of data lines, and an intersection point between the plurality of data lines and the plurality of hood lines,
Switching means, each of which is turned on / off by a voltage of a corresponding word line of the plurality of word lines, and one electrode thereof is connected to a corresponding data line of the plurality of data lines via the switching means. A plurality of memory cells having a capacitor, and the other electrode of each capacitor of the plurality of memory cells is divided for each word line of the plurality of word lines, and the potential of the other divided electrode is selected. In a memory circuit having a control circuit for controlling a word line, a voltage generation circuit, and a plurality of connections between an output of the voltage generation circuit and the plurality of word lines controlled by an output of the control circuit A memory circuit, further comprising: switching means.