JPH023161A - Memory circuit - Google Patents

Abstract

PURPOSE:To broadly reduce a data line charging/discharging current and to improve information holding time, an alpha rays resistant sift error property and an S/N by reducing a data line voltage amplitude on memory cell signal amplifying. CONSTITUTION:A memory cell array MA of a memory circuit consists of plural D0, the inverse of D0-Dn and the onverse of Dn, word lines W0-Wn and a memory cell MC. Besides, the plural word lines and the one of data lines are selected with X and Y decoders XD and YD, a signal read out of the memory cell MC is amplified with sense amplifiers SA0-SAn. Besides, while a data line precharging signal the inverse of phiP is 4V at a high electric potential, it becomes 1V at a data line precharging electric potential. Then, sense amplifier driving signals phiSF and the inverse of phiSn become 4V, the sense amplifier becomes an off condition, the inverse of phiP becomes a low electric potential and the word line is selected. Besides, the electric potential difference between the data lines is lowered to a value which is a little larger than the threshold voltage of an MOS-FET constituting the sense amplifier, the electric potential of the inner high electric potential of a memory cell signal is selected and pressure is raised with a terminal to which the MOS-FET for transfer gate is not connected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit that simultaneously satisfies lower power consumption and higher S/N of a MOS-DRAM.

[Conventional technology]

A conventional DRAM circuit includes a memory array (memory cell matrix) consisting of a plurality of memory cells for storing signals, and an X decoder for selecting one of the plurality of memory cells, as described in Japanese Patent Publication No. 61-61479.

It consists of a Y decoder, a sense amplifier that amplifies the signal read out from the memory cell, etc. A memory cell matrix consists of bit lines (data lines), word lines provided to intersect with the bit lines, and memory cells provided at the intersections of the word lines. A memory cell consists of one MOS-FET and one capacitor, and the drain terminal of the MOS-FET is connected to a data line, the source terminal to one end of the capacitor, and the gate terminal to a word line. Writing signals to memory cells in these circuits is carried out as follows.
The word line voltage is set to a high potential, and the signal stored in the memory cell (hereinafter referred to as a memory cell signal) is read out to the data line. The read signal is amplified by a sense amplifier, and the paired data lines are set to high potential and low potential. This voltage is written into the selected memory cell again, and the same signal is written into the memory cell again. After that, the potential of the selected word line is slightly lowered from the high potential. The amount of decrease in this potential is such that the transfer gate (MOS-FET) of the memory cell into which a high potential has been written is turned off.

After this, the MOS-F of the capacitor that constitutes the memory cell is
The potential of the terminal not connected to the source terminal of ET is changed from low potential to high potential.

As a result, the potential of the high potential among the memory cell signals is further increased. On the other hand, those with low potential do not change because their potential is held by the sense amplifier. Therefore, the amount of signals stored in the memory cell can be increased, and a high S/N ratio can be achieved.

In recent years, as memories have become more highly integrated, the number of data lines that are charged and discharged at once has increased, and the resulting increase in power consumption has become a problem. However, the above memory circuit did not take these points into consideration.

[Problem to be solved by the invention]

The above conventional technology arises as memory becomes highly integrated.
No consideration was given to increasing power consumption, resulting in a decrease in memory information retention time and an increase in noise.

There were problems such as a decline in reliability.

One way to counter the increase in power consumption is to lower the voltage used by memory. However, the voltage accumulated in the memory cell cannot be lowered unnecessarily due to information retention time and resistance to α-ray soft errors. Therefore, the voltage used in the memory cannot be lowered much, and it is difficult to significantly reduce power consumption.

An object of the present invention is to significantly reduce power consumption while ensuring sufficient storage voltage in memory cells.

[Means to solve the problem]

The above purpose is to amplify the memory cell signal in the sense amplifier.
In addition to lowering the potential difference between paired data lines (hereinafter abbreviated as data line voltage amplitude) to a value slightly larger than the threshold voltage of the MOS-FET that constitutes the sense amplifier, This is achieved by boosting the potential of the object using a terminal that is not connected to the transfer gate MO8-FET of the capacitor that constitutes the memory cell.

[Effect]

By reducing the data line voltage amplitude during memory cell signal amplification, data line charging 1! Current can be significantly reduced, and power consumption can be reduced.

By reducing the data line voltage amplitude, the voltage written into the memory cell from the data line becomes smaller, but by boosting the voltage from one end of the capacitor that constitutes the memory cell, the memory cell signal can be increased. Therefore, information retention time, α-ray soft error resistance, and S/N ratio can be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In Figure (a), MA is a memory cell array, which is composed of a plurality of data lines D o HD o"' D n HD n , a word line W o = W-, and a memory cell MC.X
D selects one of a plurality of word lines by an X decoder. YD is a Y decoder that selects one of a plurality of data pairs. Yo is a data line selection signal line that transmits the output signal of the Y decoder. PD is the terminal on one side of the capacitor that makes up the memory cell (referred to as a plate here) P o
-P is a plate drive circuit that controls the voltage of m. A plate wiring P o ''P - is arranged for each word line.SAo''SAn is a sense amplifier that amplifies a signal read from a memory cell. 1 is a signal line that transmits a data line precharge voltage Vop, and 2 is a data line precharge signal line that transmits a precharge signal φP. 3 and 4 are sense amplifier drive signal lines, each of which receives a sense amplifier drive signal φ.
Tell spy φSN. Ilo and Ilo are data input/output lines that transmit write signals to memory cells and read signals from memory cells. Note that a precharge circuit for the data input/output line is omitted here. AMP is an output amplifier that amplifies the signal read from the memory cell and outputs it as an output signal Dout. DiB is a data input puffer that converts an external input signal (write signal) to a signal level within the chip. φW is a write control signal.

Figure 1(b) shows the readout operation of the circuit shown in Figure 1(a).
This will be explained using the operating waveform shown in FIG. In addition, Fig. 1(b)
In order to facilitate the explanation, an example of the voltage value of each waveform is shown.

Data line precharge signal φP is at high potential, here 4V
During this time, the data lines Do and Do (Dn, DIl) are at a precharge potential, which is 1V here.

At this time, the sense amplifier drive signals φsp and φSN are at 1V, and the sense amplifier is in an OFF state.

After φP goes to a low potential, here Ov, a word line is selected. Assume that word line Wo is selected. When Wo goes from a low potential (Ov) to a high potential (4V), a memory cell signal appears on each data line.

Here, it is assumed that high-potential signals are stored in the memory cells connected to the data lines Do and Dn. Therefore, the potential of the data line Do (Dn) increases.

The zero-order φsp, which is slightly higher than (Dn), is 1 to 2 V.
Then, when φsN changes from 1v to Ov, the sense amplifier SAo''SA operates and amplifies the memory cell signal.As a result, the data line Do becomes 2v and D.

becomes Ov. After that, a pair of data lines is selected by Y decoder YD. Here, it is assumed that Do and Do are selected. Therefore, the potential of the data line selection signal line Yo becomes a high potential (4V), and the data input/output lines I10. A memory cell signal is read to I10. This signal is output amplifier A
The output signal is amplified by MP. The rewriting operation of the signal to the 6th order memory cell, which is ut, will be explained. After the sense amplifier operates, the potential of the storage terminal 10, which is one terminal of the capacitor constituting the memory cell, is 2V, which is the same potential as Do (when the terminal 10 is at a high potential in FIG. 1(b)). , at this time, the potential of the plate Po changes from 4v to O
However, since the potential of the word line Wo is 4V, the potentials of the data line and storage terminal are held by the sense amplifier. Thereafter, the potential of the word line Wo decreases from 4v to 2v. Here, if the threshold voltage of the transistor constituting the memory cell is 1V, then the potential of the storage terminal 10 is 2V and the potential of the data line Do is 2V, so the transistor To is in the OFF state. Therefore, next time the potential of the plate Po changes from Ov to 4V, the potential of the W product terminal 10 increases from 2V to approximately 6V. This causes approximately 6V to be written into the memory cell. On the other hand, when a low potential signal is stored in the memory cell, the following operation occurs. This will be explained using operation waveforms when the terminal 10 in FIG. 1(b) is at a low potential. After the sense amplifier operates, the data line Do becomes ov, and the i product terminal 10 also becomes Ov. Therefore, after this, the potential of the word line Wo is 4
Even when the voltage drops from v to 2v, the transistor TO forming the memory cell remains in the ON state. Therefore, even if the potential of the plate PO changes from Ov to 4V next time, the potential of the storage terminal 10 is maintained at Ov by the sense amplifier. As a result, Ov is written into the memory cell.

Next, the word line Wo becomes Ov, and rewriting to the memory cell is completed. After that, φSPI φ8N becomes 1v.

Further, 77 becomes 4V and precharges the data line to 1V.

Next, the write operation will be explained using the operation waveforms shown in FIG. 1(c). After the memory cell signal is amplified by the sense amplifier in the same manner as the read operation, the write signal Dt, , (first
When the primary write control signal φW (not shown in FIG. 1C) becomes 4V, the data input/output line I10.
The potential of I10 is Dt. It is divided into high potential and low potential depending on the voltage. Here, it is assumed that Ilo becomes OV and Ilo becomes 2v.

After that, a pair of data lines is selected by Y decoder YD. Here, it is assumed that Do and Do are selected.

Therefore, the data line selection signal line YO becomes 4V.

As a result, Do becomes 2V and Do becomes Ov, and a low potential Ov is written to the storage terminal 10 of the memory cell (operating waveform when the terminal 10 is at a high potential).

On the other hand, the operation of writing a high potential into a memory cell in which N low potentials are multiplied is performed as follows. After the sense amplifier operates
o is OV, and Do is 2v.

The potentials of Ilo and Ilo are 2v and O, respectively, due to D + n.
It is made into V. After that, Yo rose to 4■, DO became 2V,
Do becomes Ov, and 2V is applied to the storage terminal 10 of the memory cell.
is written (operating waveform when terminal 10 is at low potential)
.

The operation after a signal is written into the memory cell as described above is the same as the read operation. That is, among the signals of the memory cells, those at high potential are boosted and stored at approximately 6V, and those at low potential are stored at Ov.

As described above, according to this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, by reducing the voltage amplitude of the data line, which is related to the power consumption of the memory, and increasing the voltage amplitude of the plate, which is related to the memory cell signal, the power consumption of the memory can be reduced and the S/N ratio can be increased. In this case, the voltage amplitude of the plate is made larger than that of the data line. In this way, most of the memory cell signals can be written from the plate, so the voltage amplitude of the data line can be reduced to near the operating limit of the sense amplifier. This makes it possible to significantly reduce power consumption while ensuring a sufficient signal voltage for the memory cells.

Further, in this embodiment, the potential at the time of precharging the data line is set between the high potential and the low potential of the voltage amplitude of the data line. This allows power consumption to be further reduced. Note that the voltage amplitude of the data line is determined by the MOS-
Although it can be reduced to near the threshold voltage of FET, considering the stability of operation, the N-MOSTr that constitutes the sense amplifier
It is preferable that the voltage is slightly larger than the sum of the absolute values of the threshold voltages of the p-MOSTr and the p-MOSTr. Here, N-MOSTr, P-M O
Assuming that the threshold voltages of STr are 0.7V, -0, and 7V, respectively, and the data line voltage amplitude is 2V, the charging/discharging current can be reduced to 1/2.5 compared to the case of 5V amplitude. . Note that driving the plate may increase power consumption, but when considering an array of 256 word lines x 1024 data pairs, the data line capacitance that is charged and discharged at - degrees is 200 to 300 pF, whereas the plate drive The capacitance is 2 to 3 pF and can be ignored.

As described above, according to this embodiment, it is possible to reduce the voltage amplitude of the data line while ensuring the write voltage to the memory cell, thereby achieving both low power consumption and high S/N of the memory.

As shown in Figures 1(b) and 1(c), if the potential of the plate is set to a potential between the two types of storage potential of the memory cell when the memory is on standby, the capacitor that makes up the memory cell will The applied electric field becomes smaller. Therefore, reliability of the capacitor is improved.

In this embodiment, the signal stored in the memory cell is larger on the high potential side than on the low potential side.

In order to increase the information retention time and the margin against α-ray soft errors, it is necessary to increase the memory cell signal on the high potential side. Therefore, according to this embodiment, a memory with a large margin can be obtained.

Another embodiment of the present invention will be described with reference to FIG.

In this embodiment, the voltage amplitude of the data line and the voltage amplitude of the plate are made the same. Other operations and circuit configurations are the same as the embodiment shown in FIG.

2(a) shows the read operation of the memory, and FIG. 2(b) shows the write operation. In this embodiment, the voltage amplitude of the data line and the voltage amplitude of the plate are made the same, and the potential of the plate is set to The potential is set to be an intermediate potential between the two types of storage potential of the cell. As a result, the voltage applied to the capacitor of the memory cell is the same whether the potential stored in the memory cell is high or low, and the reliability of the capacitor can be improved.

FIG. 3 shows an example of a memory cell configuration in which a plate wiring is provided for each word line. In the same figure, (a) is the equivalent circuit,
(b) shows the planar structure. Conventional memory cell configurations include eye, varnish, and varnish.

See, see 86. Digest, of, technical,
Paper, page 263 (ISSCC86, Digest
ofTechnical Papers P263)
Yaai, varnish, varnish, sea, sea 85. Digest of Technical Paper, page 245 (ISSCC
85, Digest of Technical Pap
ers P245). In a memory cell array using these memory cells, the plates are not separated for each word line. FIG. 3(b) shows an example in which the plates are separated for each word line based on the above-mentioned conventional memory cell. In the figure, numeral 1 is a diffusion layer serving as a source (drain) terminal of a transistor constituting a memory cell, and is connected to a data line via a through hole 4. Data lines are not shown here to avoid complicating the drawing. The data lines are arranged perpendicularly to the word lines, for example in the AL layer. Reference numeral 2 denotes a plate formed of a first polysilicon layer, which is separated corresponding to each word line as shown in the figure. 5
The part marked with is the capacitor part. 3 is a word line formed of the second polysilicon layer, and a portion 6 is a transistor section. As is clear from the memory cell configuration shown in FIG. 3, if a plate wiring is provided for each word line, a space is required between the plate wirings, which increases the chip size.

Next, a method in which a plate wiring is shared by a plurality of word lines will be described.

Another embodiment of the present invention will be described with reference to FIG.

The memory configuration shown in FIG. 4(a) is the same as that shown in FIG. 1(a) except for the configuration of the plate wiring.

The same reference numerals as in FIG. 1(a) indicate the same parts.

In the embodiment shown in FIG. 1, a plate wiring was provided for each word line, but in this embodiment, two word lines share one plate wiring.

Figure 4(b) shows the readout operation of the circuit shown in Figure 4(a).
This will be explained using the operating waveform shown in FIG.

While the data line precharge signal n (not shown in FIG. 4(b)) is at a high potential, the data line Do.

Do (D,, Dn) is precharged to 4V.

At this time, the sense amplifier drive signals φSP and φSN are at 4V, and the sense amplifier is in an OFF state. φP
After becomes Ov, the word line is selected. Here, it is assumed that the word WWo is selected.

When Wo goes from Ov to 7V, a memory cell signal appears on each data line. Here, the data line Do.

Assume that high potential signals are stored in all memory cells connected to D. Therefore, Do.

0th order φsP where the potential of Dn is slightly higher than Do, D
When φsN changes from 4v to 5v and from 4v to 3v, sense amplifiers 5Ao-8AI operate and amplify the memory cell signal. As a result, the data line Do is 5V, Do
becomes 3v. After that, a pair of data lines is selected by Y decoder YD. Here, it is assumed that Do and Do are selected. Therefore, data line selection signal line Yo (fourth
(not shown in FIG. 4(b)) becomes a high potential, and memory cell signals are read out to data input/output lines I10 and l10 (not shown in FIG. 4(b)). This signal is amplified by the output amplifier AMP, and the output signal D out
(not shown in FIG. 4(b)) The rewriting operation of the signal to the primary memory cell will be explained. When the sense amplifier operates, Do becomes a high potential of 5V, D.

is at a low potential of 3V. At this time, the storage terminal 10 of the memory cell becomes 5V, the same high potential as Do (Fig. 4(b)
) and the terminal 10 is at a high potential) the primary plate Pa'
changes from 6v to 3v, but the potentials of the data line and W contact terminal do not change because they are held by the sense amplifier.Then, the potential of the word line Wo decreases from 7v to 5v. Assuming that the threshold voltage of the transistor constituting the memory cell is 1V, the storage terminal 10 is 5V and the data line Do is 5V, so the transistor To is OFF.
state. Therefore, next plate Po' is 3
When the voltage changes from V to 6V, the potential at the storage terminal 10 rises from 5V to approximately 8V. This gives approximately 8V to the memory cell.
A high potential will be written. On the other hand, when a low potential signal is stored in the memory cell, the following operation occurs. This will be explained using operation waveforms when the terminal 10 in FIG. 4(b) is at a low potential. After the sense amplifier operates, the data line Do is at a low potential of 3V, and the storage terminal 10 is also at 3V. Therefore, even if the potential of the word line Wo decreases from 7v to 5v after this, the transistor To forming the memory cell remains in the ON state. Therefore, then plate Po
Even if ' changes from 3V to 6V, the potential of the storage terminal 10 is maintained at 3V by the sense amplifier. As a result, a low potential of 3V is written into the memory cell again.

Now, in this embodiment, the potential of the plate of the memory cell connected to the unselected word line changes as well.
The behavior of the storage terminal 11 of the memory cell connected to 1 will be explained. First, the operation when a high potential is written to the storage terminal 11 is as follows. During standby, plate Po
is 6V, and the M connection terminal 11 is 8V. After the sense amplifier amplifies the memory cell signal, Po' becomes 3v.
Then, the voltage at the storage terminal 11 becomes 5V. At this time, word line W
1 is Ov, and the data line Do is 3v or 5v, so the transistor T1 is never turned on and the signal in the memory cell is not destroyed.

After that, Po' becomes 6V, and the potential of the storage terminal 11 returns to 8V. The operation when a low potential is written to the storage terminal 11 is as follows. When on standby, preto Po'
is 6V, and the W contact terminal 11 is 3V 4C.

After the sense amplifier amplifies the memory cell signal, Po'
When becomes 3V, the storage terminal 11 becomes Ov. At this time, the word tiA W 1 is Ov and the data line Do is 3V or 5V, so the transistor TI is not turned on and the signal in the memory cell is not destroyed.

After that, Pa' becomes 6V, and the potential of the storage terminal 11 returns to 3V.

Next, the word line Wo becomes ov, and rewriting to the memory cell is completed. After that, φSP and φSN become 4v. Further, φP becomes a high potential and precharges the data line to 4V.

Next, the write operation will be explained using the operation waveforms shown in FIG. 4(c). After the memory cell signal is amplified by the sense amplifier in the same way as the read operation, the write signal D1n is taken into the data input buffer.

Next, when the write control signal φW (not shown in FIG. 4(c)) becomes a high potential, the data input/output line is divided into a high potential and a low potential depending on D In. Here Ilo is 3v
, Ilo becomes 5V.

After that, a pair of data lines is selected by Y decoder YD. Here, it is assumed that Do and Do are selected.

Therefore, the data line selection signal line YO becomes 6■.

As a result, Do becomes 5V and Do becomes 3V, and a low potential of 3V is written to the storage terminal 10 of the memory cell (operating waveform when the terminal 10 is at a high potential).

On the other hand, the operation of writing a high potential into a memory cell in which a low potential has been stored is performed as follows. After the sense amplifier operates
o is 3V, and Do is 5V.

The potentials of Ilo and Ilo are 5V and 3V, respectively, due to [)tn.
be made into After that, YO becomes 6V, Do becomes 5V, Do
becomes 3v. Therefore, the storage terminal 10 of the memory cell
5V is written to (operating waveform when @child 10 is at a low potential).

The operation after a signal is written into the memory cell as described above is the same as the read operation. That is, among the memory cell signals, those with high potential are boosted and stored at approximately 8V, and those with low potential are stored at 3V.

As described above, in this embodiment, since the data line voltage amplitude during scan amplifier operation is reduced, the data line charging/discharging current can be reduced and power consumption can be reduced.

Further, since a sufficient voltage is written into the memory cell by writing from the plate, information retention time and α-ray soft error resistance characteristics can be improved. Furthermore, since one plate wiring is shared by two word lines, the space between the plate wirings is reduced, and the chip size can be reduced. Note that, as shown in this embodiment, when a plate wiring is shared by multiple word lines, if the low potential of the data line is set higher than the low potential of the word line by more than the plate voltage amplitude, unselected It does not destroy the signals of memory cells connected to the word line.

Another embodiment of the present invention will be described using FIG. 5.

In this embodiment, the voltage amplitude of the data line and the voltage amplitude of the plate are made the same. Other operations and circuit configurations are the same as the embodiment shown in FIG.

FIG. 5(a) shows the read operation of the memory, and FIG. 5(b) shows the write operation. In this embodiment, the voltage amplitude of the data line and the electric amplitude of the plate are made the same, and the potential of the plate is set to an intermediate potential between the two types of storage potential of the memory cell during standby of the memory. As a result, the voltage applied to the capacitor of the memory cell is the same whether the potential stored in the memory cell is high or low, and the reliability of the capacitor can be improved.

FIG. 6 shows an example of a memory cell configuration in which one plate wiring is shared by two word lines.

In the figure, 1 is an n← diffusion layer which becomes the source (drain) terminal of a transistor constituting a memory cell, and is connected to a data line via a through hole 4. Data lines are not shown here to avoid complicating the drawing. The data lines are arranged perpendicularly to the word lines, such as ALM4. Reference numeral 2 denotes a plate wiring formed of the first polysilicon layer, which is shared by two word lines as shown in the figure. 3
is a word line formed of the second polysilicon layer.

By sharing one plate wiring with two word lines as shown in this embodiment, the number of spaces between the plate wirings can be reduced, and the chip size can be reduced.

FIG. 7 shows an example of a memory cell configuration in which one plate wiring is shared by four word lines.

According to this embodiment, the number of spaces between plate wirings can be further reduced, and the chip size can be reduced.

FIG. 8 shows one subarray (for example, 128 word lines,
6, which is an embodiment in which the plate wiring is shared by 512 pairs of data lines (512 pairs), a special wiring area is provided at the end of the sub-array. Run a low-resistance metal wiring in this area parallel to the word line.

If it is connected to the first polysilicon layer of the plate wiring.

The resistance of plate wiring can be lowered. This makes it possible to increase the response speed of the plate wiring.

FIG. 9 shows an example of a memory cell configuration in which a plate wiring is provided for each word line. In the figure, 1 is the source (drain) terminal of the transistor that constitutes the memory cell.
+In the diffusion layer, it is connected to the data line via the through hole 4. In this embodiment as well, data lines are omitted to avoid complicating the drawing. Note that the data lines are arranged perpendicularly to the word lines as in the previous embodiment. Reference numeral 2 denotes a plate wiring formed of a first polysilicon layer, which is separated for each word line. In the case of the memory cell configuration in which 3 is a word line formed of the second polysilicon layer, two data line configurations are possible. One is an open type data line (bit line) configuration, and the other is a folded type data line (bit line) configuration.
It is complete.

FIG. 9(b) shows an open data line configuration, where adjacent data lines are connected to different sense amplifiers. 9th
Figure (c) shows a folded data line configuration, in which adjacent data lines are connected to the same sense amplifier. in this case,
When one word line is selected, memory cells connected to the paired data lines are selected. That is, 1 bit 1/
It has a 2-cell memory cell array configuration. Therefore, the memory cell signal appearing on the data line can be twice as large as that in a 1 bit/1 cell memory cell array.

Another embodiment of the present invention will be described using FIG. 10. FIG. 10 shows operating waveforms showing another driving method for the plate wiring of the memory circuit shown in FIG. 4(a). In the operation shown in FIG. 10, the read operation until the output signal D out is output is the same as the embodiment shown in FIG. 5, but the rewrite operation is different. The rewriting operation is performed as follows. When the sense amplifier operates, Do is a high potential of 4V, and Do is a low potential of 2V.
It has become. At this time, the storage terminal 10 of the memory cell is connected.

The voltage is 4V, which is the same high potential as (when terminal 10 is at a high potential in FIG. 10). After that, the potential of the word line Wo changes from 5v to 4v.
decreases to Here, if the threshold voltage of the transistor constituting the memory cell is 1V, the storage terminal 10 is 4V,
Since the data line Do is 4V, the transistor To
is in the OFF state. Therefore, then plate Po'
changes from 2V to 4V, the potential of the storage terminal 10 becomes 4V.
It increases from ■ to almost 6V. On the other hand, if a low potential signal is stored in the memory cell, after the sense amplifier operates, Do is 2V and W product terminal 10 is 2V, so even if the word line drops to 4V.

The transistor To constituting the memory cell is in the ON state6. Therefore, even if Po' changes from 2V to 4V, the potential of the storage terminal is held at 2V by the sense amplifier. After that, after the word line Wo becomes OV,
Plate Po' changes from 4v to 2v. As a result, the potential at the storage terminal of the memory cell changes from approximately 6V to 4V when a high potential has been stored, and from 2V to Ov when a low potential has been stored. Therefore, the behavior of the storage terminal 11 of the memory cell connected to the 0th order unselected word line Wl, in which the memory cell stores a potential of 4V on the high potential side and OV on the low potential side, will be described. Storage terminal 11
If a high potential is written to the plate P during standby,
o' is 2V, and #product terminal 11 is 4V. After the sense amplifier amplifies the memory cell signal, PO2 becomes 4
When the voltage reaches V, the voltage at the storage terminal 11 becomes approximately 6V. after that,
P.

becomes 2V, and the potential of the storage terminal 11 returns to 4V.

During this time, the word line W1 is at OV and the data line Do is at 2V or more, so the transistor Tz is not turned on and the signal in the memory cell is not destroyed.

When a low potential is written to the storage terminal 11, during standby, the plate Po' is 2V, ? J product terminal 11 is set to Ov. After the sense amplifier amplifies the memory cell signal, when Pa' becomes 4V, the storage terminal 11 becomes approximately 2V.
become. After that, Po' becomes 2V and the potential of the storage terminal 11 returns to OV. During this time, the word line Ws is Ov and the data line Do is 2V or more, so the transistor T
1 will never be in the ON state, and the signal in the memory cell will not be destroyed.

As described above, in this embodiment as well, since the data line voltage amplitude can be made small, power consumption can be reduced. Furthermore, in this embodiment, the memory cell signal on the low potential side can be made larger than the memory cell signal on the high potential side.

Another embodiment of the present invention will be described using FIG. 11. Figure 11 shows the connection relationship between data lines and data input/output lines in the memory circuit, and the other circuit configurations are shown in Figure 4 (a).
) is the same as the circuit shown in ).

The circuit in Figure 11 converts the signals on the data lines Do and Do into MOS
-FET, Tz, is received at the gate of Ta and used as a drain current to connect the data input/output line I10゜Ilo
It is something that can be conveyed to people. In order to increase the signal transmitted to the data input/output line, it is important to use Tx and Ta in a region where g is large. In the embodiment shown in FIG. 4, the potential of the data line is set high, so T z .

Since T8 operates in a region where g is large, the signal can be increased. Therefore, if the circuit system of this embodiment is used in a memory that operates with a high data line potential, the S/S/
N can be achieved.

Another embodiment of the present invention will be described with reference to FIG. 12. In this embodiment, the word line voltage is set to two values. The operation and circuit configuration other than this are the same as the embodiment shown in FIG. While the data line precharge signal φP is 4V, the data line is precharged to 1V. After φP becomes Ov,
Word line W.

is 2 V + V t (V t is MO8-FET (
7) Increases to L (voltage). As a result, the memory cell signal is read out onto the data line. Next, the sense amplifier drive signal φsP changes from 1v to 2v, psn changes from 1v to Ov, and the memory cell signal is amplified. In this case, the word line W
If a high potential signal is accumulated in the memory cell connected to
) becomes Ov. At this time, the potential of the word line Wo is 2V+
Vt, the data 1iADo is 2V, and the storage terminal 10 of the memory cell is 2V, so the transistor To constituting the memory cell is turned OFF.

Next, when the potential of plate Po decreases from 4v to Ov,
The potential of the terminal 10 decreases a little, the transistor To turns on, and the 2V potential of the terminal 10 is held by the sense amplifier. After that, when the potential of the plate Po rises from Ov to 4V, the transistor To turns OFF.
The potential at terminal 10 rises to approximately 6V. On the other hand, the operation when a low potential signal is stored in the memory cell is as follows (waveform when terminal 10 is low potential in FIG. 12): After the memory cell signal is amplified by the sense amplifier, Since the data line Do is at Ov, the storage terminal 10 of the memory cell is at Ov, and the word line Wo is at 2 V + Vt, the transistor To forming the memory cell is turned on. Therefore, even if the potential of the plate Po changes from 4■ to Ov or from Ov to 4V, the potential of the terminal 10 will change to Ov.
hold. After the signals are accumulated in the memory cells as described above, the word line Wo becomes Ov. Also, after that φ
P is 4v, φSP and φSN are 1v, and the data line is 1v.
Precharged to v.

As described above, according to this embodiment, the same operation as the embodiment shown in FIG. 1 can be performed even when the word line voltage is binary. Therefore, the word line voltage control circuit becomes simple and easy to design.

Another embodiment of the present invention will be described using FIG. 13. This embodiment differs from the embodiment shown in FIG. 1 with a dummy word line WDo,
The difference is that WD1 is provided. The other circuit configuration and operation are the same as the embodiment shown in FIG. In the embodiment shown in FIG. 1, the signal (memory cell signal) when the word line is set to a high potential and the memory cell signal is read out to the data line is lower than that when a high potential is stored in the memory cell. This becomes larger than when the potential is WM. Therefore, in this embodiment, the difference is made small. for example.

Assume that the word line Wo is selected and has a high potential.

In this case, a memory cell signal appears in data 1Do (Dll). At this time, the dummy word line WDo is changed from a low potential to a high potential. As a result, the data line D becomes a reference signal.
The potential of o(Dn) increases slightly. As a result, if a high potential is accumulated in the memory cell by `fI, the memory cell signal becomes small in one equivalent manner, and becomes large if a low potential is accumulated in the memory cell. Therefore, the difference between memory cell signals when a high potential is accumulated and when a low potential is multiplied by fI can be reduced. This allows the noise merge to be averaged, and the S/
N can be improved. Note that when the word line W is selected, the dummy word line W D 1 changes from a low potential to a high potential.

FIG. 14 shows an example of a circuit for generating sense amplifier drive signals φSP and φ8N. In the figure, Ax is a differential amplifier circuit, which together with the transistor Trill resistor Rztt + Vrt determines the high potential of φsp. A2 is also a differential amplifier circuit, and together with the transistor Txxz and the resistors Rztz and Vrz, determines the low potential of φSN. The operation of this circuit is shown in Figure 14 (
This will be explained using the operation waveform of b). While the signal φ1 is 5V, the transistor T281. TxazrT268 is ON
Then, set φsp and φSFI to 3V.

At this time, signal φ2 is 5V, φ3 is Ov, and transistor T
zz, T24 is OFF. After φ1 becomes Ov, φ2 becomes Ov and φ3 becomes 5V. As a result, φSP
is 4V, which is the same potential as V r 1, and φSN is 2 V, which is the same potential as V r 2. After that, φ2 is 5v, φ8 is Ov
As a result, transistors Tax and Tz4 are turned off.

Next, φ1 becomes 5V, and the transistor TxespTxt
sz+ Tzgs turns ON and φSP+ LPss becomes 3
Make it v.

As described above, in this circuit, the high potential of φsp and the low potential of φSN can be arbitrarily determined by changing the magnitudes of Vrz and Vrz.

FIG. 15 shows an example of a word line voltage generation circuit.

In the figure, 33 is a word line, 36 is an X decoder, and 34 is an address signal line. 6Aδ is a differential amplifier circuit which, together with the transistor Tso, the resistors Rao and Vrs, determines the intermediate potential of the word line voltage. The operation of this circuit is shown in Figure 15 (
This will be explained using the operation waveform of b).

When the memory is on standby, the output terminal 35 of the X decoder is at a high potential of 5V. At this time, the signal φ is at a low potential Ov. Therefore, the transistor Tl! 111
T8δ2 is ON, T5xzt T331 is OF
F, and the word line becomes Ov. After this word line Wo
When is selected, the terminal 35 becomes Ov. As a result, the transistor T831 becomes ○N, Taaz becomes OFF, and the voltage of the word line rises to 5V. Next, when the φ number becomes 5V, the transistor Tazt turns OFF and T slz turns ON.
Therefore, the voltage of the word line becomes 4V, which is the same as Vrs. Thereafter, when the potential of the terminal 35 becomes 5■, the voltage of the word line becomes Ov.

As described above, the circuit shown in FIG. 15 can also create three levels of word line voltage.

An embodiment of the present invention will be described with reference to FIG.

In FIG. 16(a), MA is a memory cell array, which includes a plurality of data lines Do, Do+ to Dn, Dn*'7- data line Wo.
"W-, dummy word line WDo, WDt
, plate wiring P o ” P- and memory cell MC
Consists of.

XD is an X decoder that selects one of a plurality of word lines. YD is a Y decoder that selects one pair of data line pairs. *Yo-Yn is a data line selection signal line that transmits the output signal of the Y decoder.

PD is the terminal on one side of the capacitor that makes up the memory cell (
This is a plate drive circuit that controls the voltage of Po-PIl (referred to as a plate here). Similar to the X decoder, this circuit also selects one of the plurality of plate lines according to the address signal.
Select a book. Sense amplifiers 5Ao-5An are configured as a circuit as shown in FIG. 16(b), and amplify signals read out from the memory cells. In this example, the transistor with an arrow is a P-channel MO3FET (
The one without an arrow is an N-channel MO3FET (N-MOSFET). 1
is a signal line that transmits the data line precharge voltage Vap. 2
is the data line precharge signal line and the precharge signal φ,
convey. Sense amplifier drive signal lines 3 and 4 transmit sense amplifier drive signals φsp and π, respectively. Ilo,
Ilo is a data input/output line that transmits a write signal to the memory cell and a read signal from the memory cell.

Although not shown here, there is a 16th line on the data input/output line.
A precharge circuit IOP and a bias circuit IOB shown in FIG. 2(Q) are provided. AMP is an output amplifier that amplifies the signal read from the memory cell and outputs it as an output signal Dout. D, . . . are data manual buffer circuits that convert an external input signal (write signal) to a signal level within the chip.

φ is a write control signal.

Figure 16(a) shows the readout operation of the circuit shown in Figure 16(a).
This will be explained using the operation waveform shown in d).

FIG. 16(d) shows an example of the voltage value of each waveform for ease of explanation.

While the data line precharge signal φ- is 4V, the data line D
o, Do (Dnt Dn) is precharge potential, 1v
It becomes. At this time, sense amplifier drive signals φ5F, φ
sn is 1v, and the sense amplifier is in an OFF state. Assume that after φP becomes Ov, Po is selected from among the plurality of plate signal lines.

When Po changes from 4v to Ov, a memory cell signal appears on each data line. Here, assuming that a low potential signal O■ has been accumulated in the memory cell connected to the data line Do, when aPo changes from 4v to Ov, Ov of the memory cell
decreases towards -4v. At this time, the word mWo is O
When the amount of decrease exceeds the threshold voltage of the MOS-FET, the storage terminal 10 of the memory cell and the data line are connected. As a result, a current flows from the data line to the memory cell, and a memory cell signal appears on the data line Do. At this time, the dummy word line WDo changes from 4V to Ov. As a result, a reference signal appears on the data line Do. In addition,
When a high potential signal 6v is stored in the storage terminal 10, the potential of 1o becomes 2v due to the voltage change of Po.

In this case, the transistor To constituting the memory cell is O
Since it is in the FF state, the potential of the data line does not change.

Now, after the memory cell signal and reference signal appear on the data line, φsp changes from 1v to 2v, and φsn changes from IV to Ov.
Changes to As a result, the sense amplifier S Ao ” S
An operates to amplify the memory cell signal. Therefore, the data line Do becomes Ov, and Do becomes 2V. After this, the word line Wo changes from ov to 4■, and Ov (2V in the case of high potential reading) is written into the memory cell.

Next, a pair of data lines is selected by Y decoder YD. Here, it is assumed that Do and Do are selected. Therefore, the potential of the data line selection signal line Yo becomes 4V, and memory cell signals are read out to the data input/output, WI/○, and Z/○. This signal is amplified by the output amplifier AMP and lowers the sixth order word line Wo, which becomes the output signal Dout, from 4v to 2v. After this, change the plate Po from Ov to 4
Make it v. At this time, since a low potential Ov is written in the memory cell, the transistor To that constitutes the memory cell
is in the ON state. Therefore, the voltage Ov of the memory cell remains unchanged.

Note that when a high potential of 2V is written in the memory cell, the transistor To is in an OFF state.

Therefore, the potential of the memory cell increases from 2v to 6v. Thereafter, the word 1iAWo becomes Ov, and writing to the memory cell is completed. In addition, the dummy word line WDo has 0-order φsp and φsn that change from OV to 4V, and φ is 4V.
v, and precharges the data line to 1v.

Next, the write operation to the memory cell will be explained using the operation waveform shown in FIG. 16(e). After the memory cell signal is amplified by the sense amplifier in the same manner as the read operation, the write signal DI,l is taken into the data buffer.
Next, when the write control signal φ becomes 4V, the potential of the data input/output line I10゜Ilo changes to a high potential according to Di,l.
Divided into low potential. Here Ilo is 2V, D10
Suppose that becomes Ov. After that, Y decoder YD causes 1
A pair of data lines is selected. Here, it is assumed that Do and Do are selected. Therefore, the data line selection signal line Yo is 4.
It becomes v. Do becomes 2V, Do becomes Ov, and a high potential of 2V is written to the storage terminal 10 of the memory cell (operating waveform when the terminal 10 is at a low potential).On the other hand, a low potential is written to the memory cell in which the high potential is stored. The operation to write the potential is performed as follows. After the sense amplifier operates, Do is set to 2V, and Do is set to O.
It is V. The potentials of Ilo and Ilo are set to OV and 2V, respectively, by Dlll. After that, Yo rises to 4■, Do becomes OV, Do becomes 2V, and Ov is written to the storage terminal 10 of the memory cell (operating waveform when the terminal 10 is at a high potential).

The operation after a signal is written into the memory cell as described above is the same as the read operation. That is, among the memory cell signals, those at high potential are boosted to 6V, and those at low potential are stored at Ov.

As described above, according to this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, the voltage amplitude of the plate, which determines the voltage of the high potential signal of the memory cell, which is related to the information retention time of the memory cell, should be large, and the voltage amplitude of the data line, which is related to the power consumption of the memory (voltage amplitude during sense amplifier operation), should be large. ) can be made smaller compared to the voltage amplitude of the plate in this embodiment.

The voltage amplitude of the data line is reduced. This makes it possible to significantly reduce power consumption while ensuring a sufficient signal voltage for the memory cells. Therefore, low memory power consumption and high S
/N can be achieved at the same time. Further, in this embodiment, the potential at the time of precharging the data line is set to be between the high potential side and the low potential side of the voltage amplitude of the data line. This allows power consumption to be further reduced. The voltage amplitude of this data line can be reduced to about the sum of the absolute values of the threshold voltages of the N-NO3 transistor and the P-MOS transistor constituting the sense amplifier. Since the threshold voltage is normally 0.5V to 1.2V, if the voltage amplitude of the data line is 2V, the charging/discharging current can be reduced to 1/2.5 compared to the case of 5V amplitude. Further, in this embodiment, when the signal line is driven by 8 normal MO5FETs which read signals from the memory cell by changing the plate Po from 4V to Ov, the discharging operation is faster than the charging operation. Therefore, the speed of the read operation from the memory cell can be increased compared to the read operation in which the word line is changed from a low potential to a high potential.

FIG. 17 shows an embodiment of the word line drive P path.

In the figure, MA is a memory cell array, Do and D'o are data lines, Wo and W- are word lines, and Po and P- are plates. WD is a word line intermediate potential setting circuit which, together with a differential amplifier Azo, a transistor Tso, a resistor R60° and a reference voltage Vrto, sets the intermediate value of the word line voltage.

The operation of this circuit will be explained using the operating waveforms shown in FIG. 17(b). When the memory is on standby, the signal φ20 is OV, φz1 is 4V, and the plate drive signal φP is 0°φ2. ．． is 4v. Therefore, the transistor T e l 1.
T e a , T sδ is ON, Text, T
psa.

TP83 is OFF, iJ, '7- wires Wo, W- and OV- terminal 64 are at 4V. After that, signal φ2
1 becomes OV and transistors Tea and Teδ are turned off. Next, when φpmO becomes Ov, the transistor T
psg turns ON and the voltage of the word line WO becomes 4V. Next, when the signal φ20 becomes 4V, the transistor T8
11 is OFF and T812 is ON.

This causes the voltage at terminal 64 and word line WO to be 2v.
become. Thereafter, when φpmo becomes 4v and then φ21 becomes 4v, the voltage of the word line Wo becomes Ov.

As described above, according to this embodiment, a word line can be selected by selecting a plate, thereby eliminating the need for a word line selection circuit.

Furthermore, since the plate and word line can be selected almost simultaneously, the speed of the memory can be increased.

Another embodiment of the present invention will be described using FIG. 18. This memory circuit is the same as the circuit shown in FIG. 16(a) except that it has 2 cells/bit and there is no dummy word line. Since there are 2 cells/bit, memory cell signals are simultaneously read out to each pair of data lines.

Since these two signals are always in a complementary relationship, no dummy cell is required. The operation of this circuit is shown in Figure 18(b).
This will be explained using the operating waveforms.

While the data line precharge signal φP is 4V, the data line D
o, Do(Dny o,,) is precharged to 1v. At this time, the sense amplifier drive signal φSF.

π is 1v, and the sense amplifier SAo~5Afi
is in the OFF state. Next, plate Po is selected and goes from 4v to Ov. As a result, the signals of the memory cells connected to Po are read out to each data line. for example,
Assume that the high potential 6V is stored in the storage terminal 10 of the memory cell, and the low potential Ov is stored in the storage terminal 11 of the memory cell. Plate Po is 4v
When the voltage changes from Ov to Ov, the potential at the terminal 10 changes from 6v to 2v.

At this time, the data line DO is at 1V and the word line WO is at OV, so the transistor To1 is OFF and the voltage of the data line Do does not change. On the other hand, the potential of terminal 11 is O
At this time, the data line D decreases from v to -4v.
O is IV, word line W.

is Ov, so when the potential of the terminal 11 becomes lower than the MOSFET threshold voltage V, the transistor Tax turns on.
Therefore, a current flows from the data line Do toward the terminal 11. This causes the potential of the data line DO to drop slightly. As a result, the data lines Do, D.

This means that memory cell signals are read out to both.

Next, the sense amplifier drive signal φsp changes from 1v to 2v,
φsn changes from 1v to Ov, the sense amplifier operates,
Do becomes 2v, DO becomes Ov 0 order, word R&W
After the voltage of o becomes 4V, 2V is rewritten to the storage terminal 10 of the memory cell, and ov is rewritten to 11, the data lines Do, Do are selected by the Y decoder YD, and the data line selection signal line Yo becomes 4v. As a result, the memory cell signal is transferred to the data input/output line I10. It is read out at I10.

This signal is amplified by the output amplifier AMP and becomes the output signal Dout. After this, the potential of word line WO becomes 2v.
decreases to At this time, the potential of the data line DO is 2v, 5τ
The potential of the memory cell is Ov, and the potential of the storage terminal 10 of the memory cell is 2V.
, 11 is Ov, so the transistor Tax is Ov.
F F , the 0th order when Tow is ON, the plate PO
When the voltage increases from Ov to 4V, the storage terminal 1 of the memory cell
The potential of 0 becomes approximately 6V, and the potential of 11 remains at ov. After this, the potential of the word line becomes Ov, and writing to the memory cell is completed. Therefore, when approximately 6V is written to the storage terminal 10 of the memory cell and Ov is written to 11 again, the data line precharge signal i becomes 4V.
, the sense amplifier drive signal φsp is set to IV, the voltage is set to 1V, and the data line is precharged to 1V.

Next, the write operation to the memory cell will be explained using the operation waveform shown in FIG. 18(c). Similarly to the read operation, after the memory cell signal is amplified by the sense amplifier, the write signal D r a is taken into the data manual buffer. Next, when the write control signal φ becomes 4V, the data input/output line /○.

The potential of Ilo is divided into high potential and low potential depending on DI and l. Here, it is assumed that Ilo becomes OV and Ilo becomes 2■. After that, a pair of data lines is selected by Y decoder YD. Here, Do, D.

Suppose that is selected. Therefore, data line selection signal line Yo
becomes 4v. This makes DO Ov.

becomes 2V, Ov is written to the storage terminal 10 of the memory cell, and 2V is written to the storage terminal 11 of the memory cell.

The operation after this is the same as the read operation. That is,
The potential of the storage terminal 11 of the memory cell is boosted to 6V, and the potential of 10 is stored as Ov.

As described above, also in this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, the data line charging/discharging current can be reduced, and the power cost of the memory can be reduced. Further, the decrease in the write voltage to the memory cell due to the reduction in the data line voltage amplitude is compensated for by writing from the plate. Therefore, since the present embodiment uses a 2-bit/cell configuration, the information retention time and α-ray soft error resistance characteristics can be improved, so the readout signal of the memory cell is twice that of 1-bit/cell. High S/N can be achieved. Further, dummy cells are not required.

Another embodiment of the present invention will be described using FIG. 19. This circuit differs from the circuit shown in FIG. 16(a) in that a bipolar transistor is used to read the memory cell signal from the data line. Therefore, two types of data input/output lines are provided: signal reading wirings 0, 0 and signal writing wirings I, I. Although only the relationship between the data line and the data input/output line is shown here, the other circuit configuration is the same as that shown in FIG. 16(a). The operation of this circuit is the same as that shown in FIG. 16 except that the potential of the data line and related potentials are different since a bipolar transistor is used to read out the memory cell signal. The read operation of this circuit will be explained using the operation waveforms shown in FIG. 19(b).

Assuming that the forward voltage between the base and emitter of the Pipo transistor is VBE, the data line D is precharged to 2.VBE while the data line precharge signal φP is 4V. At this time, sense amplifier drive signals φsp, φ
sI, is 2・VBE, and the sense amplifier is OF
It is in F state.

Next, the plate P changes from 4V to Ov, and the signal of the memory cell is read out to the data line. Assume that a low potential VBE is stored in the storage terminal 10 of the memory cell. When plate P goes from 4v to ov.

The potential of the terminal 10 decreases from vBE toward -(4-VBE). At this time, the data line is at 2·VBE and the word line W is at Ov, so the potential at terminal 10 is -Vt.
When it becomes lower than , the transistor T constituting the memory cell
is turned on, and current flows from the data line toward the terminal 10. As a result, the memory cell signal is read out onto the data line. On the other hand, at this time, the dummy word line WD changes from 4V to Ov, and a reference signal appears on the data line.

In order to simplify the explanation, only the D dummy word line is shown here, but in an actual memory, the D dummy word line is also provided.

Also, a high potential of 3VBE is applied to the storage terminal 1o of the memory cell.
If +4V has been accumulated, when P changes from 4V to Ov, the potential at the terminal 10 becomes 3·VBE. At this time, the data line is at 2 VBE and the word line W is at Ov, so the transistor T is OFF and the potential of the data line remains unchanged.Now, the memory cell signal and the reference signal are on the data line. After appearing, the sense amplifier drive signal φsp becomes 2-V.
BE to 3-VBE, φsn from 2-VBE to VBE
Change to As a result, the sense amplifier operates and D becomes VBE.
, D becomes 3・VBE. Next, the potential of the word line W is 4
VBE is written to the terminal 10 again. After this, Y of the data line selection signal line becomes 4V, and the memory cell signal on the data line is read out to the signal reading wirings ○ and ○ via the bipolar transistor. This signal is amplified by the output amplifier and becomes the output signal D out .After this, the potential of the word line W decreases to 3·VBE. At this time, the potential of the data line is VBE and the potential of the terminal 10 is also VBE, so the transistor T is in the ON state, and even if the plate P changes from Ov to 4V, the potential of the terminal 10 remains VBE.

Note that when a high-potential signal is stored in the memory cell, when the potential of the word line becomes 3.VBE, the potential of the data line is 3.VBE, and the potential of the terminal 10 is also 3.VBE. Therefore, the transistor T is turned off, and when the voltage of the plate P changes from Ov to 4V, the potential of the terminal 10 rises to 3·VBE+4V. After this, the potential of the word line becomes Ov, and writing to the memory cell is completed. Further, the dummy word line WD changes from Ov to 4V. Thereafter, the data line precharge signal φP becomes 4V, the sense amplifier drive signal φsr becomes 2·VBE, and $− becomes 2·VBE, so that the data line is precharged to 2·VBE.

Next, the write operation to the memory cell will be explained using the operation waveform shown in FIG. 19(c). Similar to the read operation, after the memory cell signal is amplified by the sense amplifier, the write signals Dl, l are taken into the data manual buffer. Depending on this signal, the potentials of the signal writing wirings I and I are divided into high potential and low potential. Here, the engineering is 3・VBE,
Suppose that ■ becomes VBE. Thereafter, the data line selection signal line Y is set to 4V by the Y decoder YD. This)
JD is 3-VBE, D is VBE2, terminal 1
3·VBE is written in °. The operation after this is the same as the read operation. That is, the potential at the storage terminal 10 of the memory cell is boosted to 3·VBE+4■, and is stored.

As described above, in this embodiment as well, the data line voltage amplitude can be reduced while ensuring a sufficient memory cell signal, so that the power consumption of the memory can be reduced.

Furthermore, in this embodiment, the potential of the data line is determined based on the forward voltage between the base and emitter of the bipolar transistor, so it is easy to design a memory LSI in which MOSFETs and bipolar transistors are mixed.

Another embodiment of the present invention will be described with reference to FIG. 20. This embodiment is another example of the operation of the circuit shown in FIG. 4(a). This embodiment shows operating waveforms when a write command signal from outside the chip is input to the chip with a significant delay with respect to the address strobe signal. This embodiment differs from the operating waveform shown in FIG. 4(c) in that the storage terminal of the memory cell is boosted twice by the plate. Others are 4th
This is the same as the operating waveform in Figure (Q). In addition, in Figure 20, R
AS is a row (X) address strobe signal, CAS is a column (Y) address strobe signal, and WE is a write command signal.

The operation from reading the memory cell signal to boosting the voltage by the plate of the storage terminal is the same as the operation shown in FIG. 4(b). This is a write operation. This causes the word @W.

The potential rises to 7V again. On the other hand, the data line selection signal line Yo changes from ov to 6V, and signals are written to the data lines Do and Do via the data input/output line. Here, it is assumed that 3V is written to Do and 5V is written to Do. As a result, the primary plate Po', on which 3V is written to the storage terminal 10 of the memory cell, changes from 6V to 3V again. At this time, since the potential of the word line Wo is 7V, the potential of the storage terminal 10 is held by the sense amplifier. After that, the potential of the word line Wo decreases to 5V.
' changes from 3v to 6v. In this case, since the potential of the word line Wo is 5V and the potential of the data line Do is 3V, the transistor To forming the memory cell is in an ON state, and the potential of 3V at the storage terminal 10 is held by the sense amplifier. Note that when a high potential of 5V is written to the storage terminal 10, the potential of the word mWo becomes 5V, so that the transistor To is turned off. Therefore, when the plate Po' changes from 3V to 6V, the potential of the W product terminal 10 rises from 5V to approximately 8V (20th
After one or more operations (when the terminal 10 is at a low potential in the figure), the potential of the word line Wo becomes Ov, and writing of the signal to the memory cell is completed. After that, the data lines Do, Do are precharged to 4V.

Also, φsp and φS11 become 4v.

As described above, according to this embodiment, the voltage amplitude of the data line can be reduced even in the operation mode in which write commands are input slowly, so that power consumption can be reduced.

Another embodiment of the present invention will be described using FIG. 21. Second
The operating waveform shown in FIG. 1 differs from the operating waveform shown in FIG. 20 in that the word line voltage waveform is binary, but otherwise is the same. When making the potential of the word line binary, as shown in the example of FIG. 12, if the potential on the high potential side is set higher than the high potential of the data line by the threshold voltage of the MOSFET, It becomes possible to boost the voltage at the storage terminal. Therefore, in this embodiment, even if the write command is input late.

The word line voltage remains unchanged, and only the storage terminal is boosted by the plate again. Therefore, according to this embodiment, there is no need to boost the word line voltage during writing, making circuit design easier.

Another embodiment of the present invention will be described with reference to FIG. 22.

In FIG. 22(a), MA is a memory cell array that stores a plurality of data INr ml o , ml o , ~LJ n
+ υ. , word fitting WO, Wl-W-, dummy word lines W Do , W D t.

It consists of plate wirings Pa, Pz to P, dummy cells DMC and memory cells MC. MC is composed of a MOS transistor To and a storage capacitor Cs.

DMC is a dummy cell for generating reference voltage and MO
It is composed of S transistors TB and T4 and a storage capacitor Cso. Reference numeral 8 denotes a signal line for writing the storage voltage DV into the dummy cell, and transmits a dummy cell write signal DC. X
D is an X decoder that selects one of a plurality of word lines and a dummy word line in response to an external address signal. The relationship between the word line and the dummy word line is such that when the word line Wo, in which the memory cell is connected to the data line Do, is selected, the DWs, in which the dummy cell is connected to Do, is selected. YD is a Y decoder that selects one of a plurality of data pairs. YO to Y are data line selection signal lines that transmit the output signal of the Y decoder. PD is the terminal (referred to as plate here) on one side of the capacitor that makes up the memory cell.

This is a plate drive circuit that controls the voltage of ~P.

Like the X decoder, this circuit also selects one of a plurality of plate lines in response to an address signal.

5Ao=SA□ is P channel MOS transistor and N
This is a normal sense amplifier composed of flip-flops of channel MOS transistors, and amplifies the signal read from the memory cell. 1 is a signal line that transmits the data line precharge voltage vdP.

2 is a data line precharge signal line and precharge signal j
Convey 7. Sense amplifier drive signal lines 3 and 4 transmit sense amplifier drive signals φs1φ3n, respectively. Il
o and Ilo are data input/output lines that transmit write signals to memory cells and read signals from memory cells. Although not shown here, a precharge circuit is provided for the data input/output line. AMP is an output amplifier that amplifies the signal read from the memory cell and outputs the output signal Dout. IIDIIB is a data buffer that converts an external input signal (write signal) to a signal level within the chip. φ is an intrusion control signal.

Figure 22 (a) shows the readout operation of the circuit shown in Figure 22 (a).
This will be explained using the operation waveform shown in b).

FIG. 22(b) shows an example of the voltage value of each waveform for ease of explanation. The voltage value of each waveform is not limited to this value.

While the data line precharge signal φP is 4V, the data line D
ot Do (Dnl Dn) is the precharge potential, 2
VBE (1.6V). At this time, the sense amplifier drive signals φip and φsll are at 2VBE, and the sense amplifier is in an OFF state. After φP becomes Ov,
Assume that Wo is selected from among the plurality of word lines. When Wo changes from Ov to 5VBE (4V), a memory cell signal appears on each data line.

Here, M of the memory cell connected to data Nl & D o
M terminal 10 D is high potential a VBE+5 VBB=8
VBf! Assume that (6,4V) is accumulated. Wo
is 5VBE from Ov! (4V), a read signal voltage corresponding to the data line capacitance Go and the storage capacitance Cs appears on the data line Do. This read signal amount ΔVs is as follows: ΔVs('1')=Cs/(Co+C5)X Vs
('1') Here, C5: Storage capacity CD = Data line capacitance Vag: Forward voltage between base and emitter of bipolar transistor (0,8V) Vs ('1'): W product voltage (8VBE! -2
(VBB=6 VBE (4, 8V)) Furthermore, the read signal voltage ΔVs ('O') when the low potential signal VRE is accumulated in the storage terminal 10 is ΔV
s('O')=Cs/(Co+C5)XVs('O'')
Vs('O'): Accumulated voltage (2VBE - VaE
= VBF (0,8V)).

With such a voltage relationship, as described above, the read signal voltages are significantly different between +1' and jO7. Dummy cells are provided to eliminate this imbalance. A cell connected to a data line opposite to that of the memory cell is selected as the dummy cell.

That is, when the word line Wo is selected, the dummy word @WDt is selected, and the reference read signal voltage ΔVso appears on the data line Do. The value of ΔVso is determined by the storage voltage of the dummy cell, that is, the voltage value of DV. Normally, the voltage value of DV is.

'1' and 'O' (7) Intermediate value, i.e. 4.5Va
F! (3,6V). If it is desired to increase the margin on the 11' side due to α-ray soft errors or refresh problems, the voltage value of VD may be lowered.

Now, after the memory cell signal and reference signal appear on the data line, φsp goes from 2 VBE (1, 6 V) to 3 VB!
! (2,4'V)Ic, $sn from 2VBp to VaEL
:Change. This causes the sense amplifier 5Ao=SA to operate and amplify the memory cell signal. Therefore, data line Do becomes 3VBE and Do becomes VBH. Next, plate Po 5 VBE! (4V) to OV. At this time, the word line voltage is 5VBB (4V), so even if the plate voltage changes, the terminal 10 of the memory cell is 3V.
BB(2,4V) (7) A pair of data lines is selected by the 0th order Y decoder YD which applies the data line voltage. Here, it is assumed that Do and Do are selected. Therefore, the potential of the data line selection signal line Yo becomes 4V, and the data input/output line I
10. A memory cell signal is read out to I10. This signal is amplified by the output amplifier AMP, and the output signal D o
5Vap (4
V) to 3VBE (2,4V). After this, the plate Po is changed from Ov to 5 Vag (4V). Since the high potential 3Vap is written in the memory cell, the transistor To that constitutes the memory cell is Ov.
It is in FF state. Therefore, the terminal 1° voltage of the memory cell increases from 3Vap to 3VBE+5VBE (6, 4V). Note that when the low potential Vae is written in the memory cell, the transistor To is in the ON state. Therefore, the potential of the terminal 10 of the memory cell remains at VBH. Thereafter, the word line Wo becomes Ov, and writing to the memory cell is completed. Next, φsp, φSn are 2VBE, φ
? becomes 4V, precharging the data line to 2VBH.

Next, the write operation to the memory cell will be explained using the operation waveform shown in FIG. 22(c). After the memory cell signal is amplified by the sense amplifier in the same way as the read operation, the write signal Dln is taken into the data input buffer. When the 0th order write control signal φW becomes 4V, the data input/output line I10° 6. The potential is divided into high potential and low potential depending on Dln. :, in m, engineering/○ is vBE, Ilo is 3
Suppose it becomes VBH. After that, Y decoder YD causes 1
A pair of data lines is selected. Here, it is assumed that Do and Do are selected. When the data line selection signal line Yo becomes 4V, Do becomes Vag and Do becomes 3VBH, and a low and high potential VBE is written to the storage terminal 10 of the memory cell (when a high potential is initially stored in the terminal 1o) operating waveform),
On the other hand, the operation of writing a high potential to a memory cell in which a low potential has been accumulated is performed as follows.
o is VaE, and Do is 3VBE. Ilo, I
The potentials of lo and ll are 3VBB and VBH, respectively.
be made into

After that, Yo rises to 4V, Do becomes 3VBE, D.

becomes Vsa, and 3VB is applied to the storage terminal 10 of the memory cell.
p is written (operating waveform when a low potential is initially stored in the terminal 10).

The operation after a signal is written into the memory cell as described above is the same as the read operation. That is, among the memory cell signals, those with high potential are boosted to 3 VBE+ 5
VB! = 8 VBB (6,4V), low potential is stored in VBB. In addition, the dummy cell has lMOS
Dummy cell write signal DC via transistor Tδ
A constant voltage DV is written.

As described above, according to this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, the voltage amplitude of the plate, which determines the voltage of the high potential signal of the memory cell, which is related to the information retention time of the memory cell, should be large, and the voltage amplitude of the data line, which is related to the power consumption of the memory (voltage amplitude during sense amplifier operation), should be large. ) can be made smaller. In this embodiment, the voltage amplitude of the data line is made smaller than the voltage amplitude of the plate. This makes it possible to significantly reduce power consumption while ensuring a sufficient signal voltage for the memory cell. Therefore, it is possible to achieve both low power consumption and high S/N of the memory. Further, in this embodiment, the potential at the time of precharging the data line is set to be between the high potential side and the low potential side of the voltage amplitude of the data line. This allows power consumption to be further reduced. The voltage amplitude of this data line can be reduced to about the sum of the absolute values of the threshold voltages of the N-MOS transistor and the P-MOS transistor constituting the sense amplifier. Since the threshold voltage is normally from 0.5 V to IV, if the voltage amplitude of the data line is 2 Vag (1, 6 V), the charging/discharging current can be reduced to about 1/3 compared to the case of 5 V amplitude. In addition, in this embodiment, a dummy cell is provided so that its storage voltage can be freely controlled.
It is possible to freely control the readout signal amount of ITIOl, and it is possible to design a memory that is resistant to α-ray soft errors and has low power consumption without adversely affecting refresh characteristics. In addition, in this embodiment, each operating voltage such as the potential of the data line is determined based on the forward voltage between the base and emitter of the bipolar transistor, so it is easy to design a memory LSI in which MOSFETs and bipolar transistors are mixed. .

FIG. 23 shows a specific example of the dummy cell write voltage DV. Bipolar transistor Q.

and resistors R1, Rz, and Rs. The voltage value DV of the terminal 21 is expressed as the base-emitter voltage of RsVBE:Qo, and R
The voltage value can be freely set by the resistance values of z and R8.

Another embodiment of the present invention will be described using a memory circuit shown in FIG. 24(a). This memory circuit is different from the circuit shown in FIG. 22(a) in that the plate electrode of the storage capacitor of the memory cell is
They are the same except that they are common to each word line.

Since the plate electrode is shared by two word lines, higher integration can be achieved than in the case of FIG. 1. The operation of this circuit will be explained using the operating waveforms shown in FIG. 24(b).

While the data line precharge signal φ is 4V, the data line D
o, D o (D n −D −) is 4 VBE (
It is precharged to 3.2V). At this time, the sense amplifier drive signal φSFt φ5n is 4Vng, and the sense amplifier 5Ao=SAn is in the OFF state.

After φP becomes Ov, a word line is selected.

Here, it is assumed that word line Wo is selected. Word line W
When o is selected and becomes 5.5■ from Ov, W.

The signals of the memory cells connected to are read out to each data line. Here, the memory cells connected to the word line Wo are
Assume that signals of high potential (about 88F) have been accumulated in each case. Therefore, '1' information is stored in Do and On.
At n, the reference voltage is read from the dummy cell.
Sense amplifier drive signal psp is 4vRF! , Kara5Va
At E, φs,l changes from 4VBE to 3VBp, the sense amplifier operates, Do is amplified to 5VaE, and Do is amplified to 3Vap.After that, a pair of data lines DO#DO is selected by Y decoder YD, and the data Line selection signal Yo becomes low potential, and data input/output lines I10. A memory cell signal is read out to I10. This signal is amplified by the output AMP, becomes an output signal Do□, and is output to the outside.

Next, the operation of rewriting a signal to a memory cell will be explained. The sense amplifier sets Do to a high potential of 5Vag and Do to a low potential of 3VBH. At this time, since the word line Wo is at a high potential, the storage terminal 10 of the memory cell is 5VBE, which is the same as Do.Then, the plate Pa' is 5.5V.
B! (4,4V) to 2.5VBE (2V), but the potentials of the data line and storage terminal 10 do not change because they are held at 5Vap by the sense amplifier. After that, the potential of the word line Wo changes from 5.5V to 5VBE! decreases to

Here, assuming that the threshold voltage of the transistor constituting the memory cell is 1V, the voltage at the storage terminal 10 is 5VBE.

Since the data line Do is at 5VBE and the word line Wo is at 5VBE, the transistor To is in an OFF state. Therefore, next time Po changes from 2.5VBE to 5.5VBH, the potential of the storage terminal 10 will change from 5V8E to approximately 8V.
It rises to BE (6.4V). As a result, a high potential of approximately 8VBH is written into the memory cell. On the other hand, if a low potential signal of the memory cell is accumulated, the operation will be as follows. Terminal 1 in Figure 24(b)
This will be explained using an operation waveform when 0 is a low potential. After the sense amplifier operates, the data line Do is at a low potential of 3VB! ,
The potential of terminal 10 is also 3VsF! There's a lot of yelling. Therefore, after this, the potential of the word line Wo increases from 5.5V to 5VBE.
(4v), the transistor To constituting the memory cell remains in the ON state. Therefore, plate Po′
No matter how the data i changes, the sense amplifier
Since the potential is fixed, the potential of the storage terminal 10 is 3V.
af! is maintained. As a result, the memory cell has a low potential of 3VBI again! Now, in this embodiment, the potential of the memory cell connected to the unselected word line also changes. The behavior of the storage terminal 11 of the memory cell connected to this unselected word line W1 will be explained. first,
The operation when a high potential is written to the storage terminal 11 is as follows. During standby, plate Po' is 5,5
Vup, W product terminal 11 is 8VugiC.

After the sense amplifier amplifies the memory cell signal, Po'
When the voltage becomes 2.5 Vaa, the storage terminal 11 becomes 5Vap. At this time, the word line W1 is Ov, and the data line τ is 3V.
Since it is BE, the transistor T1 will not turn on and the information in the memory cell will not be destroyed.After that, Po' becomes 5.5VBH and the storage terminal 11
The potential returns to 8VBH. The operation when a low potential is written to the storage terminal 11 is as follows. When waiting,
Plate PO is 5.5VBE, W product terminal 11 is 3VBp
Nittatail.

After the sense amplifier amplifies the memory cell signal, Po'
When it became 2.5VBE, the district rushed and 11 became OV. At this time, the word line W1 is Ov, and the data line τ is 5VBB.
Therefore, the transistor Tl is not turned on and the information in the memory cell is not destroyed.After that, Pa' becomes 5.5VBH and the potential of the storage terminal 11 returns to 8VBH. Next, the word line Wo becomes Ov, and rewriting to the memory cell is completed. After that, φsp,
φS becomes 4VaE, and 77 becomes a high potential, making the data line 4VBI! Precharge to.

Next, the write operation to the memory cell will be explained using the operation waveform shown in FIG. 24(Q). First, the operation of writing a low potential into a memory cell in which a high potential is stored will be described. Similarly to the read operation, after the memory cell signal is amplified by the sense amplifier, the write signal DIfl is taken into the data buffer. Next, when the write control signal φ becomes high potential, the data input/output lines I10. I1
The potential of 0 is divided into high potential and low potential depending on DIn. , :m: then Ilo is 3VBF, , Ilo is 5VBH
Suppose that it becomes After that, a pair of data lines is selected by Y decoder YD. Here, it is assumed that Do and Do are selected. Therefore, the data line selection signal line Yo becomes high potential. As a result, Do becomes 3Vas and Do becomes 5Vag, and a low voltage of 3VBB is written to the storage terminal 10 of the memory cell. The operation after this is the same as the read operation.

As described above, also in this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, the data line charging/discharging current can be reduced, and the power consumption of the memory can be reduced. Further, the decrease in the write voltage to the memory cell due to the reduction in the data line voltage amplitude is compensated for by writing from the plate. Therefore, the information retention time and the α-ray soft error resistance can be improved. In addition, in this embodiment, a dummy cell is provided so that its storage voltage can be freely controlled, so that
' can be freely controlled, making it possible to design a memory that is resistant to α-ray soft errors and has low power consumption without adversely affecting refresh characteristics. Also,
In this embodiment, each operating voltage such as the potential of the data line is the forward voltage VB between the base and emitter of the bipolar transistor.
! ! Since it is decided based on this, it becomes easy to design a memory LSI in which MOSFETs and bipolar transistors are mixed.

Furthermore, since the plate is commonly wired by two word lines Wo and W1, the chip area can be reduced.

〔Effect of the invention〕

According to the present invention, the data line voltage amplitude during sense amplifier operation can be significantly reduced compared to the conventional one, so the data line charging/discharging current can be reduced, and the power consumption in the memory cell array can be reduced to a level lower than that of the conventional one.
It can be reduced to /2 to 1/3.

Further, by boosting a high potential among the memory cell signals from the plate, the memory cell signal can be increased.

Therefore, the present invention provides memory with low power consumption and high S/N.
It is effective for Namely.

Improved information retention time and alpha soft error resistance.

It is possible to reduce noise and improve reliability.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram and operating waveform diagram of an embodiment of the present invention, Fig. 2
3 is a diagram showing a memory cell configuration of an embodiment of the present invention. FIG. 4 is a circuit diagram and operation waveform diagram of an embodiment of the present invention. 5 is an operation waveform diagram of an embodiment of the present invention, FIG. 6 is a diagram showing a memory cell configuration of an embodiment of the present invention, and FIG. 7 is a diagram showing a memory cell configuration of an embodiment of the present invention. FIG. 8 is a diagram showing a memory cell configuration of an embodiment of the invention, FIG. 9 is a diagram showing a memory cell configuration of an embodiment of the invention, and FIG. 10 is an operation waveform diagram of an embodiment of the invention. , FIG. 11 is a circuit diagram of an embodiment of the present invention, and FIG. 12 is a circuit diagram of an embodiment of the present invention.
The figure is an operational waveform diagram of an embodiment of the present invention, Figure 13 is a circuit diagram of an embodiment of the present invention, Figure 14 is a circuit diagram and operational waveform diagram of an embodiment of the present invention, and Figure 15 is a diagram of this embodiment. FIG. 16 is a circuit diagram and operating waveform diagram of an embodiment of the invention; FIG. 17 is a circuit diagram and operating waveform diagram of an embodiment of the invention; FIG. 18 is a circuit diagram and operational waveform diagram of an embodiment of the present invention, FIG. 19 is a circuit diagram and operational waveform diagram of an embodiment of the present invention, and FIG. 20 is an operational waveform diagram of an embodiment of the present invention. Fig. 21 is an operating waveform diagram of an embodiment of the present invention, Fig. 22 is a circuit diagram and operating waveform diagram of an embodiment of the invention, Fig. 23 is a circuit diagram of an embodiment of the invention, Fig. 24 1 is a circuit diagram and an operation waveform diagram of an embodiment of the present invention. MA...Memory cell array, XD...X decoder,
YD...Y decoder, PD...plate drive circuit,
AMP...Output amplifier, DiB...Data input buffer, P o g P m "' plate wiring, Do,
Do, Dn + Figure 1 (b) YD Y decouper DiB\D, force -y77
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Claims (1)

[Claims] 1. A plurality of data lines, a plurality of word lines arranged to intersect with the data lines, a memory cell arranged at the intersection of these lines, an amplifier that amplifies the memory cell signal read out on the data line, and the word line. It consists of a switching means whose ON/OFF state is controlled by the voltage of the line, and a signal storage capacitor, one end of which is connected to the data line via the switching means, and the other end connected to the first control signal line. 1. A memory circuit comprising connected memory cells, wherein the voltage amplitude of the first control signal line is larger than the voltage amplitude of the data line. 2. The memory circuit according to claim 1, wherein the potential of the data line during memory standby is between a high potential and a low potential of voltage amplitude during sense amplifier operation. 3. The voltage amplitude of the data line is determined by M that constitutes the sense amplifier.
The memory circuit according to claim 1 or 2, characterized in that the voltage is reduced to near the threshold voltage of an OS-FET. 4. The memory circuit according to claim 1, wherein the potential on the low potential side of the voltage amplitude of the data line is higher than the potential on the low potential side of the word line by more than the voltage amplitude of the first control signal line. . 5. The memory circuit according to claim 1, wherein among the accumulated signals of the memory cell, a signal on a high potential side is larger than a signal on a low potential side. 6. The potential of the first control signal line is between the high potential side signal potential and the low potential side signal potential of the memory cell signal when the memory is on standby; Memory circuit in the second term. 7. The memory circuit according to claim 1 or 2, characterized in that the signal of the memory cell is read onto the data line by changing the potential of the first control signal line from a high potential to a low potential. . 8. The word line is selected by changing the potential of the first control signal line from a high potential to a low potential, and the signal of the memory cell is read onto the data line. Memory circuit in the second term. 9. A plurality of data lines, a plurality of word lines arranged to intersect with the data lines, a memory cell arranged at the intersection of these lines, an amplifier that amplifies the memory cell signal read on the data line, and a voltage of the word line. It consists of a switching means whose ON/OFF state is controlled and a signal storage capacitor, one end of which is connected to the data line via the switching means, and the other end of which is connected to the first control signal line from the memory cell. 1. A memory circuit comprising: a voltage amplitude of the first control signal line is larger than a voltage amplitude of the data line. 10. The memory circuit according to claim 9, wherein the potential of the data line during memory standby is intermediate between the high potential and the low potential of the voltage amplitude during sense amplifier operation. 11. The memory circuit according to claim 9 or 10, characterized in that the voltage amplitude of the data line is reduced to near the threshold voltage of a MOS-FET constituting a sense amplifier. 12. The memory circuit according to claim 9, characterized in that a dummy cell is provided on the data line.