JPS6226116B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and in particular to a one-transistor type dynamic memory.

Please note that the following explanation is for N channel only for convenience.
Although MOS transistors are used as examples, the present invention is essentially equally applicable to P-channel MOS transistors or any other type of insulated gate transistor.

A block diagram of a conventional one-transistor type dynamic memory is shown in FIG. In Figure 1, 1
is an X decoder that selects one line out of n word lines according to the X address signals X ₀ , X ₁ , ..., X _l ; 2 and 2' are memory cells arranged in m rows and n columns; A memory cell matrix consisting of n bit lines and n word lines, 3 a sense amplifier group provided corresponding to each bit line, 4 a sense amplifier group provided corresponding to _{each bit} line, and 4 a memory cell matrix consisting of n _{word lines} . A Y decoder selects one row out of m rows of bit lines, and 5 is an input/output circuit that receives an output signal from the Y decoder and controls input/output signals from the bit lines. FIG. 2 shows a circuit block diagram of the circuit in the j-th row of FIG. 1. In Figure 2, 20 and 2
0' is a memory cell connected to the word lines wj and wk of the j-th column and the k-th column, representing a large number of memory cells connected to the i-th row bit lines B _i and _i ;
21 and 21' connect the potential between the high and low binary levels read from the memory cell to the bit line B _i or _i.
30 is a sense amplifier that amplifies the minute difference signal read from the memory cells on bit lines B _{i and i} at the timing of clock signal P2; An input/output circuit that controls reading of the difference signal and writing to the bit line using the output signal PY _i from the Y decoder, 6
0 and 60' are bit lines B _i by clock signal P ₁
and a precharge circuit for setting _i to the initial state, and C _B is the bit line parasitic capacitance added to bit lines B _i and _i .

FIG. 3 shows a conventional memory cell using a MOS structure as the cell capacitance _CSO3 . At this time
Since the capacitance of the MOS structure has a threshold voltage, the gate electrode of the cell capacitor _CSO3 is connected to the highest voltage power supply _VDD used in this memory, and the source and drain electrodes are connected to the node S, which is as high as possible. It was used to store electrical potential. However, if this is done, fluctuations in the power supply V _DD will cause the potential stored at the node S through the cell capacitor C _SO3 to fluctuate, resulting in malfunction.

Therefore, recently we have used multilayer polysilicon technology,
In some cases, a capacitor having no threshold voltage is created between these polysilicon layers and used as a cell capacitor.
This memory cell is shown in FIG. Here, the cell capacitance _CSO4 is the same as an ordinary capacitance that does not have a threshold voltage, so the other electrode connected to the node S must be kept at a constant potential, and normally the potential fluctuations will not occur. This is the lowest ground potential.

In addition, in Figures 3 and 4, cell capacitance C _SO3 and C _S
All other parts have the same structure except for the structure of _O4 . That is, the gate of the selection gate GT is connected to the word line W, the drain is connected to the bit line B, and the source is connected to the node S. Also, the node S
The parasitic capacitance added to is expressed as C _S1 . Here, the total capacitance attached to node S consisting of the sum _of cell capacitance C _SO3 or C _SO4 and parasitic capacitance C
The following explanation will be given by replacing it with _S.

In FIG. 2, after the precharge circuits 60 and 60' are operated by the clock signal _P1 , when the word line selected by the Cell information stored in one of the many memory cells connected to lines B _i and _i is read out to the bit line to which that memory cell belongs, and the other bit line is read out by the reference potential generation circuit. Therefore, a potential between two high and low levels is generated on the bit line in accordance with the "H" and "L" levels of the cell information. For example, when word line W _j is selected, cell information of memory cell 20 is read out to bit line B _i , and bit line _i
A reference potential is generated by the reference potential generation circuit 21'. Conversely, when word line _Wk is selected, the cell information of memory cell 20' is read onto bit line _i , and a reference potential is generated by reference potential generation circuit 21 on bit line B _i . As a result, a slight potential difference is generated between the bit lines B _i and _i, which is determined by the capacitance division between the storage capacitance C _S of the memory cell and the parasitic capacitance C _B of the bit line. Here, the minute potential difference is amplified by activating the sense amplifier 30 by the clock signal P2. After that, the information on the bit line B _i is outputted through the input/output circuit 50 selected by the output signal PY _i from the Y decoder,
Reading of cell information is completed. Also, in writing, information is written to the bit line and memory cell through the input/output circuit 50.

FIG. 5 shows voltage waveforms at various parts when a conventional dynamic memory is driven by a normal driving method and word line W _j is selected. In order to drive a semiconductor memory with the conventional structure, first, the clock signal P1 is set to a low level and the word line W is driven.
The cell information of the memory cell 20 is read out to the bit line B _i by setting the potential of _j to a high level. At the same time, reference potential generation circuit 2 is applied to bit line _i .
1' generates a reference potential, so the sense amplifier 3 activated by the clock signal P2 absorbs the minute potential difference that occurs between B _i and _i as a result.
At that time, the potential of the bit line B _i was rewritten into the memory cell 20 as refreshed information. In this case, the minute potential difference △V read from the memory cell to the bit line
If the precharge potential of the bit line is V _BD and the storage potential at node S in the memory cell is V _SO , then C _S = C _SO3 + C _S1 or C _S = C _SO4 + C _S1 , so △V = (C _S /C _S + C _B )・(V _SO −V _BO ). Furthermore, if the potentials of nodes S representing "H" and "L" of cell information stored in a memory cell are V _H and V _L , then the read signal difference between "H" and "L" cell information is △ V _HL is △V _HL = (C _S /C _S +C _B )・{(V _H −V _BO )−
(V _L V _{B O} )}=(1/1+C _B /C _S )·(V _H −V _L ). Therefore, the cell information read signal difference ΔV _HL is approximately inversely proportional to the division ratio C _B /C _S between the parasitic capacitance C _B of the bit line and the storage capacity C _S of the memory cell.
The “H” information potential V _H and the “L” information potential V _L stored in the storage capacitor C _S in the memory cell
It can be seen that it is proportional to the potential difference (V _H - V _L ) between the two.

In the conventional transistor-type dynamic memory explained in detail using the figures from FIG. 1 to FIG. 5, a large number of memory cells are connected to one bit line, so the memory has a large capacity. As the number of memory cells increases, the number of memory cells coupled to the bit line increases, the parasitic capacitance C _B of the bit line increases, and the division ratio C _B / _{CS of the memory cell with respect to the storage capacitance C S also} increases. Then, as shown in the previous calculation, the cell information read signal difference ΔV _HL becomes very small because it is almost inversely proportional to the division ratio C _B /C _S . In order to compensate for this, it is sufficient to increase the potential difference (V _H - V _L ) between the potentials V _H and V _L of "H" and "L" cell information in the memory cell, but conventionally "H" cells The information potential V _H is determined to be slightly lower than the voltage of the power supply that supplies the highest voltage used in this conventional memory device, and the "L" cell information potential V _L is determined to be the ground potential. Therefore, it has been difficult to compensate for the increase in the division ratio C _B /C _S by increasing the cell information potential difference (V _H −V _L ). Therefore, as the power supply voltage used for this memory becomes lower, the potential V _H of "H" cell information in the memory cell becomes lower, so the read signal difference △V _HL from the memory cell becomes smaller, which is often used in high-sensitivity devices. A sense amplifier will be needed. This was a serious drawback of the conventional example.

An object of the present invention is to provide a semiconductor memory device that can increase the capacity without using a highly sensitive sense amplifier, and another object of the present invention is to provide a semiconductor memory device with a large storage capacity and a small chip area. It is another object of the present invention to provide a semiconductor memory device in which memory cell refresh intervals are long and the memory can be used with high efficiency.

According to the present invention, as shown in FIGS. 6 to 9, bit lines are arranged as rows and word lines are arranged as columns, and memory cells are attached near each intersection between the rows and columns. A first storage word line provided substantially parallel to the word line to form a pair with the word line.
and a second memory cell matrix, and a number equal to the number of the rows arranged in columns in which the first and second memory cell matrices are arranged on the left and right thereof, and each is connected to the corresponding bit line on the left and right, respectively. a sense amplifier, an X decoder that selects the word line and the storage word line as a pair, an input/output circuit that selectively inputs and outputs signals to the bit line, and a Y decoder that controls the input/output circuit. and,
In the semiconductor memory device, the memory cell includes at least one selection gate and one cell capacitor, a control terminal of the selection gate is connected to the word line, and a first input/output terminal is connected to the bit line. Connect the second input/output terminal to the first
and a second electrode of the cell capacitor is connected to the storage word line,
The signal level when selecting the word line is a first level of a high potential and a second level of an intermediate potential.
At the first level, when reading binary information expressed by the charge level stored in the capacitor, the selection gate is completely turned on and the potential of the bit line and the first electrode of the cell capacitor are connected. set to a potential that substantially equalizes the potentials;
The second level is set to a potential that makes the selection gate non-conductive when the potential of the bit line after activating the sense amplifier is at a high level, and makes the selection gate conductive when the potential is low; The potential of the storage word line is set to change from a low potential to a high potential when the word line is at the second level, and to change from a high potential to a resistive potential after the word line is in a non-selected state. did,
A semiconductor memory device is obtained.

The present invention mainly improves the latter of the selection gate and the information storage capacitor that constitute the memory cell, and when storing the potential of cell information "L" at the node S in the memory cell, the conventional cell information "H" and "L" cell information is stored in the memory cell by storing a potential lower than the "L" potential and maintaining the cell information "H" potential at the same potential as before. This succeeded in increasing the potential difference between the two.

The present invention will now be described in detail using typical examples to aid understanding.

FIGS. 6 to 9 show an embodiment of the present invention in the same manner as FIGS. 1 to 5.
Equivalent parts are given the same reference numerals for convenience of comparison.

FIG. 6 is a block diagram, and the difference from the conventional example shown in FIG. 1 is that instead of the power supply line for memory cells, storage word lines are connected in parallel to word lines W _i (j=1, 2, . . . , n). Z _j (j = 1, 2, ..., n) is newly installed, and although the X decoder 10 is not much different in appearance from the conventional X decoder (1 in Figure 1), it is always newly installed with a word line. The storage word line is changed so that two storage word lines are selected.

FIG. 7 is a diagram taken out of the i-th line of the circuit in FIG. 6, and corresponds to FIG. 2 of the conventional example. 7th
The embodiment of the present invention shown in the figure is different from the _conventional configuration shown in FIG _. That's true.

FIG. 8 is a diagram showing in more detail an example of the configuration of a memory cell suitable for the present invention, which corresponds to the memory cells 22, 22' of FIG. 7. This configuration differs from the conventional examples shown in FIGS. 3 and 4 in that the electrode of the cell capacitor C _SO8 , which was conventionally set to the power supply level or ground level, is connected to the storage word line Z, and the cell capacitor C _SO8 The structure is the same as the cell capacitor _CSO4 shown in FIG. 4, and is a capacitor structure without a threshold voltage.

FIG. 9 shows the operating waveforms of FIGS. 7 and 8, and corresponds to FIG. 5 of the conventional example.

Here, as an example, the read operation and cell information storage operation when the memory cell shown in FIG. 8 is inserted into the circuit shown in FIG. 7 are selected when the i-th row and j-th memory cell shown in FIG. This will be explained using the operating waveforms.

In the present invention, as shown in FIG. 9, the operation is the same as that of the conventional example until the sense amplifier 30 is activated by the clock signal P2 and the minute difference signal read out from the memory cell onto the bit line is amplified. . After this amplification operation is completed, the word line W _j is set to an intermediate level V _W ', that is, when the bit line level is high at this time, the selection gate GT is made non-conductive, and when the bit line level is low, the selection gate GT is made conductive. Set the level to the state. After that, when the storage word line _Zj , which has been kept at a low potential, is raised to a high potential, the potential at the node S in the memory cell rises due to the coupling of the cell capacitance _CSO8 . At this time, the increase ΔV' by the potential of the node S becomes ΔV'=V _Z /1+C _S1 /C _SO8 , where V _Z is the amount of change in the potential of the storage word line Z _j . However, this is true when the selection gate GT is non-conductive, and when the selection gate GT is conductive, this increase in potential △V' is absorbed by the bit line B _i and the potential at the node S remains at a low potential and does not rise. Here, the word line W _j is set to a sufficiently low level, the selection gate GT is rendered non-conductive, and cell information is stored in the storage capacitor C _S in the memory cell. At this time, the potential of the node S stored in the memory cell is higher than the conventional potential by △V' when the cell information is "H", and becomes the ground potential as before when the cell information is "L". There is. Therefore, at this point, it is already "H",
Although the potential difference of the "L" cell information has increased by ΔV', since the storage word line Z _j is still at a high potential, it is necessary to return it to its original potential. Therefore, when the storage word line Z _j is changed from a high potential to a low potential, the potential of the node S generated by the sense amplifier of the cell capacitance C _SO8 when the previously calculated storage word line Z _j changes from a low potential to a high potential A potential drop equal to the rise △V' occurs. Therefore, the potential of the cell information "H" stored at the node S in the memory cell is unchanged from the conventional one, and the potential V _L ' of the cell information "L" can be lowered by △V' than the conventional one. As a result, the potential difference between "H" and "L" cell information can be increased by ΔV'. However, the low level of the word line is set to a potential that makes the selection gate GT non-conductive even when the potential of the node S in the memory cell reaches V _L '.

Moreover, the X decoder 10 used in the present invention has 1
It is sufficient to have a configuration that outputs two signals with different timings for the set of X address signals X ₀ , X ₁ , ..., X _l , and the output of the conventional X decoder 1 is branched into two. It may also be a model like this. Alternatively, two conventional X-decoders may be provided, and each X-decoder may drive the word line and the storage word line separately.

As described in detail above, the present invention uses a capacitor whose cell capacitance does not have voltage dependence, which constitutes a memory cell, and drives the capacitor with a newly provided storage word line. The effect of increasing the potential difference between information "H" and "L" is obtained. Therefore, if it is sufficient to read a signal of the same size as before from a memory cell, the cell capacitance can be made smaller than before, and a large capacity can be achieved without using a particularly sensitive sense amplifier. It may be possible to think that it will be possible to reduce the chip area, and if the storage capacity of the memory device is fixed, then the chip area can be reduced. In addition, the potential difference between cell information "H" and "L" stored in the cell can be increased, so if there is a leakage current of the same level as before, the potential difference between cell information "H" and "L" can be increased. The refresh interval can be lengthened to the extent that is large. In other words, this can be interpreted as an effect of increasing the usage efficiency of the memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional semiconductor memory device, FIG. 2 is a block diagram showing the i-th row of the circuit in FIG. 1, and FIGS. 3 and 4 are diagrams showing a conventional memory cell. The circuit diagram shown in FIG. 5 is an operating waveform diagram of the conventional circuit. FIG. 6 is a block diagram showing an embodiment of the present invention, FIG. 7 is a block diagram showing the i-th line of FIG. 6, and FIG. 8 is a circuit diagram showing a memory cell of the present invention. FIG. 9 is an operational waveform diagram of the circuit of the present invention. In the figure, 1 and 10 are X decoders, 2 and 2'
is a memory cell matrix, 3 and 30 are sense amplifiers, 4 is a Y decoder, 5 and 50 are input/output circuits, 2
0, 20', 22, 22' are memory cells, 21, 2
1' is a reference potential generation circuit, 60, 60' are precharge circuits, W _j , W _k , W are word lines, B _i , _i ,
B is a bit line, Z _j , Z _k , Z are storage word lines, X ₀ , X ₁ , ..., X _l are X address signals, Y ₀ ,
Y ₁ ,..., Y _r are Y address signals, GT is a selection gate, C _SO3 , C _SO4 , C _SO8 are cell capacitances, C _B is a parasitic capacitance added to the bit line, and C _S1 is a parasitic distributed within the memory cell. capacity, respectively.

Claims (1)

[Claims] 1 A memory cell is arranged in rows and columns with bit lines as rows and word lines as columns, memory cells are attached to each intersection between the rows and columns, and storage word lines are provided almost parallel to form pairs with the word lines. the first and second memory cell matrices, and the number of rows arranged in columns in which the first and second memory cell matrices are arranged on the left and right sides and each is connected to a corresponding bit line on the left and right sides, respectively. An equal number of sense amplifiers, an X decoder that selects the word line and the storage word line as a pair, an input/output circuit that selectively inputs and outputs signals to the bit line, and controls the input/output circuit. a Y-decoder, the memory cell comprising at least one selection gate and one cell capacitor, a control terminal of the selection gate connected to the word line, and a first input/output terminal connected to the word line; is connected to the bit line, a second input/output terminal is connected to the first electrode of the cell capacitor, and a second electrode of the cell capacitor is connected to the storage word line. The signal level at the time of selection is two levels: a first level of high potential and a second level of intermediate potential, that is, the first level is the readout of binary information expressed by the charge level accumulated in the capacitor. At this time, the selection gate is made completely conductive and set to a potential that makes the potential of the bit line substantially equal to the potential of the first electrode of the cell capacitor, and the second level activates the sense amplifier. When the potential of the subsequent bit line is at a high level, the selection gate is set to a non-conductive state, and when the potential is at a low level, the selection gate is set to a conductive state. 1. A semiconductor memory device characterized in that the word line is set to change from a low potential to a high potential when the word line is at a level 2, and then change from a high potential to a low potential after the word line is in a non-selected state.