JPH01162296A - Dram - Google Patents

Abstract

PURPOSE:To reduce a load to an oxide film and to improve the reliability of an element by providing a means to boost a word line from supply voltage only when an row address strobe (RAS) cycle is completed. CONSTITUTION:The title device is equipped with a boosting means to boost the word line from the supply voltage only when the RAS cycle is completed. When voltage VWL of the word line is boosted from the supply voltage only at the time of completing the RAS cycle in this manner, the time in which the boosted high voltage is impressed to a gate oxide film, etc., becomes shorter, and the load to the oxide film is reduced. Thus, the destruction of insulation, etc., can be prevented beforehand, and further, the destruction of insulation with the lapse of time can be prevented also, and the reliability of the element can be improved widely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DRAM (dynamic random access memory), and particularly to a DRAM having boosting means on its word line.

[Summary of the invention]

The present invention provides a DRAM having a voltage boosting means for boosting a word line to a voltage higher than a power supply voltage.
By making it relevant only at the end of the AS cycle, the load on the oxide film etc. is reduced and the reliability of the device is improved.

[Conventional technology]

A DRAM having a configuration having memory cells shown in FIG. 4 is well known. That is, each memory cell 40 is
It is composed of an access transistor 41 and a capacitor 42. The gate of the access transistor 41 is connected to the word line W
One of the source and drain of access transistor 41 is connected to bit kIABL, and the other is connected to capacitor 42.

In a memory cell having such a structure, when writing to the capacitor 42 with the power supply voltage Vdd, a voltage drop equivalent to the threshold voltage V occurs in the access transistor 41, so it is necessary to boost the word line WL. arise. For this reason, it is known that some conventional DRAMs are provided with a bootstrap circuit as shown in FIG. 5, for example, as word line boosting means.

Briefly explaining a DRAM equipped with this bootstrap circuit, only one transistor 58 is selected and turned on by a signal from the decoder 54. Therefore, the word line 51 connected to the memory cell 52 and selected is connected to the connection line 57, but this connection line 57 has
A booster circuit 55 and its switching circuit 56 constituting a bootstrap circuit are connected, and when a word line is selected, a connection line 57 is connected to a voltage higher than the power supply voltage Vdd (for example, 5V) (for example, about 6 to 7V). ).

The booster circuit 55 has a capacitor 58, and has a signal ΦB
A high voltage (for example, about 8 to 9 cm) is generated. The switching circuit 56 generates a signal ΦWL' using a word line selection signal.

ΦWL′ connects the connection line 5 through the transistor 59.
The transistor 61 operates by discharging the transistor 7 or by raising the gate voltage of the transistor 61 using the capacitor 60.

Furthermore, to briefly explain the operation of the DRAM with reference to FIG. 6, initially, the RAS signal (row address strobe signal), the signal ΦWL', and the signal ΦB are
"level (high level; for example, power supply voltage Vdd),
The signal ΦWL' is at “L” level (low level: ground voltage GN
D).

At this time, the transistor 59 is in the on state, and the connection line 57 is set to the L" level. Next, the RAS signal falls, and the signal ΦB that generates the boosted voltage also goes to the L" level.
Change in level. Then, the word line to be selected is determined, and the voltage at one end of the capacitor 58 of the booster circuit 55 is also increased by the signal ΦB. and,
The booster circuit 55 outputs a high voltage of, for example, about 8 to 9 cm. Subsequently, the transistors 59 and 62 are turned off from the signals ΦWL' and ΦWL', and the connection line 57 is disconnected from the ground voltage GND, and the low voltage side electrode is connected to the booster circuit 55 while maintaining the potential difference of the capacitor 60.
The voltage is switched to be boosted by Therefore, connecting line 5
7 is raised to a voltage via a transistor 61 kept in an on state by the capacitor 60, and this voltage is applied to the voltage V of the word line 51 via a transistor 58.
This will increase Wt.

[Problem that the invention seeks to solve]

As mentioned above, in the RAM, for example, 4M bits 516M
Bits and their miniaturization have progressed, and the dimensions of the elements themselves formed on wafers have also become smaller.

However, in DRAMs having the above-described configuration, while the dimensions of the elements have become smaller, the power supply voltage has not necessarily become smaller. For this reason, for example, the electric field applied to the gate oxide film increases in inverse proportion to the reduction in the oxide film thickness, and as the word line 51 is boosted using the bootstrap circuit described above, further damage to the gate oxide film becomes a problem. becomes. In addition, even if the applied voltage is lower than the dielectric strength voltage, dielectric breakdown (TDDB; tim) due to long-term use can occur.
e dependent dielectric br
The problem of eakdown) will also occur, and the reliability of the device will deteriorate.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention aims to provide a RAM that reduces the burden on the oxide film and improves the reliability of the device.

[Means for solving problems]

In order to solve the above-mentioned problems, the DRAM of the present invention has the following features:
The present invention is characterized in that it includes a boosting means that boosts the voltage of the word line above the power supply voltage only at the end of the RAS cycle.

Here, "only at the end of the RAS cycle" means that the word line voltage is increased at the end of the RAS cycle, including at least when a rewrite operation is performed.

[Function] In the conventional DRAM using the bootstrap circuit described above, the voltage of the word line VIGIL in FIG.
Cycle time t IIA! When , there is a slight time lag, but the voltage is always boosted. However, in the DRAM of the present invention, as shown in FIG. 1 based on the embodiment, the word line voltage VWt is applied only at the end of the RAS cycle.
is boosted from the power supply voltage. Therefore, the time during which the boosted high voltage is applied to the gate oxide film etc. is shortened, and the burden on the oxide film etc. is reduced.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

The DRAM of this embodiment is equipped with a voltage boosting means that boosts the voltage of the word line above the power supply voltage only at the end of the RAS (row address strobe) cycle, which reduces the load on the gate oxide film, etc., and reduces the borrowing property of the element. can be increased.

First, the basic configuration will be explained with reference to FIG. 1, which is a waveform diagram.
In AM, when the RAS signal falls, the signal ΦWL for driving the word line falls, and the signal ΦW
Due to L, the voltages V and L of the word lines in any row also rise to the "H" level (for example, about 5 V) which is the power supply voltage Vdd. When the word line voltage VWL reaches the "H" level in this way, data is read from the memory cell and data is input to the sense amplifier, but no rewrite operation is performed yet. Since the word line voltage vwL during reading is rewritten with a high voltage as described later, even if it is at "H" level, it can be sufficiently sensed using a sense amplifier.

Next, at the rising edge of the ■τ signal at the end of the RAS cycle, the restore signal ΦRST is changed from the "L" level, which is the ground voltage GND, to the "H" level. Then, using this restore signal R3T, the voltage V of the word line is increased. “EH” which further boosts L from the “°°H” level
change to the level. Here, the potential difference between the "H" level and the "EH" level is, for example, greater than the dark value voltage V□ of the access transistor.By setting the voltage V.L of the word line selected in this way to the "EH" level, Even if writing is performed at a potential lowered by the threshold voltage V by the access transistor of the memory cell, a sufficient voltage will be applied to the capacitor.

Thereafter, the restore signal ΦRST changes from "H" level to "L" level, the word line voltage VWt changes from °"EH" level to H" level, and the word line voltage VWt changes from "■1" level. Then, the signal ΦWL becomes °
The word line voltage changes from the "L" level to the #Hn level, and the voltage 4L of the word line returns to the "L" level, thereby completing the writing by the boosted word line.

DR of this example having the configuration shown in such a waveform diagram
In AM, the word line voltage V. L is L, and signal ΦWL is L”
When the restore signal ΦR3T is at the "H" level, the level is not at the boosted "EH" level throughout the entire period, but at the "EH" level, which is boosted only during the period when the restore signal ΦR3T is at the "H" level.

For this reason, write characteristics equivalent to those of a boost type DRAM can be obtained, and at the same time, the load on the gate oxide film of the access transistor is reduced.
The dielectric breakdown and deterioration over time are also good, and the reliability of the device is improved.

DRAM of this embodiment having the basic configuration as described above
For more specific examples, see Figures 2 and 3.
This will be explained with reference to the figures.

FIG. 2 shows the circuit configuration of the DRAM. memory cell 2
is composed of an access transistor 3 whose gate is connected to the word line l, and a capacitor 4. Data is stored in the capacitor 4 and read out to the bit line BL via the access transistor 3. Although not shown in the figure, the memory cells 2 are arranged in a matrix.

A word line 1 for selecting one row of memory cells 2 arranged in a matrix is connected via a selection transistor 22 to a connection line 13 commonly used by each word line. The gate of the selection transistor 22 is connected to the decoder 21 via a transistor 25. This decoder 21 is supplied with an address signal and selects a word line based on the address signal. The selection is performed by turning on the transistor 22. Further, the decoder 21 connects the unselected word line to the ground voltage GND through the transistor 24 via the inverter 23 .

The connection line 13 is commonly used for each word line, and especially in the DRAM of this embodiment, supplies a particularly boosted voltage at the "' E H" level only at the end of the RAS cycle. The boost circuit as the boost means drives a boost capacitor 10, an inverter 11.12 driven by the restore signal ΦR3T, a 2MO3) transistor 14 whose gate is similarly supplied with the restore signal ΦR3T, and a word line. PMOS transistor 15. controlled by signal ΦWL. NMO3) transistor 16.

Here, to further explain this booster circuit, one terminal of the booster capacitor 10 is connected to the connection line 13, and the other terminal is connected to the output side of the inverter 11. This boosting capacitor 10 may be about one-third the size of a conventional capacitor if the voltage to boost the word line is, for example, about 2V. The inverter 1
The output side of the inverter 12 is connected to the input side of the inverter 1.
The input side of the inverter 12 has a beam store signal ΦR3.
T is supplied. The PMO3) transistor 14 has its gate supplied with the restore signal ΦR3T, and its source supplied with, for example, the power supply voltage Vdd. This 2MO
3) The drain of the transistor 14 is connected to the source of the PMO3) transistor 15, and the drain of the 2MO3) transistor 15 is connected to the drain of the NMO3) transistor 16. The ground voltage GND is supplied to the source of the NMO3) transistor 16, and the above PMOS)
The transistor 15 and its NMO transistor 16 constitute a CMOS inverter whose gate is supplied with the signal ΦWL, and an output signal appears on the connection line 13.

Next, an example of the operation of the DRAM according to this embodiment will be explained with reference to the waveform diagram in FIG.
Then, the RAS signal falls and the RAS cycle starts. At this time, the signal ΦWL for selecting the word line is “H”.
” level (for example, power supply voltage Vdd), word line 1
The voltage VWL is at the "L" level (for example, the ground voltage GND). Further, the bit line BL (bit) is at an intermediate level as a pair of bit lines are equalized, and the restore signal ΦR3T is at the "L" level. At time t0, the RAS signal falls, and the address signal (ll
The ROW address is determined by ddress). Then, at the time, the signal ΦWL for selecting the word line based on the determined ROW address is "°H".
The word line voltage VWL also changes from the "L" level to the "'H" level based on the change in the signal ΦWL.

Referring again to the circuit shown in FIG. 2, first, at time t0, the signal ΦWL is at the "H" level, the restore signal ΦRST is at the "L" level, and the PM
OS transistor 14. The NMOS transistor 16 is turned on, and the PMOS transistor 15 is turned off. Therefore, the voltage of the connection line 13 of the boost capacitor 10 and the voltage of the inverter 11 side of the capacitor IO are set to L'' level.
The outputs of all of the transistors 24 in all rows are turned on, and the voltages V and I of each word line are
L is set to "Lo" level. Next, at time t1, the signal ΦWL changes to "L" level. Then, the decoder 2
1 selects a certain word line 1, and the transistor 22 connected to the selected word line is turned on. At the same time, the 2MO3) transistor 15 is turned on and the NMOS transistor 16 is turned off, the voltage on the connection line 13 side of the boosting capacitor 10 changes to the "■1" level, and the potential of the connection line 13 also rises. This leads to the selected word line and the word line voltage v@.

The level also changes from the °°L" level to the "°H'° level.

After such word line selection is performed, as shown in FIG. 3, a difference signal of data in the memory cell appears on the bit line (BIT) at time Lx. Next, at time t, the sense amplifier is driven, and the difference signals are mutually amplified between the pair of bit lines. Also, before and after this sensing operation,
For example, the write enable signal WE is “L” at time tw+.
level (indicated by the broken line in the figure), then the DRAM performs a write operation, and the data input signal D
The value of i h can be taken in, and depending on the taken value, the data on the bit line can be inverted or left unchanged at time t@t. Note that when the signal WE remains at the "H" level, a write operation that involves data capture is not performed. Also, at the time, the CAS signal (column address strobe signal) falls, and at the time, the CAS signal rises. The address signal at that time determines the column address, and when reading or writing, an operation is performed based on the already selected word line and the determined column address.

Next, at time t, the RAS signal changes from the "L" level to the "H" level.
" level, and the RAS cycle ends. With the end of this RAS cycle, the data retention operation is performed. First, the restore signal ΦRST rises to the time t,
The signal rises from the "L" level to the "H" level. Then, in the circuit of FIG. 2, the PMOS transistor 14
is turned off, and then the terminal of the boosting capacitor 10 on the inverter 11 side is raised from the L'' level to the °°H'' level. At this time, the boost capacitor 10 is
Since there was a potential difference greater than or equal to the threshold voltage V between both ends, the voltage at the terminal on the connection line 13 side of the boosting capacitor IO was raised from the HI+ level to a higher voltage. This is transmitted to the word line, and at time t8, the word line voltage VWt is boosted from the "H" level, which is the power supply voltage Vdd.
This will push it up to the "EH" level.

In this way, the word line voltage v, 1. When the voltage rises to the "EH" level, even if a voltage drop equivalent to the dark value voltage V occurs due to the access transistor 3 of the memory cell 2, the capacitor 4 is easily connected to a voltage approximately equal to the power supply voltage Vdd. Can be rewritten. That is, even if the word line voltage is not boosted for the entire selection time as in the conventional case, rewrite characteristics equivalent to those obtained by sufficiently boosting the voltage can be obtained.

Therefore, the burden on the gate oxide film and the like is also reduced.

Next, at time t, the restore signal ΦR3T changes from "H" level to "L" level, and accordingly, at time t1
At °, the word line voltage VIII also changes from the “EH” level to “
H" level. Here, the time between time L8 and time is the time required for rewriting.
At ++, the signal ΦWL changes from the "L" level to the "H11" level, and at time tI! The word line voltage V@t also becomes “H”.
" level changes from "L" level to end the rewrite operation. Thereafter, for example, at time t's, equalization of the bit line etc. is performed.

In the DRAM of this embodiment that operates in this manner, first, the voltage at the time of rewriting is boosted by a boosting means, and therefore it is possible to compensate for the voltage drop corresponding to the dark value voltage V in the access transistor. , it is possible to obtain data retention characteristics equivalent to those provided with a conventional Pootstrap circuit (see FIG. 5).

In particular, in the DRAM of this embodiment, the word line is “H”.
The only time the voltage is raised above the "H" level is the time related to rewriting, for example, about 10 to 20 n5ec. This is because conventionally the voltage was always raised above the "H" level for a period of about 100 to 120 nsec. The stress on the gate oxide film and the like is alleviated compared to the conventional structure, and dielectric breakdown and the like can be prevented, and dielectric breakdown over time can also be prevented. Therefore, the reliability of the element is greatly improved.

In addition, one equipped with a conventional Pootstrap circuit (fifth
(see figure), the number of circuit elements increased, and the boosting capacitor also needed to be larger. However, in the circuit shown in FIG. 2, it is only necessary to boost the voltage from the power supply voltage Vdd instead of from the ground voltage GND, so the configuration is simplified and the area occupied is small (
Therefore, for example, the number of boost capacitors 10 can be reduced to about one-third. Furthermore, in the circuit shown in FIG. 5, the voltage at the gate of the transistor 61 becomes a high voltage, exceeding the power supply voltage Vdd+2 dark value voltage, but in the circuit shown in FIG. It can be solved.

Furthermore, in the DRAM equipped with the conventional putot strap circuit shown in FIG.
However, in the DRAM of this embodiment, the voltage is boosted only at the end of the RAS cycle, and no problem such as voltage drop occurs even during a long RAS cycle. .

Note that the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit thereof.

〔Effect of the invention〕

Since the DRAM of the present invention has a configuration in which the voltage is increased only at the end of the RAS cycle, it is possible to prevent dielectric breakdown and the like, and also to prevent dielectric breakdown over time.

Therefore, the reliability of the device can be significantly improved. Further, it is possible to simplify the circuit configuration, and it is also possible to prevent problems caused by long RAS cycles.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the basic configuration of an example of the DRAM of the present invention, FIG. 2 is a circuit diagram for explaining its specific circuit configuration, and FIG. A waveform diagram for explaining the operation, FIG. 4 is a circuit diagram of a general RAM memory cell, FIG. 5 is a circuit diagram of a DRAM with a conventional bootstrap circuit, and FIG. 6 is a circuit diagram of a DRAM shown in FIG. 5.
FIG. 3 is a waveform diagram for explaining the operation of M. 1... Word line 2... Memory cell 3... Access transistor 10... Boosting capacitor 11.12... Inverter 13... Connection line 14.15... PMOS transistor 16... N.M.
O3I - Transistor RAS...Low address strobe VWL...Word line voltage ΦR3T...Restore signal Patent applicant Akira Kobe, patent attorney representing Sony Corporation (and 2 others)

Claims (1)

[Claims] A DRAM equipped with boosting means that boosts the word line voltage above the power supply voltage only at the end of a RAS cycle.