JP3107841B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to an output circuit thereof.

2. Description of the Related Art In a semiconductor memory device, a current at an output portion is large, and when the current is turned on and off in accordance with read data, there is a possibility that a potential of a power supply circuit fluctuates. Particularly, in recent semiconductor memory devices, there is a tendency that the output is increased in number of bits as the storage capacity increases, and 4, 8, 9, or 16
A multi-bit output of each bit has been developed.
If a large number of bits have the same data 1 and 0 in such a multi-bit storage device, charges remaining at many output terminals will be charged / discharged all at once, and the V _CC / _VSS power supply line A large current flows to fluctuate the potential of the power supply line, causing a malfunction of the device.

[0003]

2. Description of the Related Art FIG. 5 shows an example of a conventional output circuit. 5A to 5C show an N-bit parallel output type, in which Dout Buf
1 to N are the N output data buffers. C ₁ and / C _{1 to} C _N and / C _N are the inputs of these buffers, D ₁
In the / D ₁ to D _N and / D _N is the output, all of which are complementary. These outputs D ₁ and / D ₁ to D _N and / D _N is n connected in series between the output stage, the power supply V _cc and ground V _SS
It applied to the gates of the channel MOS transistor Q ₁₁ and Q ₁₂ to Q _N1 and Q _N2.

Accordingly, in FIG. 5A, the input C ₁ is at the H level, / C ₁ is at the L level, and the clock (enable signal)
When the output D ₁ of the output data buffer Dout Buf1 activated in phi ₁₁ is H, / D ₁ is at L, the transistors Q ₁₁
But on, Q ₁₂ is turned off, the input C _1, the output Dout 1 for / C ₁ is H. The same applies to the output Dout N for other inputs, for example, C _N and / C _N , and C _N = H, / C _N
= L, Dout N = H. Conversely, C _N = L, / C
_N = H, the output D _N are L of Dout BUFn activated in phi _11, / if D _N = H, Q _N1 is off, Q _N2 is on, Dou
t N is L.

Outputs Dout1 to DoutN are output to the outside through output terminal pins. In a multi-bit semiconductor memory device, a so-called I / O common in which input terminals and output terminals are shared to reduce the number of terminal pins. Often takes the form.
I / The O common output terminal, when data is output holds the potential which has been externally supplied immediately before (at the time of reading) (write voltage), the output stage transistor Q ₁₁ charges determined by the potential Q ₁₂ to charge / discharge all at once via the ON of Q _N1 and Q _N2 . At this time, a large amount of noise is applied to the power supply lines V _CC and V _SS , which may cause a malfunction of the semiconductor memory device. In recent years, since the number of bits has been further increased to × 8 and × 16, the risk of malfunction has been increasing.

FIGS. 5 (b) to 5 (d) show an output section circuit which takes measures against this malfunction. In (b), the power supply circuits V _CC1 and V _{SS1 of the} output stage transistors Q ₁₁ and Q _{12 to} Q _N1 and Q _N2.
V _CCN, by inserting a resistor R _C1 and R _S1 to R _CN and R _SN to V _SSN separately from the memory power supply V _CC, V _SS, memory power supply V _CC,
A capacitor C is connected between V _SS . Also depends on the resistor R _C1 R _S1 ~R _CN and R _SN and capacitor C the charging / discharging current through what is on the output terminal transistor Q ₁₁ With this configuration Q ₁₂ to Q _N1 and Q _N2 flow Fluctuation in the memory power supplies V _CC and V _SS is reduced by the smoothing action, and memory malfunction can be avoided. However, this method is not effective unless a certain large resistor or capacitor is used, and another problem occurs in the use of a large resistor or capacitor.

FIG. 5C shows an output data buffer Dout.
Clocks φ ₁₁ to φ _N1 for activating Buf ₁ to _N are sequentially delayed, and these data buffers are sequentially operated. FIG.
(A) shows an operation waveform. The enable signals φ _{11 to} φ _1N sequentially rise, and the outputs Dout _{1 to} Dout N appear sequentially.
In this way, the charging / discharging currents flow sequentially and do not flow simultaneously, so that the influence on the power supplies V _CC and V _SS is small. A particularly problematic power supply variation is a power supply variation of V _SS , as shown in the figure, and only a small floating is repeated each time Dout appears. For this reason, a memory malfunction can be avoided. However, in this method, if the sum of the delay time of each bit and the delay time are all the same and τ is set as τ, the access time becomes large by τ (N−1). Not a good idea.

As shown in FIG. 5D, there is also a conventional circuit for applying an intermediate potential to an output terminal at the time of output. In this circuit, the clock φ ₁₂ enters immediately before the output, and the transistors Q ₂₃ and Q ₂₄
Is turned on, and an intermediate potential between the power supplies V _CC and V _SS is output to the output terminal Dou.
Give to t. Output Dout (here using the same reference numerals terminal and its output) is entered clock phi ₁₁ is Dout Buf
Output N ₁₁ , N ₁₂ becomes H, L or L, H, and the transistors Q ₂₁ , Q ₂₂ turn on, off or off, and turn on to H, L. Is performed from the intermediate potential, it is faster than if it is performed from the opposite L, H or H, L, and therefore the access time is shorter. However since the transistor Q ₂₃ and Q ₂₄ to the intermediate potential generating simultaneously turned on, the power supply to the V _SS flows from the power supply V _CC through these transistors,
This gives noise to the power supply. FIG. 6B shows the operation waveform of this circuit. D when the clock φ ₁₂ rises
out becomes the intermediate potential, the input then clock phi ₁₁ is I rise C, it becomes L level by the potential present embodiment in accordance with the / C. Noise to the power supply V _SS and when phi ₁₂ climbed standing, resulting twice when the phi ₁₁ climbed standing. If this is used in a device having a multi-bit (N-bit) configuration, a large number (N) of transistors Q ₂₃ and Q ₂₄ will be provided, so that the power supply noise due to the DC path cannot be ignored. Also, transistors Q ₂₃ and Q
There is also a problem that ₂₄ source and drain capacitances are attached to the output terminal, and the capacitance of the terminal pins becomes large.

[0009]

As described above, in the conventional method, the charge / discharge current of the charge at the I / O terminal pin causes power supply noise at the time of data output, especially in a multi-bit configuration. There is a problem that memory malfunction occurs.

In order to cope with this problem, the power supply line of each output section circuit is separated from the main power supply (memory power supply) line in a wiring pattern, a resistor is inserted into each of them, and a capacitor is connected to the main power supply line. However, this cannot be seen without inserting some large resistors and capacitors.

In addition, a signal for enabling each output unit circuit is made independent, and each output unit circuit is staggered with a delay. In this method, the access time is determined by the delayed output enable signal. Therefore, it is not advisable to increase the access speed even in a multi-bit configuration.

There is also a method in which the output terminal is set to an intermediate potential immediately before output. However, there are problems such as a current flowing through the intermediate potential generating circuit disturbing the power supply and a parasitic capacitance of the intermediate potential generating circuit being attached to the terminal.

It is an object of the present invention to improve such a point and to reduce noise on a power supply line without delaying access and causing no circuit malfunction.

[0014]

The potential generating circuit VG1~VGN for generating a lower power supply voltage V _cc potential provided by the present invention as shown in SUMMARY OF THE INVENTION FIG. 1 (a), the transistor Q ₇₁ to Q _7N this output the output stage transistor Q ₁₁ via the Q ₁₂ ~
It is connected to the output terminal Dout 1~Dout N of Q _N1 and Q _N2. Transistor Q ₇₁ to Q _7N is controlled by the clock phi _12, on the previous data output, turned off otherwise.

As is the case throughout the drawings, the same parts as those in the other drawings are denoted by the same reference numerals. Therefore, Dout Buf1
N data output buffer, phi ₁₁ its activation clock (enable signal), C ₁ and / C ₁ -C _N and / C _N input signals, D ₁ and / D ₁ to D _N and / D _N output Signal. The present invention can be applied to a 1-bit output in addition to the N-bit output as shown. In this case, one potential generating circuit and one transfer gate transistor may be used. Alternatively, only one potential generating circuit may be provided for the N-bit output, and this common potential generating circuit may be connected to the output terminal of the output stage transistor of each bit via a transfer gate transistor. 1B to 1D show specific examples of the potential generation circuit.

[0016]

According to the present invention circuit, the intermediate potential of the output voltage, for example, V _cc and V _SS potential generating circuit VG1~VGN for generating a lower power supply voltage V _cc potential, each bit through the transistor Q ₇₁ to Q _7N the output stage transistor Q ₁₁ of the Q ₁₂ ~Q _N1
To the output terminal Dout 1~Dout N of Q _N2, since added immediately before the data output, the output change is performed from the intermediate potential, the power supply V _cc, the voltage variation of the V _SS is relaxed, malfunction of the memory can be avoided .

[0017] The potential generating circuit is operating normally, since it will not make the connected DC path output immediately before the power supply V _cc, between V _SS, no power supply voltage variation due to the DC path generation. Also because normally is disconnected from the output terminal Dout 1 to N by the transistor Q ₇₁ to Q _7N OFF, I /
There is no increase in the parasitic capacitance of the O terminal pin. In addition, the access time is not increased because the operation is not staggered (the output change starts at an intermediate potential, so that access is quicker. In addition, since the influence on the power supply is reduced, the driving capability of the output stage transistor is increased. In this respect, the access speed is also increased), and there is no problem that the power supply voltage of the output stage circuit is reduced because it is not the RC insertion, and that the IC is difficult to be formed by inserting the large capacity C.

[0018]

FIG. 1 shows a specific example of potential generation circuits VG1 to VGN.
(B) to (d). (B) In the power supply V _cc, and transistor Q ₈₁ between V _SS resistors R _1, R ₂ connected in series, R
₂ and to connect the capacitor C ₁ in parallel, the transistor Q ₈₁
A potential generating circuit is configured such that a clock φ ₁₃ is applied to the gate of the inverter via the inverter I. The clock φ ₁₃ is an activation signal for the device, for example, RAS (Row Addr
ess Strobe). Therefore device (memory chip)
There is as long as the transistor Q ₈₁ that is operating on, to generate a voltage divided by approximately resistors R _1, R ₂ the voltage applied to the power supply V _cc from the node N. This intermediate voltage is applied to the connection point (output end Dout 1) to the output stage transistor Q _11, Q ₁₂ when the transistor Q ₇₁ by the clock phi ₁₂ is turned on. The configuration and operation of the other potential generation circuits VG2 to VGN are the same.

FIG. 1 (d) are those obtained by replacing the resistor R ₂ at the transistor Q ₈₂ of the diode connection, other configurations and operations are the same as FIG. 1 (b). FIG. 2A shows the operation waveforms when FIGS. 1D and 1B are used as the potential generating circuit in FIG.

Inputs C ₁ and / C _{1 to} C _N and / C _N are entered,
Then the transistor Q ₇₁ to Q _7N is turned on when the one-shot pulse of the clock phi ₁₂ enters the output stage transistor Q
Is to ₁₁ and Q ₁₂ to Q _N1 and Q _N2 of the output terminal Dout 1~Dout N V _cc / 2 is applied to an intermediate potential present example produces the potential generating circuit VG1～VGN. At this time, if the potential of the output terminal is V _cc , it drops to V _cc / 2, and if it is V _SS , V _cc / 2
, And at this time, a charge / discharge current flows. Power V _cc due to the charge and discharge current, there is a potential change of the V _SS, which the resistance of the circuit of the current in the large eg Q ₈₁ R ₁ and Q _71,
And the resistance of R ₂ and Q ₇₁ can be reduced. For example, these resistors are connected to the transistor Q ₁₁
And Q _12, 4 times the resistance ..., can be dropped eight times, the noise level by the ...... 1 / 4,1 / 8. Capacitor C ₁ has the effect of reducing the charge / discharge flow affecting the power source potential.

[0021] Thereafter the clock phi ₁₁ rises, on the output stage transistor Q ₁₁ and Q ₁₂ to Q _N1 and Q _N2 produce output data buffer Dout Buf1～N is corresponding to the input enabled off. As a result, the outputs Dout1 to Dout rise to _Vcc if they are at the H level, and fall to _Vss if they are at the L level. Since this is performed from the intermediate potential _Vcc / 2, it is quick. Although flows this time charging / discharging current, to half compared to the case since it is from V _cc / 2 from V _SS from V _cc and V _cc to V _SS.

In FIG. 1C, the potential generating circuits VG1 to VG
N is composed of one diode-connected transistor Q ₉₁ . Therefore, the intermediate potential generated by this circuit is almost at the V _SS level. The operation waveform of the circuit of FIG. 1A using this is shown in FIG. In this case, as shown also first input C ₁ and / C ₁ -C _N and / C _N enters, then the clock φ
Enters ₁₂ . This transistor Q ₇₁ to Q _7N is turned on, the potential generating circuit output voltage to the output terminal D of VG1~VGN
1 to Dout N. In FIG. 1C, this output voltage is V _SS , and therefore, the output terminal at the H level is pulled down toward this V _SS , and the output stage at the L level is left as it is. become. Then the output data buffer clock phi ₁₁ rises becomes active, the output Dout 1～Dou
tN rises / falls to H or L according to the input.

In this circuit, all the output stages are pulled down to the V _SS side immediately before the output. Therefore, when there are many outputs at the H level, the charging current becomes large and the voltage drop of the _Vcc power supply is large. The voltage drop on the _Vcc line does not have as bad an adverse effect on the memory operation as the voltage rise on the _Vss line. If the voltage is pulled down to the V _SS side, the discharge current at the time of data output is reduced, so that the voltage rise of the V _SS line is reduced, and a memory malfunction is avoided.

The clock phi ₁₃ when the device is in the standby state disconnected potential generating circuit from the power source is intended to eliminate the current the voltage generating circuit consumes, FIG. 1 (c)
The clock φ ₁₃ is not required for the case where the output terminal is simply pulled down to V _SS as shown in FIG.

FIG. 3 shows the configuration of the memory. As shown, it comprises a memory cell array 10, a row decoder 12 for selecting its word line, a column decoder 14 for selecting a bit line, a sense amplifier and I / O gate 16, a data input buffer 18, and a data output buffer 20. It also includes clock generators 22, 24, 26, mode control 28, address buffer and predecoder 30, refresh address counter 32, and substrate bias generator 34. .. / WE are write enable bars, Din is input (write) data, Dout is output (read) data, / RAS is a las bar, / CAS is a cas bar, and A ₀ , A ₁ , A ₂ ,... It is. The present invention relates to an output stage after the data output buffer 20 and I / O terminals.

FIG. 4 shows a circuit example of a multi-bit data output unit. In this example, 4-bit simultaneous output is performed, and there are four pairs of data buses DB and / DB, which have four sense buffers SBuf and four output data buffers Dout B.
uf is connected. The cell array has a large number of word lines WL and bit line pairs BL and / BL. At the intersection of these, there is a memory cell MC. Each of these bit line pairs BL and / B
Sense amplifiers SA are connected to L, and four of these are connected to four pairs of data buses via column gates CL.

[0027]

As described above, according to the present invention, it is possible to prevent a memory malfunction due to a power supply fluctuation due to terminal charging / discharging at the time of data output, and to limit the output transistor in consideration of the power supply fluctuation. Current driving force can be improved, thereby contributing to an increase in access speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output unit of a semiconductor memory device according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of FIG.

FIG. 3 is a block diagram illustrating a configuration of a memory.

FIG. 4 is a block diagram illustrating a configuration of an output unit of the memory.

FIG. 5 is a circuit diagram showing an example of a conventional output unit.

FIG. 6 is a circuit diagram for explaining the operation of FIG. 5;

[Explanation of symbols]

Q ₁₁ and Q _12, a pair of transistors ...... output stage VG1, ...... potential generating circuit Dout 1, ...... read output

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-293786 (JP, A) JP-A-2-161688 (JP, A) JP-A-62-159910 (JP, A) JP-A-2- 264314 (JP, A)

Claims (3)

(57) [Claims] 1. A semiconductor memory device comprising: a pair of transistors connected in series between a power supply and a ground, wherein a read output is generated from a series connection point of the pair of transistors according to read data, wherein And a first transistor that is turned on and off by a device activation signal that activates the semiconductor memory device, and a potential intermediate between a power supply voltage and a ground potential during a period in which the first transistor is closed. And a control clock independent of the device activation signal , wherein an output terminal of the potential generation circuit is connected to the series connection point.
A second transistor which is turned on / off by a signal and is closed only during a period immediately before data output. 2. The semiconductor memory device according to claim 1, wherein the intermediate potential between the power supply voltage and the ground potential is a half of the power supply voltage. 3. A semiconductor memory device comprising: a pair of transistors connected in series between a power supply and a ground; and generating a read output from a series connection point of the pair of transistors in accordance with read data. A potential generating circuit configured to generate a potential close to the ground potential, and a second transistor having an output terminal of the potential generating circuit connected to the serial connection point and closed only during a period immediately before data output. A semiconductor memory device characterized by the above-mentioned.