JPS59163835A - Semiconductor device - Google Patents

Abstract

PURPOSE:To hold low level output of a semiconductor device at a constant by a method wherein the plural number of pieces of FETs of the same load current for load elements, and the same number of enhancement type insulating gate FETs of the same length and width of gates for driving elements are contained in a logic gate circuit. CONSTITUTION:An inverter circuit formed by using respectively one piece of a load transistor 12 and a driving transistor 14 out of transistors of the plural number of pieces of fundamental cells is provided with an inverter input terminal 8 and an inverter output terminal 9. By connecting in parallel with the driving transistors of the same number corresponding to the number of the load transistors to be used for security of a speed, constant low level output can be obtained without changing the design of the driving transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which output level characteristics are made constant using a master slice method.

[Prior art]

Recently, as the scale of integrated circuits has increased, the master slice method has been attracting attention as a method for integrating logic circuits. In the master slice method, when realizing the integration of required functions, the designer prepares basic circuit functions such as NAND function, NOR function, flip-flop function, etc. in advance, and the designer By combining functional circuits, a complete logic function can be constructed, and when realizing an integrated circuit, only metal wiring is placed on a substrate on which basic elements such as transistors and resistors are regularly arranged (this is called the master slice base). This is a cutting method that designs according to individual desired characteristics.

Large-scale integrated circuit using mask slicing method (hereinafter referred to as 1)
Compared to LSI design using conventional design methods, the design of an LSI (referred to as LsI) is that the basic circuit functions described above are already designed as a single unit and are a prototype source, so its performance can be sufficiently predicted. Design accuracy can be improved. Furthermore, LS
When converting to I, design using the master slice method is usually a design of only metal wiring and does not include the design of elements such as transistors, which reduces design errors, reduces design man-hours, and improves design efficiency. The period can also be shortened. Furthermore, CA, I) method can be easily applied to design, and design accuracy can be improved.

Figure 1 is a schematic diagram of the basic cell of the conventional master slice base, and Figure 2 (al (bl) is a diagram of the conventional master slice configuration. The master slice base of the master slice method is standardized as shown in Figure 1. drive transistor 4,
A plurality of basic cells including several basic elements such as a load transistor 2 and a connection terminal 3.5 are further included, and the basic cells 1 and connection wiring 6 are combined and arranged in an array as shown in FIG. 2(a). Or, as shown in Figure 2 (bl), construct a block 7 containing several basic cells 1, and connect the block 7 and the connection wiring 6.
It is common to combine them to form a block-like array. According to a conventionally known method, the basic cell l shown in FIG.
has m load transistors 2 and n drive transistors 4.
(m\1.n\1.n:)m). Once the basic design of the master slice is completed, the transistor dimensions of the load transistor 2 are uniquely determined by the load current value, and the transistor dimensions of the drive transistor 4 are similarly determined uniquely. FIG. 3 shows the basic circuit of the inverter. The third
The inverter circuit shown in the figure can be designed to have a constant inverter ratio, and the low level output from the inverter output terminal 9 when the inverter input terminal 8 is at a high level can also be designed to have a constant potential. However, in the design using the master slice method, two or more load transistors 2 of the basic cell 1 are connected in parallel to increase the current supply capacity of the load transistors.
Since it is possible to increase the rise speed of the inverter output terminal 9, depending on the design, the load current may be selected to be an integral multiple of the load current of the basic inverter circuit. It has the disadvantage that it does not become sufficiently low. Figure 4 (al, (
b) , (C1 is a circuit diagram showing a conventional basic cell connection method, which is composed of the basic cell 1 shown in Fig. 1. As shown in Fig. 4 (al), one load transistor 2 is Figure 4 shows the inverter circuit when used (bl, (C1
When a plurality of load transistors 2 are used in parallel as shown in FIG. 7, the voltage at the terminal 9 when the trace inverter output terminal 9 is at a low level as shown in FIG. 7 changes depending on the load current value. FIG. 7 is a low level output characteristic diagram of a conventional inverter circuit. That is, as the current flowing through the drive transistor 8 necessary to keep the output terminal 9 at a low level increases, the low level output as the source-drain voltage of the drive transistor 8 increases.

Therefore, in the conventional cell configuration, the ratio of the drive transistor 4 deviates from that of the basic inverter circuit, resulting in an increase in low level output.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a master slice type semiconductor device that can maintain a constant low level output and secure an operating margin.

[Features of the invention]

The present invention provides a master slice type semiconductor device including:
The logic gate circuit includes a plurality of field effect transistors with equal load currents 5- for the load elements, and enhancement type insulated gate W field effect transistors for the drive elements with equal gate lengths and gate widths. A semiconductor device is characterized in that it includes the same number of field effect transistors.

〔Example〕

The present invention will be explained in detail below based on examples. FIG. 5 is a diagram showing the configuration of a basic cell according to an embodiment of the present invention. As shown in the figure, a load transistor 12, a drive transistor 14'
! il- each containing 3 load transistors, 12
and drive transistor 14 each have the same characteristics.

FIG. 6(al~(C1) shows a circuit diagram of an inverter circuit according to an embodiment of the present invention, in which FIG. 6(a) shows a load transistor 12 and a drive transistor 14 among a plurality of transistors of a basic cell. The inverter circuit is formed using one inverter circuit, and 8 is an inverter input terminal, and 9 is an inverter output terminal.

6-Figure 6 (bl is the one in which two load transistors 12 are connected in parallel to increase the operating speed, two drive transistors 14 are also connected in parallel at the same time, and the input terminals are short-circuited. The inverter ratio in this case is 61st.
The inverter ratio is the same as the inverter ratio that uses one load transistor 12 and one drive transistor 14 in the case of m1 (at).

Figure 6 (C1 is the one shown in Figure 6 (BL) in which three load transistors 12 are connected in parallel to make the operation speed even faster than in the case of BL.
Three transistors 14 are connected in parallel, and the input terminals are short-circuited. In that case, the inverter ratio will be the same as the inverter ratio of the configuration shown in diagram g6+al.

As described in 2 below, according to this embodiment, even if the load current changes, the low level output can be kept constant by connecting a plurality of drive transistors in parallel according to the load current. , it is possible to secure an operating margin.

FIG. 8 is a diagram showing the low level output characteristics of an embodiment of the present invention, and shows a situation where the low level output is kept constant even with changes in load current.

Incidentally, the circuit configuration of a general integrated circuit is as shown in FIG. That is, it consists of an input/output bumper section circuit 93 and an internal circuit section 92, and the internal circuit section 92 further consists of a transfer gate circuit section 95 and a logic gate circuit section 94. The tenth circuit shows a three-person Carratch circuit, and according to the figure, the transformer 7 agate circuit section includes two transfer gate transistors 101, and the logic gate circuit section includes two inverter circuits 102. The method of the present invention described above is applicable to logic gate circuit sections. For this reason, taking an Exclusive -01% (hereinafter referred to as Ex-OR) circuit as an example,
The Ex-OR circuit shown in FIG. 11 can be constructed in the form of an inverter circuit as shown in FIG. 12. In the circuit shown in Fig. 12 above, the circuit configuration of each inverter is designed to ensure speed with respect to the magnitude of the output load of the inverter, as explained in the inverter circuit configuration for keeping the low level output constant. The low level output of the inverter can also be kept constant by using the same number of load transistors and drive transistors.

〔Effect of the invention〕

It is clear from the above explanation that if the same number of 9-load transistors and drive transistors of the inverter circuit are prepared in the cell configuration underlying the master slice, the desired speed can be secured depending on the number of 9-load transistors used. By connecting the same number of drive transistors in parallel,
A constant low level output is obtained without changing the design of the drive transistor, and any logic gate integrated circuit can be realized by a collection of such individual inverter circuits. In particular, in the case of design using the master slice method, the low level output of the inverter circuit can be made constant by changing only the metal wiring process, ensuring an operating margin and reducing design man-hours.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of a basic cell 9- on the base of a conventional master slice; A configuration diagram of a master slice, FIG. 3 is a basic circuit diagram of an inverter, FIG. 4 (al(D) (C1 is a circuit diagram showing the basic cell configuration of a conventional master slice, and FIG. 5 is an embodiment of the present invention) A schematic diagram of the basic cell used in Figure 6 (
al(bl(Cl) is a circuit diagram of an inverter circuit according to an embodiment of the present invention, FIG. 7 is a low level output characteristic diagram of a conventional inverter circuit, and FIG. 8 is a low level diagram of an inverter circuit according to an embodiment of the present invention. Output characteristic diagram, Figure 9 is a circuit configuration diagram of a general integrated circuit, Figure 10 is a three-person Carracci circuit diagram,
Figure 1 is the circuit diagram of Exc Ius 1ve-OR, 12th
The figure shows Exclusive-O configured with an inverter circuit.
It is an R circuit diagram. 1.11... Basic cell, 2.12...
Load transistor, 3, 5... Connection terminal, 4.
14... Drive transistor, 6... Connection wiring, 7... Block, 8... Inverter input terminal, 9... Inverter output terminal ,
92... Internal circuit diagram, 93... Input/output buffer circuit, 94... Logic gate circuit section,
95...10-...Transformer 7 agate circuit section, 101...
Transfer transistor, 102/old-' (7
Bata circuit. 11- Figure 1 (cL) Figure 2 Figure 3 (6t) (b) (Situation) (Mu) Hana 8
Figure number? Figure 10

Claims (1)

[Claims] In a master slice type semiconductor device, the logic gate circuit includes a plurality of field effect transistors with equal load currents for the load elements, and enhancement type assembled gate transistors for the drive elements with equal gate lengths and gate widths. A semiconductor device comprising the same number of field effect transistors as the number of field effect transistors having the same load current.