JPS63285949A - Logic circuit device - Google Patents

Abstract

PURPOSE:To strengthen the logic function of a logic circuit device per gate by maintaining the impedance ratio to the gates as an inverting logic circuit constant, and so composing to connect transistors that a logic threshold voltage is invariable. CONSTITUTION:The source electrodes of driving FETs 11D, 12D are connected to a power line VSS, and drain electrodes are both connected to an output terminal X. The drain electrode of a load FET 11L is connected to a power line VDD, and a source electrode is connected to a gate electrode, i.e., the output terminal X. An input signal is applied to the gate electrodes A, B of the FETs 11D, 12D to obtain an inverting logic signal from the terminal X. The two FETs 11D, 12D are connected in parallel, and since either one FET is cut OFF in operation, the W/L ratio at the FET side is the same as that of one FET, and the value becomes 10. The W/L ratio at the load FET side is 6, and the impedance ratio accordingly becomes 0.6. Thus, the logic function per gate is strengthened to improve the performance in the circuit operation.

Description

[Detailed Description of the Invention] [Summary] The present invention is directed to a semiconductor bulk including a plurality of drive transistors and load transistors each having a predetermined gate width and formed in an array. By connecting drive transistors in series or parallel, and connecting in series a number of load transistors equal to the number of drive transistors connected in series, or a number equal to the number of drive transistors connected in parallel. By connecting the load transistors in parallel, the logic function per gate is strengthened and the performance of the circuit operation is improved.

[Industrial application field]

The present invention relates to a logic circuit device, and more specifically, the present invention relates to a logic circuit device, and more specifically, a predetermined number of drive field effect transistors (drive FBTs) and load field effect transistors (load FETs) formed in an array on a semiconductor bulk. The present invention relates to an inverted logic type logic circuit device composed of a drive FET and a load FET.

[Conventional technology]

FIG. 8 shows an example of the configuration of the above-mentioned inverted logic circuit. The example in FIG. 8 is a DCFL circuit (Direct Coupled PE) used as a basic gate of an IC.
TLogic circuit). DCF
The basic configuration of the L circuit is an enhancement (E) mode transistor as a drive FE7810 (or 82D) and a load FET 81L (or 82L).
It is an inverter gate (INV+) (or rNV2) consisting of a depletion (D) mode transistor as shown in FIG. There is.

FIG. 9 shows an example of the transfer characteristics of the DCFL circuit shown in FIG. Input/output transfer characteristics, P and Q
is the stable operating point, ΔV is the logic voltage amplitude, Vtho is the logic threshold voltage, NMO is the noise margin at low output level, and NMI is the noise margin at high output level.

The input/output transfer characteristics are based on the driving PE that constitutes the inverter gate.
It is determined depending on T and the saturated drain current Td of the load PET. This saturated drain current Id is Id=β(Vg
s −Vth) 2・・・・・・・・・・・・・・・・
...... (1), where Vgs is the gate-source voltage, vth is the threshold voltage of the FBT,
β represents a proportionality constant. And this proportionality constant β is F
It is known that it is proportional to the ratio of the gate width W to the gate length (hereinafter referred to as -/L ratio) of the ET. Therefore, Vgs
When the values of and vth are kept constant, the saturated drain current I
d, and the input/output transfer characteristics of each inverter gate are:
It will be determined depending on the respective W/L ratios of the drive FHT and the load PET.

If the W/L ratio is not selected appropriately,
The value of the logic threshold voltage of the inverter gate will deviate from the midpoint between the stable operating points P and Q, and this effect will cause the logic threshold voltage of the next stage inverter gate to fluctuate, thereby causing a high A problem arises in that the noise margin on the level side or the low level side is insufficient, making it impossible to obtain stable operation of the entire circuit. For this reason,
When designing a circuit, the input/output transfer characteristics must be set so that the logic threshold voltage values of each inverter gate are on the same straight line (the straight line with a slope of 1 in Figure 9).
Appropriate selection of the ratio is made.

In other words, the gate width Wgl of the load FRT in the inverter gate and the gate length LglO ratio (Wgl/LglO
l), and the gate width Wgd and gate length Lgd of the drive FET.
By keeping the ratio (hereinafter referred to as impedance ratio) to O ratio (Wgd/Lgd) constant, stable operation of the circuit can be obtained. In the case of an inverter gate using GaAs (gallium arsenide) MESFETs (metal/semiconductor PETs) as the drive FET and load FET, the gate length is 1. g
is generally kept constant, therefore, the impedance ratio is the ratio of the gate widths of the load FET and the drive FET (Wg
l/Wgd). In any case, in order to stabilize the circuit operation by equalizing the noise margins on the high level side and the low level side of the output, it is necessary to set the impedance ratio to a predetermined value.

The DCFL circuit shown in FIG. 8 is a basic circuit of an inverted logic type circuit, but when actually configuring a circuit on a semiconductor bulk such as a gate array, three to four FETs are used.
A NAND gate (Nant gate) or a NAND gate (NOR gate) consisting of a unit basic cell (B
, C,) are often connected in multiple stages.

[Problem that the invention seeks to solve]

For example, if the load FET (Lgl= 1 μm; W
gl=6μ1ll) and drive FET (Lgd=1
μm; Wgd=10. It is assumed that there is a semiconductor bulk in which FETs (ljm) are formed in an array, and a NOR gate consisting of two drive FETs and one load FET is integrated on the semiconductor bulk as IB, C,. in this case,
The two drive FETs are connected in parallel, but since one of them is in a cutoff state in operation, the 1/L ratio on the drive FET side is the same as the -/L ratio of one drive FET. Therefore, its value is 10 (10 μm/1 μm). On the other hand, the 1/L ratio on the load FET side is 6 (6 μm
/1 μm). Therefore, the impedance ratio is 0.6
becomes.

On the other hand, if you try to configure a Nant gate from the same two drive FETs and one load FET, the two drive PETs connected in series are both in the on state in the inverted logic operation, so the drive On the FET side, the gate length is equivalently doubled, so on the drive FET side, the gate length is equivalently doubled.
The L ratio is 5 (10μ-72μ 1ll). On the other hand, the aluminum ratio on the load FET side is 6 (6μm/1μm
). Therefore, the impedance ratio is 1,2,
This value is different from the impedance ratio of the NOR gate, which is 0.6.

This is done by hybridizing two types of inverted logic gates with different impedance ratios, namely a Nant gate and a NOR gate, on a semiconductor bulk prepared in advance with a predetermined gate width for each of the drive FET and load FET. This means that when connected in multiple stages, the logic threshold voltage at each gate fluctuates, making it impossible to ensure a sufficient noise margin, and therefore, the circuit operation may become unstable. To deal with this, it is necessary to set a different gate width for each B and C, for example, for a Nant gate load FET than for a Norr gate load FET. For example, in the above example, the load F of the Noah gate
While the gate width -g1 of the ET is 6 .mu.m, the gate width -g1 of the Nant gate needs to be about 3 .mu.m. In other words,
It is necessary to prepare two types of gate widths for the load FET.

However, in a type of logic IC, such as a gate array, in which basic cells with a predetermined function are arranged in advance and a predetermined logic is assembled according to the user's wishes at a later stage, it is difficult to That is, it is difficult to know in advance which cells will be configured as Noah gates or Nant gates. Therefore, there is no advantage in preparing two types of gate widths for load FETs on the same bulk, and therefore, from the point of view of manufacturing efficiency, one type of gate width for load FETs is generally designed. .

In other words, in the conventional inverted logic type logic circuit, only one of the NOR gate and the Nant gate can be used as a function, and there is a problem that the logic function as a gate is weak.

Furthermore, if a Nord gate and a Nandt gate are constructed using load PETs with one type of gate width, a situation will inevitably occur in which the saturated drain current of one of the gates will fall below its appropriate value. Therefore, the operating speed of the FET may be sacrificed, and the performance of the circuit operation may be degraded.

The present invention was created in view of the problems in the prior art described above, and aims to provide a logic circuit device that can strengthen the logic function per gate and improve the performance of circuit operation. .

[Means for solving problems]

The problem with the above-mentioned conventional technology is that whether each gate in the inverted logic type 5 logic circuit is composed of a NOR gate or a Nant gate, the impedance ratio of each gate is kept constant and the logic threshold value is This problem is solved by connecting and configuring each FET so that the voltage remains unchanged.

According to a first aspect of the present invention, a plurality of drive transistors and load transistors are formed in an array on a semiconductor bulk, each having a predetermined gate width, and are connected in series or in parallel. a predetermined number of drive transistors connected in series, and load transistors connected in series in a number equal to the number of drive transistors connected in series, and at least one source electrode of the drive transistor has a low potential. connected to a power supply line, at least one drain electrode of the drive transistor is connected to an output terminal, one drain electrode of the load transistor is connected to a high potential power supply line, and one source of the load transistor is connected to a high potential power supply line; an electrode connected to the output terminal and all gate electrodes of the load transistor,
There is provided a logic circuit device characterized in that an input signal is applied to each gate electrode of the driving transistor and an output signal is obtained from the output terminal.

Further, according to the second aspect of the present invention, in a device including a plurality of drive transistors and load transistors formed in an array shape each having a predetermined gate width on a semiconductor bulk, the plurality of drive transistors and load transistors are connected in series or in parallel. a predetermined number of drive transistors connected to the drive transistor, and load transistors connected in parallel in a number equal to the number of drive transistors connected in parallel, and at least one source electrode of the drive transistor has a low At least one drain electrode of the driving transistor is connected to an output terminal, all drain electrodes of the load transistor are connected to a high potential power line, and all of the load transistors are connected to a high potential power line. A source electrode of the transistor is connected to the output terminal and all gate electrodes of the load transistor, and an input signal is applied to each gate electrode of the drive transistor to obtain an output signal from the output terminal. A logic circuit device is provided.

[For production]

Assume now that the gate lengths of the load transistor and the driving transistor are Lgl and Lgd, respectively, and the gate widths are -gl and Wgd, respectively. Further, the predetermined number of drive transistors to be connected is assumed to be N.

In the first form, if the driving transistors are connected in series (during the Nant gate function), the number of load transistors connected in series is N. Therefore, the impedance ratio (W/L ratio on the load transistor side/-/L ratio on the drive transistor side) is (Wg+/(Lgl・N) l/(gag
d/ (Lgd-N) ) = (Wgl/l1g1)
/ (Wgd/Lgd).

On the other hand, if the driving transistors are connected in parallel (
(Nor gate function), the number of load transistors connected in series is one. In this case, on the drive transistor side, all but one transistor are in a cutoff state, so the W ratio on the drive transistor side is the same as the -R ratio of one drive transistor. Become. Therefore, the impedance ratio is (Wg
l/ (Lgl・1) ) / (Wgd/ (Lgd
-1) ) = (Wgl/Lgl) / (Wgd/L
gd).

That is, regardless of whether it is constructed with NOR gates or Nandt gates, the impedance ratio is kept constant, so the logic threshold voltage of each gate can be maintained unchanged. This ensures a sufficient noise margin and contributes to stabilizing circuit operation when multistage connection and integration are performed.

Although the above applies to the second embodiment as well, the detailed configuration and operation of the first embodiment will be explained with reference to the following examples.

〔Example〕

FIG. 1 shows a circuit pattern for constructing a logic circuit device as an embodiment of the present invention.

In Figure 1, 10 is GaAs (gallium arsenide)
A plurality of E-mode drive PETs 11D, 12D, 1 with a predetermined gate width -gd (10 μm in this example) are formed on this semiconductor bulk.
3D.

. . . are formed in an array shape, and have a predetermined gate width Wgl (6μ+m in this embodiment) to form a plurality of D-mode load FBTs 11L, 12L, 13L, .
... are formed in an array.

Furthermore, a low potential power line Vss (OV) is patterned along the array direction on the drive FET side, and a high potential power line Voo (2V) is patterned along the array direction on the load FET side. has been done. Each FET
The hatched area indicates the source or drain region (S/DfIi region), and this S/D
A channel region is formed across the 6I region, and a gate electrode is patterned on this channel region. Also, the threshold voltage of each drive FET is +〇, IV, each load FB? The threshold voltage of is set to 10.5V, and the respective gate lengths Lgd and Lgl are both formed of 1μ steel. In this embodiment, 1 basis cell (1 basis cell) is generated from two drive FETs and one load FET.
IB, C,) are configured.

FIGS. 2(a) and 2(b) show an example of the configuration of a logic circuit based on the circuit pattern of FIG. 1. The example shown in FIG. 2 shows a case where one two-person gate is constituted by I B and C.

In the figure, the opening indicated by S/D indicates a contact region, which represents a source electrode or a drain electrode. The source electrodes of drive FETs 110 and 12D are connected to power supply line V5S, and the drain electrodes are both connected to output terminal X.

On the other hand, the drain electrode of the load PRT 11L is connected to the power supply line VOO, and the source electrode is connected to the gate electrode, that is, the output terminal X. And driving Fil! T
An inverted logic signal is obtained from the output terminal X by applying an input signal to each of the gate electrodes A and B of 110 and 120.

According to the configuration shown in FIG. 2, the two drive FETs 110 and 120 are connected in parallel, and in operation, one of the drive FETs is in a cutoff state, so the W/L ratio on the drive FET side is 1. This is the same as in the case of the drive FET, and the value is 10. On the other hand, the ZL ratio on the load FET side is 6, so the impedance ratio is 0.6.
becomes.

FIGS. 3(a) and 3(b) show other configuration examples of logic circuits based on the circuit pattern of FIG. 1. The example in FIG. 3 shows a case where one two-man powered NAND gate is constructed by 2 B, C, and the like.

The source electrode of the driving FE 7110 is connected to the power supply line Vss, and the drain side is shared with the source of the driving PE 7120. The drain electrode of the drive FE7120 is the output terminal
It is connected to the. On the other hand, the drain electrode of the load FET ILL is connected to the power supply line VDf), the source electrode is connected to the drain electrode of the load FET 12L, and the source electrode of the load PET 12L is connected to the output terminal X. Furthermore, the gate electrodes of the load FETs 11L and 12L are both connected to the output terminal X. Similarly to the NOR gate shown in FIG. 2, an inverted logic signal is obtained from the output terminal X by applying an input signal to each gate electrode A, B of the driving PET 110, 120.

In addition, drive FET 130.140 (see Figure 1)
No wiring will be done for this.

According to the configuration shown in FIG. 3, the two drive FETs 110 and 120 are connected in series and both are in the on state in terms of inverted logic operation, so the gate length on the drive FET side is equivalently doubled. Therefore, W/L on the drive FET side
The ratio will be 5. On the other hand, on the load FET side, the gate length is equivalently doubled, so the W/L ratio on the load FET side is 3. Therefore, the impedance ratio is 0
．． 6, which is the same value as in the case of the Noah gate in FIG.

In other words, as shown in FIG. 1, the driving FET is
By connecting load FETs in series in a number equal to the number of ETs connected in series, the impedance ratio of each gate is made constant regardless of whether each gate is configured with a Nord gate or a Nant gate. be able to.

This makes it possible to keep the logic threshold voltage of each gate unchanged and ensure a sufficient noise margin.

FIG. 4 shows a circuit pattern for constructing a logic circuit device as another embodiment of the present invention.

The circuit pattern example shown in FIG. 4 differs from the circuit pattern example shown in FIG. 1 in that the gate width -gtl of the load FET is formed to be 4μ. Since this is the same as in the case of , the explanation thereof will be omitted. In the embodiment shown in FIG. 4, one page of seven cells (IB, C,) is constructed from two drive FETs and one load FET.

FIGS. 5(a) and 5(b) show an example of the configuration of a logic circuit based on the circuit pattern of FIG. 4. The example shown in FIG. 5 shows a case where one two-man powered NAND gate is constructed by I B and C.

In the figure, the source electrode of the drive FET 110 is connected to the power supply line Vss, and the drain side is connected to the drive FE 712.
The drain electrode of the driving FBT 120 is connected to the output terminal X. On the other hand, the load FET
The drain electrode of 41L is connected to the power supply line VDD, and the source electrode is connected to the output terminal X. Further, the gate electrode of the load PET 41L is connected to the output terminal X. And the driving FE! An inverted logic signal is obtained from the output terminal X by applying an input signal to each gate electrode A, B of T 110, 120.

Note that no wiring is performed for the load PET 42L (see FIG. 4).

According to the configuration of FIG. 5, there are two drive FETs 1lfl.

120 are connected in series and are both in the on state in terms of inverted logic operation, so the gate length on the drive FET side is equivalently doubled, and therefore the rule ratio on the drive FET side is 5. On the other hand, the -/L ratio on the load FET side is 4. Therefore, the impedance ratio is 0.8.

FIGS. 6(a) and 6(b) show other configuration examples of logic circuits based on the circuit pattern of FIG. 4. The example in FIG. 6 shows a case where one two-person gate is constituted by 2 B and C.

In the figure, the source electrodes of drive FETs 110 and 120 are both connected to the power supply line Vss, and the drain electrodes are both connected to the output terminal X. On the other hand, load FH↑4
The drain electrodes of 1L and 42L are connected to the power supply line VOO, and each source electrode is connected to each gate electrode and the output terminal X. And, as in the case of FIG. 5, each gate electrode A of the drive FET 110, 120.

An inverted logic signal is obtained from the output terminal X by applying an input signal to B.

According to the configuration shown in FIG. 6, the two drive FETs 110 and 120 are connected in parallel, and in operation, one of the drive FETs is in a cutoff state, so the 1/L ratio on the drive FET side is 1. This is the same as in the case of the driving PET, and the value is 10. On the other hand, on the load FET side, regardless of the operation of the drive FET, it always functions in a parallel connected state, so its gate width is equivalently doubled, and therefore the roll ratio on the load FET side is It becomes 8. Therefore, the impedance ratio is 0.8, which is the same value as in the case of the Nandt gate in FIG.

That is, for the circuit pattern shown in FIG. 4, the number of load FETs equal to the number of drive FETs connected in parallel
By connecting them in parallel, the impedance ratio for each gate is made constant, as in the embodiments shown in Figures 1 to 3, whether each gate is configured with a Norr gate or a Nant gate be able to.

In the above-described embodiments, the configuration example of a Nant gate or a NOR gate as a basic gate has been described, but the present invention is not limited to this and can be combined with other circuits or gates.

For example, as shown in FIG. 7(a), a drive FE771 having the same configuration, that is, the same gate width of 10μ as the drive FETs 110 and 120, is connected in parallel with the drive FETs 11D and 120 having a Nant gate configuration. Combination gates can also be constructed. In addition, as shown in FIG. 7(b), a source follower circuit consisting of a D-mode FBT 72, 73 having a gate width of 10 μm order and a diode 74 is added to the output side of the Nant gate. BPL circuit (Buffered FET Logic) that performs level shift of output signal
circuit) can also be configured. When configuring this BFL circuit, the driving Fil! T 110' and 12D° are D-mode transistors (threshold voltage: -D,
5V) is used.

In addition, -1,
A voltage of 6V is applied.

In each of the above embodiments, GaAs Ml! is used as a transistor. Although the case where a 5FET is used has been explained, the case is not limited to that, but an n-type MO5FI formed on a semiconductor bulk of Si (silicon) is used. Similar effects are expected when T is used.

〔Effect of the invention〕

As explained above, according to the present invention, the impedance ratio of each gate as an inverting logic circuit is made constant, and the transistors are connected so that the logic threshold voltage remains unchanged. Logic functions can be strengthened, and circuit operational performance can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit pattern for configuring a logic circuit device as an embodiment of the present invention, and FIGS. 2(a) and (b) are one configuration of a logic circuit based on the circuit pattern of FIG. 1. 3(a) and 3(b) are diagrams showing other logic circuits based on the circuit pattern of FIG. 1. 4 is a diagram showing a configuration example, (a) is a circuit diagram, (b) is a circuit pattern diagram including a wiring pattern, and FIG. 4 is a circuit pattern for configuring a logic circuit device as another embodiment of the present invention. Figures 5(a) and 5(b) are diagrams showing one configuration example of a logic circuit based on the circuit pattern in Figure 4, where (a) is a circuit diagram and (b) is a diagram including a wiring pattern. Circuit pattern diagrams. Figures 6 (a) and (b) are diagrams showing other configuration examples of logic circuits based on the circuit pattern in Figure 4, where (a) is a circuit diagram and (b) is a diagram including wiring patterns. 7(a) and (b) are circuit diagrams showing a logic circuit device as yet another embodiment of the present invention, and FIG. 8 is a circuit pattern diagram showing a DCFL.
FIG. 9 is a diagram showing an example of the configuration of the circuit, and FIG. 9 is a diagram showing an example of the transfer characteristic of the circuit shown in FIG. (Explanation of symbols) 10... Semiconductor bulk, 11D, 120. ..., 11D', 12D' ・
...Drive FET. 11L, 12L,..., 41L, 42L,...
...Load Ft! T. Wgd... (driving FET) gate width, -gl...
- Gate width (of load FET), Vss...low potential power line, VOO...high potential power line, A, B...gate electrode (input terminal), X...output terminal.

Claims (1)

[Claims] 1. A plurality of driving transistors (11D, 12D, . . . , formed in an array on a semiconductor bulk (10) each having a predetermined gate width (Wgd, Wgl).・
) and load transistors (11L, 12L,...
...), a predetermined number of drive transistors (11D, 12D) connected in series or parallel, and a load transistor whose number is equal to the number of the drive transistors connected in series. Transistor (11L; 12
L), the source electrode of at least one of the driving transistors (11D) is connected to a low potential power supply line (V_S_S), and the source electrode of at least one of the driving transistors (12D)
The drain electrode of one of the load transistors (11L) is connected to the output terminal (X), the drain electrode of one of the load transistors (11L) is connected to a high potential power supply line (V_D_D), and one of the load transistors (11L; 12L) ) is connected to the output terminal (X) and all the gate electrodes of the load transistors, and an input signal is applied to each gate electrode (A, B) of the drive transistor to connect the output terminal (X) to the output terminal (X). ) A logic circuit device characterized in that an output signal is obtained from the circuit. 2. The logic circuit device according to claim 1, wherein the driving transistors (11D, 12D) function as a NOR gate when connected in parallel. 3. The logic circuit device according to claim 1, wherein the driving transistors (11D, 12D) function as a NAND gate when connected in series. 4. A plurality of driving transistors (11D, 12D,...
) and load transistors (41L, 42L,...
...), a predetermined number of drive transistors (11D, 12D) connected in series or parallel, and loads connected in parallel in a number equal to the number of drive transistors connected in parallel. transistor (41L; 42
L), the source electrode of at least one of the driving transistors (11D) is connected to a low potential power supply line (V_S_S), and the source electrode of at least one of the driving transistors (12D)
The drain electrodes of all the load transistors (41L, 42L) are connected to the high potential power supply line (V_D_D), and the source electrodes of all the load transistors are connected to the output terminal (X). It is connected to the output terminal (X) and all the gate electrodes of the load transistor, and applies an input signal to each gate electrode (A, B) of the drive transistor to output an output signal from the output terminal (X). A logic circuit device characterized in that it obtains. 5. The logic circuit device according to claim 4, wherein the driving transistors (11D, 12D) function as a NAND gate when connected in series. 6. The logic circuit device according to claim 4, wherein the driving transistors (11D, 12D) function as a NOR gate when connected in parallel.