JPH0310129B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a register access control system in an information processing device.

(Prior Art) Conventionally, in this type of information processing device, when saving or restoring the contents of a register by calling a subroutine, a store instruction is executed multiple times to save the contents of the necessary registers. or execute the load instruction multiple times to recover the contents of the necessary registers.

Therefore, in addition to loading and storing register contents, processing such as reading and decoding instructions requires the same number of steps as the number of registers.
The disadvantage was that the overhead was large.

(Objective of the Invention) An object of the present invention is to configure a register to be used for loading or storing by data consisting of bits corresponding to a plurality of registers, and to directly write data from the data without overhead. It is an object of the present invention to provide an information processing device in which registers are configured so that they can be loaded and stored, and loading and storing can be efficiently performed using a plurality of registers.

(Structure of the Invention) An information processing device according to the present invention is configured to include data holding means, first and second detection means, register selection means, state inversion means, and control means.

The data holding means is for holding data consisting of bit groups associated with a plurality of registers.

The first detection means is for detecting bits in a particular state in the data holding means. The register selection means is for selecting a plurality of registers corresponding to the bit detected by the first detection means.

The state inversion selection means is for inverting the state of the bit of the data holding means detected by the first detection means. The second detection means is
This is for detecting whether or not a predetermined number of bits representing a specific state are held in the data holding means.

The control means controls the completion of a series of operations based on the output of the second detection means and sets the data holding means to an initial state.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an information processing apparatus according to the present invention, in which 1 is a data holding means, 2 is a first detection means and a selection means,
Detection and selection means effectively includes state inversion means; 3 is an address register; 4 is a register file; 5 is second detection means; and 6 is control means.

In FIG. 1, the data holding means 1 is composed of a 4-bit register, and the leftmost bit 1
0 corresponds to the register with register number 0, bit 11 corresponds to the register with register number 1,
Bit 12 corresponds to the register with register number 2, and bit 13 corresponds to the register with register number 3. Register number 0 to register number 3
The registers up to number are stored in the register file 4, and the selection of registers placed inside the register file 4 is performed by the address register 3 consisting of two bits 30 and 31. In the data holding means 1, the logical value of each bit is 1.
If the logical value is 0, the register corresponding to each bit is accessed, and if the logical value is 0, the register corresponding to each bit is not accessed. That is, if the content of the data holding means 1 is (1001) ₂ , register number 0 and register number 3 are accessed.

In FIG. 1, detection and selection means 2 which includes first detection means and selection means and which effectively includes state inversion means is constituted by the circuit shown in FIG.

In FIG. 2, first to third gate circuits 21
23 is used as a first detection means, and fourth and fifth gate circuits 24 and 25 are used as selection means to select a register.

The first detection means constituted by the first to third gate circuits 21 to 23 detects only the bit from the input signals b ₀ to b ₃ whose logical value is 1 and which corresponds to the lowest register number. is configured to select. That is, this portion effectively functions as a state inverting means.

The relationship between the signals b ₀ -b ₃ and the signals c ₀ -c ₃ is shown in a portion of FIG. 3.

On the other hand, the register selection means constituted by the fourth and fifth gate circuits selects the register numbers corresponding to the signals _c0 to _c3 whose logical value is 1, as shown in the other part of FIG. It is configured to output signals d ₀ and d ₁ .

The second detection means 5 is constituted by a gate circuit, and is configured to generate an output signal when all outputs of the data holding means 1 have a logical value of 0. The control means 6 controls the input signal.
The contents of a ₀ to _{a 3} are set in the data holding means 1.

Figure 4 shows the registers with register numbers 0 to 3.
This is a timing chart of each signal when accessed with a ₀ to a ₃ =1011, respectively.

FIG. 5 shows a second embodiment of the information processing apparatus according to the present invention, and 1 to 6 are simply the same components as those in FIG. 1.

In FIG. 5, 7 is a state inverting means, and 8 is a masking means.

The state inverting means 7 inverts the state of a bit from a logic value 1 to a logic value 0 corresponding to a register number smaller than the register number set in the address register 3.

The masking means 8 uses the output of the state inverting means 7 to
This is a gate for inhibiting the lower register number, and is made up of 4-bit gate circuits 80-83.

FIG. 6 is a circuit showing details of the detection selection means 2 shown in FIG. 5. In FIG. It is constituted by gate circuits 24 and 25.

In FIG. 6, the first detection means are the first to third detection means.
The selection means is comprised of fourth and fifth gate circuits 24 and 25. FIG. 7 summarizes the relationship between truth values showing the operation of the detection and selection means 2 shown in FIG. 6.

FIG. 8 is a circuit diagram showing details of the state inversion means 7 shown in FIG. 5.

In FIG. 8, the state reversing means 7 are located at the sixth to eighth
gate circuits 71 to 73, ninth to eleventh gate circuits 74 to 76, and a flip-flop 70. The sixth to eighth gate circuits 71 to 73 are gates for outputting mask signals, and the eighth to eighth gate circuits 71 to 73 are gates for outputting mask signals.
Eleventh gate circuits 74 to 76 are decoders for forming mask signals from the output of address register 3. Flip-flop 70 is for enabling the sixth to eighth gate circuits 71-73.

FIG. 9 summarizes truth values indicating the operation of the state inverting means 7 shown in FIG. 8.

The operation of the information processing apparatus according to the present invention will be described in detail below with reference to FIGS. 5 to 9.

The signal k from the control means 6 causes the signal lines a ₀ to a _{3 to}
The contents of are set in the data holding means 1. The signal k is also supplied to state inverting means 7, at which time flip-flop 70 is set.

The signal k has a logic value of 1 only during one clock period. Therefore, as is clear from FIG. 9, the signals m ₀ to _{m 3} all have a logical value of 1 only during one clock period, and the signals b ₀ to b ₃ are output as they are the contents of the data holding means 1. It is something.

b ₀ corresponds to register 40, b ₁ corresponds to register 41
b ₂ corresponds to register 42 and b ₃ corresponds to register 43.

Registers 40 to 43 are stored in register file 4 and can be accessed by giving the corresponding address.

The first detection means constituted by the first to third gate circuits 21 to 23 selects the bit corresponding to the lowest register number whose logical value is 1. The selection means constituted by the fourth and fifth gate circuits 24 and 25 outputs the lowest register number whose logical value is 1.

The selected lowest register number is set in the address register 3, and the corresponding register in the register file 4 is accessed.

The output of the address register 3 is also supplied to the state inversion means 7 shown in FIG. 8, and the state inversion means 7 outputs mask signals m ₀ to m ₃ .

Here, as already explained, the mask signal is used to mask each bit corresponding to a register number smaller than the register number set in the address register 3, and to prohibit output. The mask signal is input to the masking means 8.

Processing for selecting the next register is started by the output signals b ₀ -b ₃ masked by the mask signals m ₀ -m ₃ . In this way, only the registers designated by the data set in the data holding means 1 are accessed one after another without any overhead.

Second detection means 5 for detecting the end of processing
is to detect when the signals b ₀ to _{b 3} are all 0.

It goes without saying that in the first and second embodiments described above, only the portions of the information processing apparatus related to the present invention are extracted and explained, and a general explanation of the information processing apparatus is omitted. do not have.

(Effects of the Invention) As explained above, the present invention is configured by instructing a register used for loading or storing with data consisting of bits corresponding to a plurality of registers, and furthermore, it is possible to directly generate overhead data from the above data. By configuring it so that it can be loaded and stored without any effort, it is possible to perform processing quickly with a simple configuration without sacrificing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram partially showing a first embodiment of an information processing apparatus according to the present invention. FIG. 2 is a diagram showing a circuit configuration of the detection and selection means shown in FIG. 1. FIG. 3 is a diagram summarizing truth values showing the operation of the detection and selection means shown in FIG. 2. FIG. 4 is a timing chart showing the operation of the information processing apparatus shown in FIG. FIG. 5 is a block diagram partially showing a second embodiment of the information processing apparatus according to the present invention. FIG. 6 is a diagram showing a circuit configuration of the detection and selection means shown in FIG. 5. Figure 7 shows the 6th
FIG. 3 is a diagram summarizing truth values showing the operation of the detection and selection means shown in the figure. FIG. 8 is a diagram showing a circuit configuration of the state inverting means shown in FIG. 5. Figure 9 shows the 8th
FIG. 3 is a diagram summarizing truth values showing the operation of the state inverting means shown in the figure. 1... Data holding means, 2... Detection selection means,
3... Address register, 4... Register file, 5... Second detection means, 6... Control means, 7
...State inversion means, 8...Mask means, 21-2
5, 71-76, 80-83...gate circuit, 7
0...Flip flop, 10~13,30,3
1,40~43, _a0 ~ _a3 , _b0 ~ _b3 , _d0 , _d1 , _e0 ,
e ₁ , m ₀ to m ₃ , k...signal.

Claims (1)

[Claims] 1. data holding means for holding data consisting of a group of bits associated with a plurality of registers; a first detection means for detecting bits in a specific state in the data holding means; register selection means for selecting the plurality of registers in response to the bit detected by the first detection means; and register selection means for inverting the state of the bit of the data holding means detected by the first detection means. a state inverting means; a second detecting means for detecting whether or not a predetermined number of bits representing a specific state are held in the data holding means; and the second detecting means. An information processing apparatus comprising: control means for controlling the end of a series of operations by output and setting the data holding means to an initial state.