KR100557918B1 - Error Correction Device Using Joint Test Access Group - Google Patents

Abstract

The present invention relates to an error correction device using a JTAG, in the prior art, a separate device is required to access the external memory, the cost increases and the size of the system is increased, and the contents of the memory can be viewed in real time. There was a problem that there is no way. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, the host and the error correction users actually download the program and execute the error correction; An interface unit for converting a user input into a JTAG interface signal; A TAP controller which receives data of a JTAG signal and actually inputs and executes data when performing error correction or testing, and outputs a state value of a board or a chip to be verified; A test apparatus to be developed / verified (subject to actual development / verification) to which serial shifting and JTAG registers are applied; A bus interface unit for connecting an external memory to the test apparatus; By providing a device configured with error correction logic that controls the test device to directly access the external memory and enables function verification and error correction in real time, separate equipment such as ROM-writer can be accessed. Reduces recurrence time by reducing the cost and increasing the efficiency of equipment, and the ability to observe the number of errors caused by external events by one clock. There is.

Description

Error Correction Device Using Joint Test Access Group

The present invention relates to an error correction apparatus using JTAG, in particular error correction using a Joint Test Access Group (hereinafter referred to as "JTAG") in consideration of the error correction (Debugging) from the design stage of the chip. By using logic to add an external ROM-emulator function inside the chip, it provides a complete error correction environment by implementing error correction logic without additional equipment such as ROM-Writer. An error correcting apparatus using a joint test access group.

1 is a block diagram showing the configuration of an error correction apparatus using a conventional JTAG, as shown in the host 10, the user actually corrects the program to download and execute the error correction; An interface unit 11 for converting a user input into a JTAG interface signal; A TAP controller 12 which actually inputs and executes data when correcting or testing an error, and outputs a state value (a register value of a block to be verified) of a substrate or a chip to be tested; A test apparatus 20 to which JTAG registers (not shown) and serial position shift registers (not shown) are to be actually developed / verified; A bus interface unit 14 for connecting the external memory 15 and the test apparatus 20; It consists of a ROM-writer 13 connecting the host 10 and the external memory 15 for quick access to the external memory 15, and the test apparatus 20 is a JTAG command as shown in FIG. 2. A JTAG command register 21 for storing an error correction mode and outputting a signal, and a JTAG data register driven by a control signal of the JTAG command register 21 to store input data for a test. 22), a serial position shift register 23 for inputting and outputting input data and test result data for a test while shifting the position serially, and a decoding unit for decoding command data input from the serial position shift register 23. The operation of the conventional apparatus configured as described above, which is constituted by (24), is as follows.

The host 10 downloads (down-loads) a user's input (actual program for error correction) and outputs it to the interface unit 11 in accordance with a predetermined protocol (to change to a JTAG interface signal). The 11 inputs a user input (address signal, data signal, and control signal) input from the host to a JTAG command signal, a test mode select signal (hereinafter referred to as "TMS") and a test clock through the JTAG interface protocol. After changing to (Test Clock) (hereinafter referred to as "TCK") and outputting to the TAP controller 12, input data (Test Deta Input) (hereinafter referred to as "TDI") for error correction in accordance with the TMS, TCK. The test apparatus 20 is executed by applying it to the serial shift register 23 of the test apparatus 20, and the result of the execution is received through the serial shift register 23 to allow the developer to view the host 10. Output to) The.

The serial shift register 23 is directly connected to a flip-flop (not shown) of all blocks (registers) in the chip, so that the serial shift register 23 is applied under the control of the TAP controller 12. By using TDI, data for error correction can be arbitrarily inserted into the flip-flop of the chip, and the result of the flip-flop can be read through the TDO by observing the output according to any input. Functional verification of the chip can be performed.

Therefore, while the application developer of the chip is running on the memory to develop a system program, the program is downloaded directly to the external memory 15 to observe the state of the chip, or the ROM-writer 13 to read the value of the external memory. Alternatively, a memory controller (not shown) may be manufactured separately to access the external memory 15. In other words, it accesses by using other device to interface with external memory, and monitors the inside by using JTAG to know the state inside the chip.

As described above, in the related art, a separate device is required to access an external memory, and thus, an increase in cost and a size of a system are increased, and there is no problem in that the contents of the memory can be viewed in real time.

Accordingly, the present invention was devised to solve the above-mentioned conventional problems, and uses an error correction logic using a joint test access group (JTAG) to function as an external ROM-emulator. In addition, the object of the present invention is to provide a device that provides a complete error correction environment by implementing error correction logic without a ROM-Writer or a separate device.

The configuration of the error correction apparatus using the joint test access group of the present invention for achieving the above object comprises: a host for the user to perform the error correction actually download the program and execute the error correction; An interface unit for converting a user input into a JTAG interface signal; A TAP controller that actually inputs and executes data when performing error correction or testing to output a state value of a substrate or a chip to be tested; A test apparatus to be developed / verified (subject to actual development / verification) to which serial shifting and JTAG registers are applied; A bus interface unit (hereinafter referred to as "BIU") for connecting between an external memory and the test apparatus; It is characterized in that the configuration of the error correction logic to control the test device to directly access the external memory, and to enable the function verification and error correction in real time.

The test apparatus includes: a JTAG command register for storing a JTAG command, determining an error correction mode, and outputting a signal accordingly; A JTAG data register driven by a control signal of the JTAG command register to store input data for a test; A serial digit shift register unit for inputting and outputting input data and test result data for a test while shifting a digit in series; An instruction register for storing instruction data for access to an external memory and outputting the instruction data; A decoding unit for decoding the command data input from the command register; An address storage register for storing an address of an external memory to be input from the decoding unit; A data register for storing data of an external memory to be input from the decoding unit; And a status control register for controlling signals (address and data of external memory) output to the BIU.

The error correction logic includes an event storage unit for separately storing only a signal (a hardware interrupt signal, etc.) related to an event input from the outside; An event monitor unit which receives the event signal output from the event storage unit and compares the event signal with a preset state and outputs a corresponding signal; An error correction control unit which stops the operation of the chip by the signal output from the event monitor unit and outputs a signal informing of an error correction mode to the error correction register; A clock generator for generating and outputting a clock for error correction by a control signal of the error correction controller; An error correction register for controlling operations of the host and error correction control unit according to the JTAG interface protocol, and storing the result; And a BIU control unit for reading data stored in the error correction register and applying a state control register value accordingly.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram showing an embodiment of an error correction apparatus using the joint test access group of the present invention. As shown in FIG. 3, a host 30 which actually downloads a program and executes error correction by the user who corrects the error is shown. Wow; An interface unit 31 for converting a user input into a JTAG interface signal; A TAP controller 32 for actually inputting and executing data when correcting an error or performing a test to output state data of a substrate or a chip to be tested; A test apparatus 50 to be developed / verified (subject to actual development / verification) to which a serial digit shift and a JTAG register (not shown) are applied; A bus interface unit (BIU) 33 for connection between an external memory 34 and the test apparatus 50; By controlling the test device 50 is configured to directly access the external memory 34, the error correction logic 40 for controlling the function verification and error correction in real time.

FIG. 4 is a block diagram showing a configuration of a test apparatus to which a serial digit shift register and a JTAG register are applied in FIG. 3. The JTAG instruction stores a JTAG instruction, determines an error correction mode, and outputs a signal according to the configuration. A register 51; A JTAG data register 52 driven by a control signal of the JTAG command register 51 to store input data for a test; A serial digit shift register unit 53 for inputting and outputting input data and test result data for a test while moving a digit in series; An instruction register 54 for storing instruction data for access to the external memory 34 and outputting the instruction data; A decoding unit (55) for decoding command data input from the command register (54); An address storing register (56) for storing an address of an external memory (34) to be input from the decoding unit (55); A data register (57) for storing data of an external memory (34) to be input from the decoding unit (55); It consists of a status control register 58 for controlling signals (address and data of external memory) output to the bus interface device (BIU) 33.

FIG. 5 is a block diagram showing the configuration of error correction logic in FIG. 3, and as shown therein, an event storage unit 41 for separately storing only a signal relating to an event input from the serial digit shift register 53; An event monitor unit 42 which receives an event signal output from the event storage unit 41 and compares it with an event of a previously set state and outputs a signal according to the event; An error correction control unit 43 which stops the operation of the chip by the signal output from the event monitor unit 42 and outputs a signal to the host 30 informing that the switch is in the error correction mode; A clock generator 44 which generates and outputs a clock for error correction according to the control signal of the error correction controller 43; An error correction register 45 for controlling operations of the host 30 and the error correction control section 43 according to the JTAG interface protocol, and storing the result; The BIU control section 46 reads the data stored in the error correction register 45 and applies the state control register 58 value of FIG. 4 accordingly.

Referring to the operation process and effect of the embodiment according to the present invention configured as described above are as follows.

The host 30 downloads (down-loads) a user's input (actual program for error correction) and outputs it to the interface unit 31 according to a preset protocol (to change to a JTAG interface signal). The T31 controller converts a user input (address signal, data signal, and control signal) input from the host 30 into a JTAG command signal, a test mode selection signal (TMS), and a test clock (TCK) through a JTAG interface protocol. After outputting to 32, input data TDI for error correction is output to the serial shift register 53 of the test apparatus 50, or the error correction result value is input from the serial shift register 53. It receives and outputs to the host (30).

In addition, the TAP controller 32 outputs the received TCK and TMS to the error correction logic 40, the error correction logic 40 received the state in real time while executing the chip through the error correction register 45 The control register 58 indicates the state of the chip out. That is, the error correction register 45 controls the error correction control unit 43 to output a signal (hereinafter referred to as a "Halt signal") that causes the clock generation unit 44 to stop the chip to stop the operation of the chip. Afterwards, the instruction register 54 instructs the external memory 34 approach, such as determining whether to read or write or in bulk mode, which is done via JTAG. The command is decoded and output by the decoding unit 55. The address storing register 56 stores an address for accessing an external memory, and the data register 57 stores data. It executes according to the memory approach, and when the execution is finished, the error correction register 45 can indicate the value of the external memory through the JTAG or write the value to the external memory. If you give a command in bulk mode, it automatically reads and writes data, incrementing the address. This allows the system to be developed while modifying data or instructions on external memory during chip execution.

In addition, when developing a system using a chip while monitoring signal transmission with an external circuit and controlling the system clock, for example, when an external interrupt signal comes in, a chip is required to access a specific area of external input / output. In this case, as shown in FIG. 5, the event monitor 42 always monitors signals related to events output from the event storage unit 41, and the state of the input signals is compared with an event of a previously set state. When a change is detected, a detection signal is output. The detection signal is inputted by the error correction controller 43 to control the clock generator 44 to output a Halt signal. The test device 50 enters the stop mode by the Halt signal. Start waiting for commands from the user. Thereafter, when the error correction control unit 43 notifies the error correction register 45 (setting a bit in the error correction register), this signal is notified to the user through the host 30 as an interrupt signal. When the user issues a command, the command sets one bit of the error correction register 45 by the interface unit 31, and this bit becomes a signal for controlling the error correction control unit 43, which is necessary for error correction again. Will do the work. That is, the clock generator 44 generates the clock signal Debug_clk informing the start of error correction, and the test device 50 in the stop mode operates according to the clock signal Debug_clk and stops the chip every clock. Make error corrections. It also allows the user to command single-stepping so that the internal state can be observed one by one.

As described above, the error correction apparatus using the joint test access group of the present invention does not need an additional device such as a ROM-writer to access the external memory, thereby reducing the cost and increasing the efficiency of the device. By allowing the correction to be observed by one clock, it is possible to observe the operating state of the hardware by actual execution, thereby reducing the recurrence time.

1 is a block diagram showing the configuration of an error correction apparatus using a conventional JTAG.

FIG. 2 is a block diagram showing the configuration of a test apparatus to which a serial digit shift register and a JTAG register are applied in FIG. 1; FIG.

Figure 3 is a block diagram showing the configuration of one embodiment of an error correction apparatus using the joint test access group of the present invention.

FIG. 4 is a block diagram showing the configuration of a test apparatus to which a serial digit shift register and a JTAG register are applied in FIG. 3; FIG.

5 is a block diagram showing the configuration of error correction logic in FIG.

*** Description of the symbols for the main parts of the drawings ***

30 host 31 interface

32: TAP controller 33: BIU

34: external memory 40: error correction logic

41: event storage unit 42: event monitor unit

43: error correction controller 44: clock generator

45: error correction register 46: BIU control unit

50: test device 51: JTAG instruction register

52: JTAG Data Register 53: Serial Shift Register

54: instruction register 55: decoding unit

56: address storage register 57: data register

58: status control register

Claims (3)

A host where error correcting users actually download the program and execute the error correction; An interface unit for converting a user input into a JTAG interface signal; A TAP controller that actually inputs and executes data when performing error correction or testing to output a state value of a substrate or a chip to be tested; A test apparatus to be developed / verified with serial shifting and a JTAG register; A bus interface unit for connecting an external memory to the test apparatus; The error correction device using the joint test access group, characterized in that the control device for controlling the test device to directly access the external memory, and to enable the function verification and error correction in real time. 2. The apparatus of claim 1, wherein the test apparatus comprises: a JTAG command register for storing a JTAG command, determining an error correction mode, and outputting a signal accordingly; A JTAG data register driven by a control signal of the JTAG command register to store input data for a test; A serial digit shift register unit for inputting and outputting input data and test result data for a test while shifting a digit in series; An instruction register for storing instruction data for access to an external memory and outputting the instruction data; A decoding unit for decoding the command data input from the command register; An address storage register for storing an address of an external memory to be input from the decoding unit; A data register for storing data of an external memory to be input from the decoding unit; An error correction apparatus using a joint test access group, characterized in that it comprises a status control register for controlling signals (external memory addresses and data) output to a bus interface device (BIU). 2. The apparatus of claim 1, wherein the error correction logic comprises: an event storage unit for separately storing a signal relating to an event input from a serial digit shift register; An event monitor unit which receives the event signal output from the event storage unit and compares the event signal with a preset state and outputs a corresponding signal; An error correction control unit which stops the operation of the chip by a signal output from the event monitor unit and outputs a signal informing that the switch is to an error correction mode, and a clock for error correction by a control signal of the error correction control unit; A clock generator for generating and outputting a signal; An error correction register for controlling operations of the host and error correction control unit according to the JTAG interface protocol, and storing the result; And a BIU controller configured to read data stored in the error correction register and apply a state control register value accordingly.