JPH0530225B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an LSI test pattern generator provided in an LSI (large scale integrated circuit) test device.

Generally, an LSI test pattern generator is included in an LSI test device that checks whether an LSI device is good or bad, and generates various test patterns for the LSI device. A conventional example of such an LSI test pattern generator is shown in FIG. This test pattern generator 1 includes an instruction memory 2 and a test pattern memory 3 that operate at high speed, a program counter control unit 4 that manages the addresses of these memories 2 and 3, and the instruction memory 2.
an instruction execution circuit 5 that interprets and executes instructions stored in the test pattern memory 3; a multiplexer 6 that switches and derives test pattern information from the test pattern memory 3 or control information from the control section of the test equipment; a test pattern register 7 that stores test pattern information, and an input/output modification register 8 that stores control information such as input pin format, I/O pin switching, and output pin care/don't care switching.
It has This test pattern register 7
The information in the input/output modification register 8 is sent to a format forming circuit 9 that forms a test pattern format.

Prior to the start of the test, instructions and test pattern information are transferred and stored in the instruction memory 2 and the test pattern memory 3, respectively, and the program counter control unit 4 receives instructions from the test equipment control unit. 2 and the start address and end address of the test pattern memory 3 are set. At the start of the test, addresses for accessing the memories 2 and 3 are given to the memories 2 and 3 by the program counter control section 4. By this,
The contents from instruction memory 2 are read to instruction execution circuit 5. Here, as a result of interpreting the read instruction, the contents of the test pattern memory 3 are transferred to the test pattern register 7 or the input/output modification register 8 via the multiplexer 6. The transferred data in the memory 3 is set in each register 7, 8 by a set pulse from the instruction execution circuit 5.

Further, if there is a jump instruction or subroutine instruction in the instruction memory 2, the instruction execution circuit 5 sets the next execution address in the program counter control section 4. If there is no jump instruction or subroutine instruction in instruction memory 2, the program counter control section increments the current address by "+1" and executes the same operation as described above, and repeats it until the preset end address is reached. . Test pattern register 7
Alternatively, the contents of the input/output modification register 8 are transferred to the format forming circuit 9 on the test equipment side, and a test pattern according to the format formed here is applied to the device under test via the driver, and the device under test via the comparator. The output is taken into the format forming circuit. On the test equipment side, a comparator compares the output of the device under test with the test pattern data and makes a pass/fail judgment to check whether the device under test is good or bad. The data is accumulated and used for analysis of device test results.

In the conventional test pattern generator as described above, when testing a device under test that requires a random test pattern, data to be output to the device under test is stored in the instruction memory 2 and test pattern memory 3 in advance. In addition, instructions such as test repetition and jump commands are stored, and the expected value pattern of the device under test is stored, and the test is executed according to the pattern. However, recent devices under test have integrated CPU, RAM, ROM, etc.
The number of LSI devices is increasing, making testing them extremely difficult.

In order to test such a device under test, even though the data is based on some kind of algorithm, such as memory addresses and data in the device under test, it is necessary to test addresses and data like other random data. It was necessary to program all data according to the order of change. Therefore,
Not only is the amount of test patterns generated and the amount of work required to create the test patterns enormous, but there is also the disadvantage that it takes a long time to transfer the pattern data, and by extension, it takes a long time to test.

The present invention was made in view of the above circumstances, and
In addition to the normal random pattern generation means, a calculation means for creating test pattern data that operates algorithmically is provided, and by switching between these means as appropriate, the effort required to create algorithmic test patterns can be reduced. It enables tests that required conventional large-capacity test patterns to be performed with an extremely small number of patterns, significantly reducing pattern transfer time during test execution, and significantly shortening test time to improve LSI performance.
The purpose of this invention is to provide an LSI test pattern generator that can improve the test efficiency of test equipment.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows a test pattern generator according to the present invention, and the circuit means for generating a normal random pattern is constructed in substantially the same manner as described above. That is, the random pattern generator 11 operates at high speed and has an instruction memory 12 that stores instructions, a test pattern memory 13 that stores test patterns, and these memories 12,1.
3, an instruction execution circuit 15 that interprets and executes instructions read from the instruction memory 12, and the test pattern memory 13.
Test pattern register 16 that stores pattern data from input pins, input pin format I/O pin switching, and output pin care/don't care
an input/output decoration register 17 that stores input/output modification information such as switching of the input/output data, a delay circuit 18 that delays the set pulse from the instruction execution circuit 15 to provide timing for data set in the registers 16 and 17, and an LSI test device. Information from the control unit, information from the test pattern memory 13, and calculation means (pattern generation means) for creating algorithmic pattern data to be described later.
It has a multiplexer 19 for switching information from the input terminal and guiding it to the registers 16 and 17.

On the other hand, the calculation means (pattern generation means) 20 that creates algorithmic pattern data is
An arithmetic unit (ALU) 21 that can execute multi-bit algorithmic operations such as "+1", "-1", "+N", "-N", etc., and a function mode sent from the LSI test equipment control section. An ALU function register 22 stores changes in data given from the LSI test equipment control section and is given to the arithmetic circuit 21, and causes the arithmetic circuit 21 to perform functional calculations according to this function mode. do
an ALU change value register 23; an initial value register 24 that is given from the LSI test equipment control unit and stores an initial value for the calculation of the calculation circuit 21; a register 25 that stores the calculation result of the calculation circuit 21 and leads it to the multiplexer 19; A multiplexer 2 that switches between the output data from this register 25 and the output data from the initial value register 24 and guides it to the arithmetic circuit 21.
6 and a counter 27 for applying a set pulse to the register 25.

Therefore, in the LSI test pattern generator shown in Figure 2, before starting the test of the device under test,
Instructions or test patterns are transferred and stored in the instruction memory 12 and test pattern memory 13, respectively, and the start address and end address for each memory 12 and 13 are set in the program counter control unit 14 by the test equipment control unit. has been done. In addition, ALU function register 22, ALU change value register 2
3. The initial value register 24 has the ALU function mode and
The initial value is set for the ALU change. Also,
A predetermined value is also set in advance in the counter 27 by the test equipment control unit, and this is determined by the number of times when the instruction read from the instruction memory 12 is a pattern dispensing instruction. The number of counters to perform the calculation is set.

At the start of the test, the program counter control section 14 specifies the addresses of the instruction memory 12 and test pattern memory 13, in this case specifying the start address. The instruction read out from the addressed instruction memory 12 is interpreted and executed by the instruction execution circuit 15. As a result, the test pattern memory 13
The pattern data read from the test pattern register 16 is guided through the multiplexer 19 to be set by the set pulse through the dayless circuit 18, and the input/output modification information is led to the input/output modification register 17 through the multiplexer 19 and set by the set pulse. . Further, if the read instruction is a jump instruction or a subroutine instruction, the instruction execution circuit 15 sets the next execution address in the program counter control unit 14; otherwise, the instruction execution circuit 15 sets the next execution address in the program counter control unit 14. The address is incremented and repeated until the preset end address is reached. In this way a series of random test patterns are generated.

The test pattern data and input/output modification information set in both registers 16 and 17 are transferred to the format forming circuit 28 on the test equipment side, and the test pattern data according to the format formed here is sent to the device under test via the driver. At the same time, the output of the device under test is taken into the format forming circuit via the comparator. On the test equipment side, a comparator compares the above device output with the test pattern data and makes a pass/fail judgment to check whether the device under test is good or bad, or to accumulate fail information. and analyze device test results.

On the other hand, in order to output the calculation results by the calculation means (pattern generation means) 20 as an algorithmic test pattern, the registers 22, 23, 24 and the counter 27 are programmed by the test equipment control section before the start of the test, as described above. First, predetermined information is set. Further, in order to output the output of the arithmetic circuit 21 as the output of the multiplexer 19, the multiplexer 19 is switched to the arithmetic means 21 by a switching signal from the input/output modification register 17.
Switch to select output of 0. This switching is performed by storing predetermined input/output modification data from the test apparatus control section into the register 17 via the multiplexer 19 before starting the test.

Note that the contents of the test pattern memory 13 and register set commands for use and non-use of the calculation means 20 are programmed in the instruction memory 12 in advance, so that the mode can be switched to the calculation means use mode during test execution. Good too.

The initial value set in the initial value register 24 becomes an operand for the operation of the arithmetic circuit 21 via the multiplexer 26. After outputting this initial value, the multiplexer 26 guides the output of the register 25 that stores the calculation result of the calculation circuit 21 to the calculation circuit 21 as an operand. Therefore, the arithmetic circuit 21 performs arithmetic processing on the output data of the multi-register 26 and the output data of the ALU change value register 23 in accordance with the arithmetic function mode set in the ALU function register 22. The calculation result of the calculation circuit 21 is set in the register 25 when the counter 27 counts the set counter value. The pattern data set in the register 25 is transferred to both registers 16 and 17 via the multiplexer 19, outputted as algorithmic pattern data, and used for testing the device under test as described above. In other words, when the instruction read from the instruction memory 12 is a pattern payout instruction, normally a random pattern is sent out from the test pattern memory 13, but if an instruction to use the arithmetic means 20 comes during test execution, Each time the counter 27 counts a predetermined number of times, an algorithmic test pattern is automatically sent out from the calculation means 20 to perform a test on the device under test.

Next, the difference between the test pattern produced by the test pattern generator described above and the test pattern produced by the conventional test pattern generator shown in FIG. 1 will be explained with reference to the instructions and test pattern data shown in FIGS. 3a and 3b. Now, for example, in order to test the built-in memory part of an LSI, first give a chip enable (CE) signal and an address.
Next, select a device under test that provides the write enable (WR) signal and write data, and set the above signal (CE) to the first pin of the LSI, and the signal (WR) to
Assume that the second pin of the LSI, the address is given to the third to tenth pins of the LSI, and the data is given to the eleventh to 18th pins of the LSI. Also, although the instructions are actually coded “1” and “0”, here, to make the explanation easier to understand, the test pattern payout instruction will be written as “SET F” and the input/output modification register 1 will be written as “SET F”.
If you pay out data to 7, “L SET+
Assuming this, the pattern generator shown in Fig. 1 requires a program test pattern as shown in Fig. 3a. In this case, the pattern generator at the even address of the test pattern is The generator gives memory addresses to the device under test and writes data at odd addresses. Therefore, if the memory of the device under test has up to 255 addresses as shown in Figure 3a, the test pattern is 256 addresses. ×2=512 steps are required.
In this case, the address of the device under test starts from address “0” and advances by “+1” sequentially to “255”.
Since it is a simple sequence of advancing to an address, the test pattern can be 512 steps, but the more complex the sequence, the longer the test pattern will be.

However, in this pattern generator, a test pattern for performing the same operation as the test pattern shown in FIG. 3a can be expressed as shown in FIG. 3b. Here, the instruction "L SET ALU" is an instruction to instruct whether or not to use the output of the calculation means 20 as data in the input/output modification register 17, and sets it to "1".
The part programmed as follows uses the output of the calculation means 20. In this case, the third to tenth pins of the LSI corresponding to the address use the output of the calculation means 20. Here, the command "LSET ALU" is different from the command "SETF". That is,
“LSET ALU” command is input/output modification register 1
This is an instruction to set data to the test pattern register 16, and has no effect on the test pattern register 16. Also,
Operand of “LSET ALU” instruction, i.e. “CE”,
“WR”, “ADDRESS 0~7” and “DATA 0”
~7” are test pattern registers 16, respectively.
is not set. Also, “L CALL-
The command "WRITE" is a function that is also provided in the conventional pattern generator shown in Fig. 1, but the command "L SUBR-
This is an instruction to move the program counter to the address indicated by "WRIT" and execute the loop a specified number of times, in this case 128 times, until it reaches "L END".In other words, the test pattern here is:
A subroutine inputs memory addresses and data. That is, the command "LSET ALU" selects the data in the memory address section in the part indicated by the address "11111111", and the next command "SET F" outputs the data of the calculation means 20. Furthermore, the "LSET ALU" command cancels the data output of the calculation means 20 in the part indicated by the address "00000000", and the next "SET F" command outputs the input data. In addition, in the figure, the pattern data of the part indicated by the address “××××××××” is stored in the calculation means 2.
Since data output from 0 is used, either "0" or "1" may be used. With this one subroutine operation, the first four “SET,
It performs the same operation as the "F" instruction. Therefore, by executing the above subroutine 128 times,
It is possible to perform the same operation as the test pattern. However, when executing the test pattern shown in Figure 3b, the initial value register 2 must be set before the start of the test.
4 is set to “0”, and ALU change value register 23 is set to “0”.
It is necessary to set the value "1", "+" in the ALU function register 22, and "2" in the counter 27, respectively.

As can be understood by comparing FIGS. 3a and 3b, the test pattern program used in this test pattern generator has a much smaller number of steps than the conventional test pattern program, making it a simple program. Therefore, not only is it easy to create a program, but the test pattern data transfer time can be shortened, so the test time for device testing can be shortened, and the test efficiency of the test apparatus can be increased. Such an effect becomes greater as the memory built into the device under test increases.

As explained above, according to the present invention, a calculation means (pattern generation means) for creating test pattern data that performs an algorithmic operation is provided in addition to the ordinary random pattern generation means, and these two means are appropriately switched. This reduces the effort (programming) required to create algorithmic test patterns, enables tests that require conventional large-capacity test patterns with an extremely small number of patterns, and reduces pattern transfer time during test execution. It is possible to provide an LSI test pattern generator that can significantly reduce test time, significantly shorten test time, and increase test efficiency of LSI test equipment.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional test pattern generator, FIG. 2 is a circuit diagram of a test pattern generator according to an embodiment of the present invention, and FIGS. 3a and 3b show test pattern programs. 3a is a test pattern program for the test pattern generator of FIG. 1, and FIG. 3b is a test pattern program for the test pattern generator of FIG. 11...Random pattern generator, 12...Instruction memory, 13...Test pattern memory, 15...Program counter control unit,
15... Instruction execution circuit, 16...
Test pattern register, 17... Input/output modification register, 18... Delay circuit, 19, 26...
Multiplexer, 20... Arithmetic means (pattern generation means), 21... Arithmetic circuit (ALU), 22...
ALU function register, 23...ALU change value register, 24...Initial value register, 25...
...Register, 27...Counter, 28...Format forming circuit.

Claims (1)

[Claims] 1. Checking whether the LSI device is good or bad.
An LSI test pattern generator that is included in an LSI test equipment and generates test patterns to be applied to LSI devices includes: (a) memory means for storing instructions and test patterns; and a program counter control section for managing addresses of this memory means. and execution means for executing instructions read from the memory means,
It has a register means for storing a test pattern read out from the memory means as a result of execution by the execution means, and a register means for storing input/output modification information of the LSI device, and a random test pattern for generating a random test pattern. (b) an arithmetic circuit, an arithmetic function specifying means for specifying a function of the arithmetic circuit, register means for storing initial value data given to the arithmetic circuit, and converted value data given to the arithmetic circuit; (c) means for automatically switching between the random pattern generation means and the algorithmic pattern generation means; and (c) means for automatically switching between the random pattern generation means and the algorithmic pattern generation means. An LSI test pattern generator characterized by comprising: