JP2671210B2 - Pattern generator for semiconductor tester - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator for a semiconductor tester, and more specifically to a pattern for a semiconductor tester that can efficiently generate an expected value when testing a logic LSI or the like. Regarding the generator. [Prior Art] FIG. 3 shows a conventional configuration centering on a pattern generator portion of a semiconductor tester of this type. In the figure, 10
Is a CPU, sets a program required for pattern generation in the pattern generator 12 through the interface 11,
The necessary data for timing generation is set in the timing generator 13. The data from the pattern generator 12 and the timing generator 13 are sent to the pin electronics 17, and the pin electronics 17 outputs the device under test (DU
A test pattern etc. is output to T) 18 corresponding to the pins. Reference numeral 20 denotes a test voltage generation circuit, which generates a bias voltage of the DUT 18 and a set voltage for setting the level of a test pattern, etc., by the data from the CPU 10,
Supply to T18 and pin electronics 17, respectively. The pattern generator 12 is generally composed of an instruction memory unit 14 including a ROM, a RAM, an arithmetic circuit, a program counter 15, a controller 16, etc., and generates an address (A) for the DUT 17, pattern data, expected value data, etc. Data (D), a read / write control signal for the DUT 18, a select signal (a part of the control information C), and the like. Then, the address control information for generating the next pattern, the address data (AC) such as the index address and the remaining part of the control information (C) are sent to the controller 16. The controller 16 receives a part (AC + C) of the information read from the instruction memory unit 14, and sets the address of the instruction memory unit 14 to be read next in the program counter 15. As a result, the next address is designated according to the address information set in the program counter 15, and the information such as the next address (A) or the data (D) such as pattern data is read from the instruction memory unit 14. The instruction memory unit 14 is an independent circuit in which the instruction memory is separated from the address operation generating circuit, the data operation generating circuit, the expected value data, the data memory storing the next address data and the like. Receiving the signals read from the instruction memory and generating the address, the control signal and the various data by these circuits, and the various kinds of data directly stored in the instruction memory itself. In some cases, it is directly read and supplied to the pin electronics 17. [Problems to be Solved] By the way, as semiconductor integrated circuits become more sophisticated, chips with many functions are integrated therein, or many functional blocks are integrated into one chip. Are coming. Therefore, when performing the function test (functional test), the number of test items increases, and it is necessary to generate various different test patterns and perform the test. Also, in the memory IC test, after writing data to the DUT, the same data as the write data is used as the expected value and the test is performed by comparing these, but the DUT has some arithmetic function or various logical functions. In the case of a logic IC, a memory with an arithmetic function, a memory with a logic function, or the like, the expected value is the result data according to the arithmetic processing inside the IC. Therefore, the result data corresponding to such an operation or logical processing is different from the write data. Therefore, it is difficult to generate the expected value corresponding to this. If the above calculation is simple, it can be stored in the instruction memory section in advance, but the actual calculation processing is diverse and difficult, and the amount of data becomes large, and the expected value is automatically calculated. There is a situation that cannot be generated. The present invention solves the above problems of the conventional technique, and provides a pattern generator for a semiconductor tester that can efficiently generate an expected value when testing a logic IC. To aim. In this specification, the logic IC is used to include an arithmetic function, a logic IC having various logical functions, a memory with an arithmetic function, a memory with a logic function, and the like. [Means for Solving the Problems] A feature of the pattern generator of the semiconductor tester of the present invention for achieving the above-mentioned object is that the data generating means for generating data, control signals and addresses at predetermined timings. And when the data is data to be written to the device under test, the data memory in which the data to be written is written and the arithmetic processing or logical processing of the device under test are supported based on the address generated corresponding to this data. Based on the arithmetic processing data and the control signal generated from the data generating means at a certain timing, predetermined arithmetic processing is performed based on the arithmetic processing data and the data stored in the data memory, and the expected value is output. And arithmetic processing means. [Operation] As described above, the arithmetic processing means is provided inside the pattern generator, and data corresponding to the data given to the DUT from the data generating means such as the instruction memory is generated and written in the data memory. By storing and storing the stored data and the further generated data in the arithmetic processing means, the arithmetic processing of the arithmetic processing means for these data is set by the control signal from the instruction memory to perform the arithmetic processing. It is possible to easily generate a wide variety of expected values corresponding to the arithmetic processing of the DUT. Also, if the data of the device under test is written to the data memory at the same time as the writing of the data, the expected value can be generated after considering only the time required for the arithmetic processing, so that the expected value can be generated at high speed. it can. In particular, since the calculation processing result is directly output as an expected value, various calculations can be performed later, and calculation processing result data can be freely generated in real time. In addition, the storage capacity of the data memory for writing data is small, and various kinds of functional tests can be performed on the device under test. As a result, it is not necessary to increase the size of the instruction memory, and it is possible to easily generate various expected values in the test of the logic IC. Therefore, various function tests for the logic IC can be efficiently performed. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram centering on a pattern generator portion of an embodiment to which a pattern generator of a semiconductor tester of the present invention is applied, and FIG. 2 shows a device under test having a logic function for performing raster calculation processing. It is explanatory drawing in case it is VRAM. In the figure, reference numeral 1 denotes a pattern generator, the instruction memory section of which is an instruction memory 2, a control signal generating circuit 3, an address operation generating circuit 4,
In this example, the data operation generation circuit 5 and the data memory 6 for expected value data, address data, etc. are separated.
Each of the circuits described above performs a predetermined logical process or arithmetic process in accordance with the data read from the instruction memory 2 to generate an output. Here, when testing a logic IC, the arithmetic circuit 7
To generate expected value data for it. Arithmetic circuit 7
Receives the output data from the data operation generation circuit 5 and the output data from the data memory 6, and receives the control signal from the control signal generation circuit 3 and / or the address from the address operation generation circuit 4 for these data. The arithmetic processing specified based on the signal is executed, and the arithmetic result is sent to the pin electronics 17 as an expected value. The data memory 6 receives access signals from the control signal generating circuit 3, the address operation generating circuit 4, and the data operation generating circuit 5, respectively, is accessed by these signals, and sends the read data to the operation circuit 7. When the DUT 18 is a memory IC, it sends the expected value directly to the pin electronics 17 side. Further, a part of the data read here is output to the controller 16. Here, the content of the arithmetic processing of the arithmetic circuit 7 is such that when the DUT 18 is a logic IC, the processing corresponding to the processing function of the logic IC to be tested is executed. The processing in this case is based on the data obtained from the data operation generation circuit 5 and the data memory 6, and the same result value as that when the logic IC normally operates is obtained. Therefore, if the two input data are the same as the data to be processed by the logic IC, the same processing as that of the logic IC may be performed, and if not, the same as the normal operation logic IC. This is a process of calculating a result value such that the above result is obtained. Now, the operation of this pattern generator 1 is as follows:
When writing data, the address operation generating circuit 4 generates an address necessary for writing, and the data operation generating circuit 5 generates write data at that time. further,
At this time, necessary control signals are generated by the control signal generation circuit 3, and these signals are transmitted via the pin electronics 17 to the DU.
Send to T18. For generation of the next expected value, the write data for the DUT 18 is given to the arithmetic circuit 7, and the write data, the data in the data memory 6, and the address signal output and / or control signal output generated at that time are output. The arithmetic processing according to the content is performed, the result is output as an expected value, and the result is sent to the pin electronics 17 side. FIG. 2 is a schematic diagram in the case where the device under test is a VRAM with a logic function for performing raster calculation processing. In this case, the VRAM 8 has a calculation circuit 8a and a memory 8b inside, An address signal from the pattern generator 1 is received at its address terminal 8c, and write data generated from the data operation generating circuit 5 as input data is received at its terminal 8d. This VRAM8 calculates the data written in the memory 8b and the input data by the lower information of the address given to the address terminal 8c, writes it in the memory 8b again, and outputs it as data from the data terminal 8e. To do. For example, assume that the data A is written in the address XX of the VRAM8. It is assumed that new data B is written at this address XX. In this case, the data actually written in the address XX is the result data C obtained by the arithmetic processing (for example, addition or subtraction) of the data A and the data B. Therefore, the expected value of the test in this case also needs to be the result value data C. Therefore, at a certain pattern data generation timing when the first data A is written in the address XX of VRAM8,
When the address XX of VRAM8 is accessed, the data A is obtained from the data operation generation processing circuit 5 and written to the corresponding address where the data memory 6 is accessed at the address XX correspondingly. . When the data B is written in the VRAM 8 at the next pattern data generation timing, this data B generated from the data calculation generation circuit 5 is added to the calculation circuit 7 together with the write processing, and the address ◯ generated at this time The address is added to the data memory 6 at the same time, this is accessed, the data A stored therein is read out and added to the arithmetic circuit 7. Then, the arithmetic circuit 7 performs the same operation as the operation performed by the VRAM 8 on these data A and data B, and the result is generated as an expected value. The expected value generation timing corresponds to the period of the determination process that requires the expected value. The processing of the arithmetic circuit 7 in this case is the same as that of the VRAM 8 in that the address XX address is received from the address arithmetic generating circuit 4 like the VRAM 8 and the data A and the data B are obtained. Therefore, from the control signal generation circuit 3 to the VRAM
A control signal for performing the same arithmetic processing as that of 8 is simultaneously given to the arithmetic circuit 7 at this time. By this, the expected value corresponding to the result of VRAM8 can be obtained. As described above, the arithmetic circuit 7 of the embodiment may be one that simulates an arithmetic operation, or may be one that is configured by a microprocessor and a memory and operates by microprogram processing. In the embodiment, the example in which the instruction memory unit is separated from the instruction memory and the arithmetic circuit for address, control signal and the like is shown. However, the instruction memory unit obtains each data or control signal directly from the instruction memory. Of course, it may be a pattern generator. [Effects of the Invention] As can be understood from the above description, in the present invention, the arithmetic processing means is provided inside the pattern generator so that the data generating means such as the instruction memory can be used.
By generating data corresponding to the data given to the DUT and setting the arithmetic processing of the arithmetic processing means by a control signal from the instruction memory to perform arithmetic processing, a wide variety of data corresponding to the arithmetic processing of the DUT can be obtained. Expected values can be easily generated. Also, if the data of the device under test is written to the data memory at the same time as the writing of the data, the expected value can be generated after considering only the time required for the arithmetic processing, so that the expected value can be generated at high speed. it can. In particular, since the calculation processing result is directly output as an expected value, various calculations can be performed later, and calculation processing result data can be freely generated in real time. In addition, the storage capacity of the data memory for writing data is small, and a wide variety of functional tests can be performed on the device under test. As a result, it is not necessary to increase the size of the instruction memory, and it is possible to easily generate various expected values in the test of the logic IC. Therefore, various function tests for the logic IC can be efficiently performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram centering on a pattern generator portion of an embodiment to which a pattern generator of a semiconductor tester of the present invention is applied, and FIG. Explanatory diagram in the case of VRAM with logic function to process,
FIG. 3 is a schematic diagram of the overall configuration of a semiconductor tester centering on a pattern generator. 1,12 ...... Pattern generator, 2,14 ...... Instruction memory, 3 ...... Control signal generation circuit, 4 ...... Address operation generation circuit,
5 ... Data operation generation circuit, 6 ... Data memory, 7 ...
… Operation circuit, 8 …… VRAM, 10 …… CPU, 11 …… Interface, 13 …… Timing generator, 15 …… Program counter,
16 …… Controller, 17 …… Pin electronics, 18 …… Device under test (DUT), 20 …… Test voltage generation circuit.

Claims (1)

(57) [Claims] In a pattern generator of a semiconductor tester, data generating means for generating data, a control signal and an address at a predetermined timing, and when the data is data to be written in a device under test, it is generated corresponding to this data. A data memory in which the data to be written is written based on the address, operation processing data from the data generating unit generated at a timing corresponding to operation processing or logic processing of the device under test, and the control signal. Based on the above, the pattern generator of the semiconductor tester is provided with an arithmetic processing means for performing a predetermined arithmetic processing on the basis of the arithmetic processing data and the data stored in the data memory and outputting an expected value. . 2. The data generating means includes an instruction memory that stores the data, the control signal, the address, or data from which these data or signals are generated, and a program counter that generates an address to access the instruction memory. And a controller for controlling the value of the program counter,
The pattern generator of the semiconductor tester according to claim 1, wherein a part of the data of the data memory is sent to the controller.