JP2837615B2 - Microcomputer with test facilitation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a ROM (Read Only Me
More specifically, the present invention relates to a microcomputer having a test facilitation circuit used for a precharge test.

[0002]

2. Description of the Related Art FIG. 1 shows a ROM built in a microcomputer.
FIG. 3 is a diagram showing an example of the configuration of FIG. In the figure, a cell selection signal generation circuit 1 generates a memory cell selection signal and a bit line selection signal corresponding to a ROM address signal supplied via an address bus AB, and supplies these to each of the memory blocks 2. . The memory block 2 is a storage circuit provided for each bit of the data bus DB as shown in the drawing, and has the same internal configuration for each bit. Memory cell block 21, precharge circuit 2
2, a selector 23 and an output buffer 24. The output buffer 24 has not only a buffer function but also a sense amplifier and a tri-state function. The memory cell block 21 is composed of a plurality of memory cells each storing a predetermined storage information signal in advance. Each memory cell of the memory cell block 21 converts a storage information signal stored in the memory cell into a bit line (a), which is a data extraction line, according to a memory cell selection signal supplied from the cell selection signal generation circuit 1. , (B), (c) and (d). The precharge circuit 22 includes a CPU (Central Proc) (not shown).
system clock PH2 supplied from the essing unit)
Precharges each of the bit lines (a) to (d) to a voltage level corresponding to logic "1". The CPU accesses various circuits such as a RAM and a timer (not shown) in addition to the ROM in the microcomputer by using the address signal. The selector 23 selects a bit line corresponding to the bit line selection signal supplied from the cell selection signal generation circuit 1 from the bit lines (a) to (d), and sends out the bit line on the selected bit line. The stored memory information signal is supplied to the output buffer 24. The output buffer 24 supplies, from a CPU (not shown), a voltage level signal corresponding to logic “1” when the voltage level of the stored information signal is equal to or higher than a predetermined level and to logic “0” when the voltage level is lower than the predetermined level. ROMRD
The signal is transmitted as one data bit signal on the data bus DB according to the signal.

[0003] In a test at the time of product shipment of a microcomputer having a built-in ROM having the above configuration, the RO
In addition to the normal test mode in which the content stored in M is read and the read data is determined to be equal to the expected value to determine the quality, the precharge circuit 22 is used. A precharge test mode for determining whether or not the precharge operation is normally performed is performed. In such a precharge test mode,
The storage contents of two memory cells on the same bit line storing information signals of different logic states are continuously read, and it is determined whether or not the storage content of the last read memory cell is equal to an expected value. Thus, it is determined whether or not the precharge operation is normally performed. Each of the above tests is executed by an evaluation tester (not shown) connected to the microcomputer.

FIG. 2 is a time chart showing an example of the operation of the ROM in the precharge test mode executed by the evaluation tester. First, in cycle 1, the evaluation tester sends an information signal of logic "0" stored in the memory cell 21a in FIG. 1 onto the bit line (a), and the bit line (a) is once set to logic "1". 0 "state. Next, in cycle 2, memory cell 2
The information signal of logic "1" stored in 1b is sent out on the bit line (a), and is read out on the data bus. At this time, the evaluation tester sets the bit line (a) when the signal read out on the data bus is logic “1”.
While it is determined that the precharge operation on the above is performed normally, when the signal read out to the data bus is logic "0", it is determined that the precharge operation on the bit line (a) is abnormal. I do. In other words, the precharge circuit 22 instantaneously precharges the bit line (a) to the voltage level corresponding to the logic "1" when the system clock PH2 is at the logic "0". , The precharge is executed gently, as shown by the broken line in FIG. In this gradual precharge operation, the voltage level corresponding to the logic "1" does not reach in cycle 2 and, at this time, the output buffer 24 sends a signal corresponding to the logic "0" onto the data bus. is there. As described above, if the operation is normal, the information signal of logic "1" stored in the memory cell 21b is supposed to be read, but the logic "0" is read due to the abnormal precharge operation. That is, the abnormality of the precharge operation can be detected by determining the deviation of the expected value.

The operation shown in FIG. 2 is an example of an operation which can be applied to a case where an arbitrary address signal can be directly and continuously supplied to the ROM.
On the other hand, like the ROM built in the microcomputer, the CPU
In such a case, there is at least one instruction fetch cycle between the cycles 1 and 2.

However, if there is an instruction fetch cycle for one cycle between the cycles 1 and 2, even if an abnormality occurs in the precharge operation and the precharge operation is performed slowly as shown in FIG. During such an instruction fetch cycle, the voltage level corresponding to logic "1" may be reached.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and it is possible to easily execute a precharge test capable of accurately detecting an abnormal precharge operation. It is an object of the present invention to provide a microcomputer provided with a conversion circuit.

[0008]

A microcomputer provided with a test facilitating circuit according to the present invention has a first logic level.
Or an information signal having the second logic level is stored.
A ROM including a plurality of memory cells, said memory cell bit lines, each said information signal stored in is drawn, and a precharge means for precharging repeatedly said bit lines during a predetermined period every that, before Symbol ROM
And the CPU performing the access in the test mode,
The CPU is executing access to the ROM
The precharge means is not in the
Trine said first logic level or the second logic level to the bit line during a period of non-precharged
And a voltage applying means for applying the corresponding voltage.

[0009]

The microcomputer provided with the test facilitating circuit according to the present invention is capable of controlling the bit in the ROM while the address signal corresponding to the ROM is not supplied and the precharge operation is not executed. Bring the line to the desired voltage level.

[0010]

FIG. 3 shows an example of the configuration of a ROM section in a microcomputer provided with a test facilitation circuit according to the present invention. In the figure, a cell selection signal generation circuit 1
A memory cell selection signal corresponding to a ROM address signal corresponding to a ROM supplied from a PU (not shown) via an address bus AB and a bit line selection signal are generated and supplied to each of the memory blocks 2a. . The memory block 2a is a storage circuit provided for each bit of the data bus DB, and has the same internal configuration for each bit. In the figure,
Only one bit corresponding to the data bus DB0 bit is shown, and the memory block 2a corresponding to the other bits is omitted.

The address decoder 3 outputs a logic "1" ROM disable signal when the address signal supplied from the CPU via the address bus AB is another address signal different from the above ROM address signal. While this is generated and supplied to gate 4, if such an address signal is a ROM address signal, a logical "0"
Is supplied to the gate 4. The mode discriminating circuit 5 discriminates the operation mode based on the mode 1 signal and the mode 2 signal supplied via the external input pin, and generates signals as shown in FIG. 4 according to the discrimination. The mode 1 signal and the mode 2 signal are transmitted to the data bus D by the CPU.
B or may be generated by software based on a signal supplied via the address bus AB. Among the signals shown in FIG. 4, the user mode signal and the normal test mode signal are supplied to various circuits (not shown) in the microcomputer. Each of these circuits enters an execution state of an operation mode according to the user mode signal and the normal test mode signal. On the other hand, of the signals shown in FIG. 4, the precharge test mode signal is supplied to the gate 4. That is, when the mode 1 signal and the mode 2 signal are logic "1" and "0", respectively, it is determined that the precharge test mode is set, and the precharge test mode signal of logic "1" is supplied to the gate 4. is there. Gate 4 is supplied only when the precharge test mode signal of logic "1" is supplied, the ROM disable signal of logic "1" is supplied from address decoder 3, and the system clock PH2 is in the logic "1" state. A gate signal (p) of logic "1" is supplied to each of the memory blocks 2a. The flip-flop 6 is provided with a predetermined bit (DB in the figure) of a data bus in response to a level setting command signal supplied from a CPU provided in the microcomputer.
0) is supplied and supplied to each of the memory blocks 2a.

Next, the internal configuration of the memory block 2a will be described. The memory block 2a includes a memory cell block 21, a precharge circuit 22, a selector 23, an output buffer 24, an applied voltage generation circuit 25, and a voltage application circuit 26. Such a memory cell block 2
Reference numeral 1 denotes a plurality of memory cells each storing a predetermined storage information signal in advance. Each memory cell of the memory cell block 21 converts a storage information signal stored in the memory cell into a bit line (a), which is a data extraction line, according to a memory cell selection signal supplied from the cell selection signal generation circuit 1. , (B), (c) and (d). The precharge circuit 22 precharges each of the bit lines (a) to (d) to a voltage level corresponding to the logic "1" when the system clock PH2 supplied from the CPU is in the logic "0" state. The selector 23 has bit lines (a) to (d)
The bit line corresponding to the bit line selection signal supplied from the cell selection signal generation circuit 1 is selected from among them, and the storage information signal transmitted on the selected bit line is supplied to the output buffer 24. Output buffer 24
ROMRD supplied from a CPU (not shown) supplies a voltage level signal corresponding to logic "1" when the voltage level of the stored information signal is equal to or higher than a predetermined level, and logic "0" when the voltage level is lower than the predetermined level. The signal is transmitted as one data bit signal on the data bus DB according to the signal.

Next, an applied voltage generating circuit 25 generates an applied voltage having a voltage level corresponding to the level designating signal supplied from the flip-flop 6 and supplies this to a voltage applying circuit 26. In the figure, when the logic of the supplied level designating signal is “1”, the applied voltage of the GND voltage level corresponding to the logic “0” is supplied to the voltage applying circuit 26, while the logic of the level designating signal is The case of “0” indicates a configuration in which the applied voltage of the VDD voltage level corresponding to the logic “1” is supplied to the voltage application circuit 26. The voltage applying circuit 26 applies the applied voltage generating circuit 25 while the gate signal (p) of logic “1” is supplied from the gate 4.
Is applied to each of the bit lines (a) to (d). Note that the voltage application circuit 26 does not apply a voltage to the bit lines (a) to (d) while the gate signal (p) of logic “0” is supplied from the gate 4.

Next, the operation in the precharge test mode executed in such a configuration will be described. In executing the precharge test mode, the tester first sets the precharge test mode by fixing the mode 1 signal and the mode 2 signal in FIG. 3 to logic “1” and “0”, respectively. Thereby, the mode determination circuit 5
Keeps supplying a precharge test mode signal of logic "1" to the gate 4. Next, the evaluation tester reads the mode 1 signal and the mode 2 signal to determine the operation mode. At this time, as described above, since the operation mode is the precharge test mode, at this time, the evaluation tester starts the precharge test initialization program. In response to the activation of the precharge test initial setting program, the CPU sends a level designation signal of, for example, logic “1” on the DB0 bit of the data bus DB, and supplies a level setting command signal to the flip-flop 6. . With this operation, the flip-flop 6
A logic “1” level designation signal is supplied to the applied voltage generation circuit 25. At this time, the applied voltage generation circuit 25 generates an applied voltage of the GND voltage level according to the level designation signal, and supplies this to the voltage application circuit 26. After the end of the operation, the evaluation tester starts a precharge test program for executing the operation as shown in FIG. In response to the start of the precharge test program, the CPU executes the ROM 1 in cycle 1 shown in FIG.
The address signal used in other than the above is sent to the address bus AB, and in the next cycle 2, the memory cell 2 in the ROM
The control operation for reading out the storage content of 1b is executed.
It is assumed that an information signal of logic "1" is stored in the memory cell 21b in advance.

In the operation as shown in FIG.
Is when the logic of the signal supplied from the address decoder 3 is "1", that is, the address signal supplied via the address bus AB is another address signal different from the ROM address signal, and the system clock PH2
Output a gate signal (p) of logic "1" while the precharge operation is not being performed. Accordingly, during this period, the applied voltage of the GND voltage level generated by the applied voltage generating circuit 25 is applied to each of the bit lines (a) to (d). All are forced to the logic "0" state. Next, in cycle 2, the information signal of logic "1" stored in the memory cell 21b is sent out on the bit line (a), and this is read out on the data bit DB0 of the data bus. At this time, the evaluation tester determines that the precharge operation on the bit line (a) is performed normally when the signal read on the data bit DB0 is logic “1”, The signal read to the bus is logic "0"
When it is determined that the precharge operation on the bit line (a) is abnormal. Further, such a cycle 2
Is performed on each of the memory cells 21c, 21d, and 21e, and the cycles 1 and 2 are performed as described above.
By repeatedly performing the above operation, the precharge test is performed not only on the bit line (a) but also on each of the bit lines (b), (c) and (d).

As described above, the microcomputer provided with the test facilitating circuit according to the present invention provides the microcomputer having the test facilitating circuit during the period in which the precharge operation is not performed while the ROM address signal is not supplied to the address bus. The bit line is forcibly brought to a desired voltage level state. Therefore, during the instruction fetch cycle in which such an address signal (another address signal different from the ROM address signal) is sent out on the address bus, the bit line in the ROM is set to a desired logic state, and the next R
The OM read operation allows such a bit line to be in a logic state different from the desired logic state.

Therefore, the ROM built in the microcomputer
It is possible to execute a precharge test that can accurately detect an abnormality in the precharge operation even in a memory under the control of the CPU as described above.
In the precharge test initial setting program in the above embodiment, a level designation signal of logic "1" is supplied to the applied voltage generation circuit 25 via the flip-flop 6, so that the voltage application circuit 26 is supplied with the GND voltage level. Although the applied voltage is supplied, depending on the configuration of the memory, it is also possible to supply a level designation signal of logic “0” to the applied voltage generation circuit 25 via the flip-flop 6. At this time, the applied voltage of the VDD voltage level is supplied to the voltage applying circuit 26.

Further, in the above embodiment, the level designation signal is supplied to the voltage application circuit 26 via the flip-flop 6, but the level designation signal is directly supplied to the voltage application circuit 26 via an external pin. May be supplied. Furthermore, the above embodiments may be formed on a single semiconductor chip, or each of various circuits such as a CPU and a ROM may be configured as a board-level board computer formed of individual semiconductor integrated circuits. It may be done.

[0019]

As apparent from the above description, the microcomputer provided with the test facilitating circuit according to the present invention is in a period in which the ROM address signal is not supplied to the address bus, and the precharge operation is executed. The bit line in the ROM is forcibly brought to a desired voltage level state during a period when the ROM is not in operation.

Therefore, during execution of an instruction fetch cycle of the CPU in which another address signal different from the address signal used in the ROM is transmitted onto the address bus,
Since the bit line in the ROM can be set to a desired logic state, even in a ROM under the control of a CPU, such as a ROM built in a microcomputer,
This is preferable because it is possible to easily execute a precharge test capable of accurately detecting an abnormality in the precharge operation.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a configuration of a ROM.

FIG. 2 is a time chart showing an operation of a ROM in a precharge test mode.

FIG. 3 is a diagram showing a configuration of a ROM in a microcomputer including a test facilitation circuit according to the present invention.

FIG. 4 is a diagram illustrating an output of a mode determination circuit.

FIG. 5 is a time chart showing an operation in a precharge test mode executed in the microcomputer according to the present invention.

[Description of Signs of Main Parts]

 25 applied voltage generator 26 voltage applied circuit

Claims (8)

(57) [Claims] A plurality of memory cells storing an information signal having a first logic level or a second logic level; a bit line from which the information signal stored in each of the memory cells is drawn; A ROM including a precharge means for repeatedly precharging a line every predetermined period; a CPU for accessing the ROM; and a test mode in which the CPU is not executing access to the ROM. And voltage applying means for applying a voltage corresponding to the first logic level or the second logic level to the bit line during a period in which the precharge means is not precharging the bit line. A microcomputer comprising a test facilitation circuit characterized by the following. 2. The method according to claim 1, wherein the voltage application unit is configured to control a voltage corresponding to the first logic level and the second logic level in response to a level designation signal.
2. The microcomputer according to claim 1, further comprising an applied voltage switching means for selecting one of the voltages corresponding to the logic level and applying the selected voltage to the bit line. 3. The voltage applying means according to claim 1, wherein the voltage corresponding to the first logic level or the second logic level is applied to the bit line only during a period when a system clock signal supplied from the CPU is at a predetermined logic level. 2. The microcomputer according to claim 1, wherein 4. The microcomputer according to claim 1, wherein said CPU generates said level designation signal. 5. The microcomputer according to claim 2, wherein said level designation signal is supplied to said voltage applying means via an external input pin. 6. The microcomputer according to claim 1, wherein the test mode is a mode for testing a precharge operation in the ROM. 7. The microcomputer according to claim 6, wherein the test mode is set by the CPU. 8. The microcomputer according to claim 6, wherein the test mode is set by an external input.