JPH04248195A - Read-only memory and method for testing this memory - Google Patents

Abstract

PURPOSE:To allow the detection of faults of all memory cells without depending on the data built into the memory cells. CONSTITUTION:Transistors 6 which maintain all bit lines 5 at an H level and transistors 7 which maintain all the bit lines 5 at an L level are provided separately from an ordinary reading out state. The operations in which the three states; the 1st state of the H level, the 2nd state of the L level and the test state to execute ordinary reading out constitute one cycle in order of the 1st state, the test state, the 2nd state, and the test state are executed with all addresses. The respective bit line signals always invert in logic level at either of the time of the transfer from the 1st state to the test state or the time of the transfer from the 2nd state to the test state and, therefore, such a fault that the memory cells are fixed at the off state and fail to attain the on state and such a fault that the memory cells are disconnected from the bit lines are detected.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only memory and a test method thereof.

0002

[Background Art] In recent years, the demand for developing high-performance electrical equipment in a short period of time has increased, and read-only memory (hereinafter referred to as ROM) does not require a precharge operation due to its ease of use and high speed. Asynchronous ROMs have come into use.

[0003] A conventional ROM and its testing method will be explained below. FIG. 4 shows a block diagram of a conventional ROM, in which 1 is a row decoder, 2 is a memory cell, 3 is a column selector, 4 is a word line, 5 is a bit line, a is an address signal, and b is a data signal.

The operation of the ROM thus configured will be explained below. First, address signal a is input to row decoder 1 and column selector 3. Row decoder 1 selects one of all word lines 4 by address signal a.
Enable only books and disable others. Next, among the memory cells 2, the data of the memory cells 2 to which the connected word line 4 is enabled is read out and appears on the bit line 5. Next, column selector 3 selects bit line 5 corresponding to address signal a. As a result, the column selector 3 outputs the data signal b.

FIG. 5 is a signal waveform diagram of a conventional ROM testing method. a is address signal, b is data signal, ck
, cl , cm , and cn are signals extracted from all the bit line signals as an example. Also, AD(N)
, AD(N+1) are address signals indicating addresses N and N+1, respectively, and D(N) and D(N+1) indicate data signals read from addresses N and N+1, respectively.

[0006] Next, a method of testing a ROM configured as described above will be explained. First, address signal a is assumed to be address AD(N) indicating address N. Then, only the word line 4 corresponding to the N address is enabled, and the data read from the memory cell 2 connected to this word line 4 appears on the bit line. In FIG. 5, four bit line signals are shown as an example from all the bit line signals. In this example, the bit line signal ck
is at “L” level, bit line signal cl is at “L” level,
Bit line signal cm is “H” level, bit line signal cn
is at “H” level. Then, the column selector 3 selects the bit line signal corresponding to the address signal AD(N) from all the bit line signals, so that the data signal b becomes D(N). The AD(N) address can be tested by comparing D(N) with the expected value.

Next, when the address signal is set to address AD(N+1) indicating address N+1, the data signal b becomes D(N+1) as described above, and is compared with the expected value. The method to perform this kind of operation from address 0 to the final address is
This is a conventional ROM test method.

[0008]

However, in the conventional configuration described above, the bit line signal is determined by the data written in the memory cell and the address signal, so once the data is written in the ROM, the column selector 3
The state of the bit line signal taken in cannot be arbitrarily set externally. Therefore, during testing, the address signal is AD(
If there is a bit line in which the logic level of the signal does not change when changing from the address AD(N+1) to the address AD(N+1), a failure in the memory cell at the address AD(N+1) connected to this bit line cannot be detected.

That is, in FIG. 5, address AD(
The bit line signal cl is at the "L" level when testing the address AD(N+1), and is also at the "L" level when testing the address AD(N+1). Therefore, address AD(N+
1) Failures such as a memory cell that outputs "L" to the bit line signal cl at an address are fixed in the off state and will not turn on, or a failure where the memory cell is disconnected from the bit line Undetectable. This is the address AD (
N) Charge of bit line during address test is address AD
(N+1) address remains during the test, and even if the memory cell is off or the memory cell is disconnected from the bit line, the input of the column selector will be in the "L" state and the data signal will also be output as "L". This is because the value matches the expected value.

The same applies to the bit line signal cn, and when testing the address AD(N), the bit line signal cn is at "H"level;
Address AD(N+1) is also at "H" level, and there is a failure such that the memory cell at address AD(N+1) is fixed in the off state and will not turn on, or the memory cell is connected to the bit line. Failures such as disconnected wires cannot be detected.

The present invention solves the above-mentioned conventional problems, and provides a ROM and its testing method that can detect failures in all memory cells without depending on the data written in the memory cells. The purpose is to

0012

[Means for Solving the Problems] In order to solve the above problems, the ROM of the present invention includes a circuit that sets each logic level of all bit lines to two mutually inverted states, in addition to the normal read state. It is something that

Further, the ROM testing method of the present invention includes a first state in which each logic level of all bit lines is set, and a second state in which each logic level of all bit lines set in the first state is inverted. and a test state in which the data of a memory cell corresponding to one address is read and compared with an expected value to make a determination, and the operation consists of one cycle in the order of the first state, test state, second state, and test state. is performed for all addresses.

[0014]

[Operation] With this configuration, all the bit lines can be set to two states immediately before the test state, and since all the bit lines are in an inverted state in the above two states, the first state in which all the bit lines are set is , a test state, a second state in which all bit lines are inverted with respect to the first state, and a test state are performed in the order of one cycle, and each bit line is tested twice in one cycle. One of these states will always be the inverse of the data stored in the memory cell at the address to be read, so there may be a failure where the memory cell remains off but does not turn on, or the memory cell is in a bit state. It is possible to detect faults such as wire breaks.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a ROM in a first embodiment of the invention. In FIG. 1, 1 is a row decoder, 2 is a memory cell, 3 is a column selector, 4 is a word line, 5 is a bit line, a is an address signal, and b is a data signal, which are the same as those in FIG. Furthermore, 6 is a P-channel transistor, 7 is an N-channel transistor, 8 is an AND gate, d is a signal that charges all bit lines to H level, e is a signal that discharges all bit lines to L level, f is all word lines The source and drain of P-channel transistor 6 are connected to the power supply and bit line 5, the source and drain of N-channel transistor 7 are connected to ground and bit line 5, and all bit lines 5 are A signal d for charging to H level is input to the gate of P channel transistor 6, a signal e for discharging all bit lines 5 to L level is input to the gate of N channel transistor 7, and further, to the input of AND gate 8. Each output of the row decoder 1 and a signal f for disabling all word lines 4 are input, and the output of the AND gate is input to each word line 4, respectively.

The operation of the ROM of this embodiment constructed as described above will be explained below. First, in a normal read state, the signal d is set to H level, the signal e is set to L level, and the signal f is set to H level, and the P channel transistor 6
, N-channel transistors 7 are both set to the off state, and the enable output of the row decoder 1 is set so as to be applied to the word line. Address signal a is input to row decoder 1 and column selector 3. The row decoder 1 enables only one of all the word lines 4 and disables the others in response to the address signal a. Next, data of the memory cells 2 to which the connected word line 4 is enabled among the memory cells 2 is read out and appears on the bit line 5. Next, the column selector 3 selects the address signal a.
The bit line 5 corresponding to the bit line 5 is selected. As a result, the column selector 3 outputs the data signal b.

Next, to set all bit lines to H level, signal d is set to L level, signal e is set to L level, and signal f is set to L level. By doing this, all word lines 4 are disabled and none of the memory cells 2 are selected. Since the signal e is set to L, the N-channel transistor 7 is in an off state. Furthermore, since the signal d is set to the L level, the P channel transistor 6 is in the on state, so that all bit lines 5 are at the H level.

To set all bit lines to L level, signal d is set to H level, signal e is set to H level, and signal f is set to L level. N-channel transistor 7 is on, P-channel transistor 6 is off, and word line 4 is disabled, so all bit lines 5 are at L level.

As described above, according to this embodiment, the signals d,
With the signals e and f, all bit lines 5 can be set to two mutually inverted states of H level and L level. Next, a ROM testing method in this embodiment will be explained with reference to the drawings. Figure 2 shows the ROM of the present invention.
A signal waveform diagram of the test method is shown, and the ROM has the configuration of the embodiment shown in FIG.

In FIG. 2, a is an address signal, b is a data signal, ck, cl, cm, cn are signals extracted from all bit line signals as an example, and d is a signal that sets all bit lines to H level. The signal e is a signal that sets all bit lines to L level, and the signal f is a signal that disables all word lines. Also, A is the first state in which all bit lines are set,
B is a second state in which all bit lines are inverted with respect to the first state;
C is a test state in which the data signal b is compared with an expected value and determined. In addition, AD(N) and AD(N+1) are address signals indicating addresses N and N+1, respectively, and D(N) and D
(N+1) indicates data signals read from addresses N and N+1, respectively.

The operation of the method for testing the ROM of this embodiment configured as described above will be described below. First, all bit lines are set to H level by signals d, e, and f. This state is the first state A. Next, signal d, signal e
, signal f are set to H level, L level, and H level, respectively, to enter a normal read state. AD(N) to address signal a
), the data signal b becomes D(N). A determination is made by comparing the data signal D(N) with an expected value. This state is test state C. At this time, the data of the memory cell corresponding to address N appears on the bit line. In this embodiment, bit line signals ck, cl, cm,
It is assumed that cn are at L level, L level, H level, and H level, respectively. Next, signal d, signal e, signal f
As a result, all bit lines are set to L level. This state is the second
This is state B. In the first state A and the second state B, the logic levels of all bit lines are inverted. Next, test state C is assumed. The operation in which the above-mentioned first state A, test state C, second state B, and test state C constitute one cycle is performed for all addresses while changing the address signal a.

As described above, according to this embodiment, each bit line signal is activated either when moving from the first state A to the test state C or when moving from the second state B to the test state C. On the other hand, the logic level is always reversed. For this reason,
It is possible to detect a failure in which a memory cell is fixed in an off state and does not turn on, and a failure in which a memory cell is disconnected from a bit line.

Note that in this embodiment, the address signal a is
(N), AD(N+1), etc., and are increased by 1, but this may be done in any order. Furthermore, in this embodiment, all bit line signals are set to H in the first state A.
All bit line signals are set to L level in the second state B, but if each bit line signal is in an inverted relationship in the first state A and the second state C, what kind of signals should be used? Good too.

FIG. 3 shows the RO in the second embodiment of the present invention.
It is a block diagram of M. 1 is a row decoder, 2 is a memory cell, 3 is a column selector, 4 is a word line, 5 is a bit line, a is an address signal, and b is a data signal, which are the same as in FIG. Furthermore, 20 is a memory cell in which data "0" is written, 21 is a memory cell in which data "1" is written, 40 is a word line connected to the memory cell 20,
41 is a word line connected to the memory cell 21, and g is an additional address signal that determines whether to access memory cell 2, memory cell 20, or memory cell 21. When the least significant bit of a is set to L, the word line 41 is enabled, and when the address signal g is set to H level and the least significant bit of address signal a is set to H, the word line 40 is enabled.

The operation of the ROM thus configured will be explained below. By setting address signal g to H level and setting the least significant bit of address signal a to L level, word line 41 is enabled and memory cell 21 is selected. Since data "1" is written in the memory cell 21, all bit lines 5 are at H level. In addition, the address signal g is set to "H" level, and the address signal a is set to "H" level.
By setting the least significant bit of word line 4 to H level,
0 is enabled and the memory cell 20 is selected. Since data "0" is written in the memory cell 20, all bit lines 5 are at L level. In a normal read state, the address signal g is kept at L level.

As described above, according to the second embodiment, by adding the address signal g and the memory cells 20, 21, all the bit lines 5 can be put into two states, H level and "L" level, which are mutually inverted. Can be set to . Furthermore, by making the additional circuit have the same configuration as the conventional circuit, the same pattern is repeated during semiconductor layout, which has the advantage of facilitating design.

In this embodiment, the data written to the memory cell 20 is "0" and the data written to the memory cell 21 is "1", but the data written to the memory cell 20 and the data written to the memory cell 21 are Other data may be used as long as the written data are in an inverse relationship to each other. For example, if a ROM has a configuration in which eight memory cells 20 are connected to one word line 40, the data written to the memory cells 20 will be sequentially written as "0010110" from the row decoder side.
1", the data to be written into the memory cell 21 may be set to "11010010" sequentially from the row decoder side.

In this embodiment, the word lines 40 and 41 are selected using the least significant bit of the address signal a.
This can be assigned to any bit.

[0029]

As described above, the ROM of the present invention can set all bit lines to two states, the first state and the second state, which are inverted states, and the ROM of the present invention can be easily tested. The method is to perform an operation for all addresses in which one cycle consists of the first state, test state, second state, and test state, so that when moving from the first state to the test state at each address, Since each bit line signal of all bit lines is always inverted either when the state is changed from the second state to the test state, it may occur that the memory cell is stuck in the off state and does not turn on, or that the memory cell This makes it possible to realize an excellent ROM and its testing method that can detect failures in which bit lines are disconnected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a ROM in an embodiment of the present invention.

FIG. 2 is a signal waveform diagram in the same ROM testing method.

FIG. 3 is a block diagram of a ROM in a second embodiment of the invention.

FIG. 4 is a block diagram of a conventional ROM.

FIG. 5 is a signal waveform diagram in a conventional ROM testing method.

[Explanation of symbols]

1
Low decoder 2
memory cell 3
Column selector 4
word line 5
bit line 6
P-channel transistor 7
N-channel transistor 8
AN
D gate 20
Memory cell 21 written with data “0”
Memory cell 40 written with data “1”
Word line 41 connected to memory cell 20
Word line a connected to memory cell 21
address signal b
Data signals ck, cl, cm, cn
Signal d extracted from all bit line signals as an example of four signals
Signal e that sets all bit lines to H level
Signal f that sets all bit lines to L level
Signal g to disable all word lines
Additional address signal A
First state B that sets all bit lines
A second state C that inverts all bit lines with respect to the first state.
Test condition where the data signal is compared and judged with the expected value

Claims (3)

[Claims] 1. A read-only memory comprising a circuit that arbitrarily sets each logic level of all bit lines to two mutually inverted states, regardless of data written in a memory cell. 2. The read-only memory according to claim 1, wherein the circuit for setting each logic level of all arbitrary bit lines to two mutually inverted states is composed of an address decoder and a memory cell. 3. A first state in which each logic level of all the bit lines is set, a second state in which each logic level of all the bit lines set in the first state is inverted, and one address. The test state includes a test state in which the data of the corresponding memory cell is read out and compared with an expected value to determine the first state,
A method for testing a read-only memory, characterized in that an operation in which the test state, the second state, and the test state are performed in the order of one cycle is performed for all addresses.