JP2641917B2 - Memory element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a memory element, and more particularly to a memory element which can easily perform a pattern test of a memory cell. In a memory device having a memory cell, a ROM incorporating a plurality of pattern generators for generating a pattern for a memory cell test, and the ROM based on a signal state of an address line of the memory device. And a test execution unit for executing a test of a memory cell in accordance with the memory test pattern.

[Industrial applications]

The present invention relates to a memory device, and more particularly, to a memory device that can easily perform a memory cell pattern test.

2. Description of the Related Art Conventionally, a semiconductor memory element as an information storage means of an information processing apparatus has a function of storing and reading data and the like. You need to check if there are any.
Such a defect of the memory cell often depends on a distribution pattern of stored data on the memory cell. That is, since an error does not occur depending on whether data is stored in a data storage unit that is in conflict with each other, it is not enough to test whether an error occurs in a storage unit alone. It is necessary to store data in various patterns, reproduce and compare the stored data with the reproduced data, and test in what pattern an error occurs.

[Problems to be solved by the invention]

By the way, in general, in a memory element, a scrambler is often provided to make a special correspondence between a designated address and a physical position of a memory cell, and data is distributed in a predetermined pattern on the memory cell. In order to do so, it is necessary to know the contents of the scramble performed by the scrambler. Since the content of the scramble differs depending on each maker or the like, when performing such a test, scramble-related data is obtained from each maker, and after scrambling is performed based on the scramble-related data, the data is stored in the memory cells. A pattern test is performed so that data is stored in a specific pattern.

However, it is cumbersome to obtain scrambled data every time such a pattern test is executed, and when the pattern test needs to be executed urgently, the scrambled data may not be in time. is there.

Therefore, an object of the present invention is to provide a memory element that can execute a predetermined pattern test of a memory element without data related to scrambling.

[Means for solving the problem]

In the present invention, a means for solving the above problem is to generate a test pattern for a memory cell 1 in a memory element 4 having a memory cell 1 as shown in the principle diagram of the present invention in FIG. ROM 6 containing a plurality of pattern generators 2 to be executed, a reading means 7 for selecting a corresponding pattern generator 2 from the ROM 6 based on the signal state of an address line of the memory element 4 and generating a memory test pattern, And a test execution means 3 for executing a test of a memory cell.

[Action]

According to the present invention, the reading means 7 is based on the signal states of the address lines of the memory element 4, for example, the address lines A1 to A9.
The corresponding pattern generator 2 is selected from the ROM 6 and activated to generate a test pattern, and the execution means 3 tests the memory cell 1 according to the test pattern. Accordingly, a predetermined pattern test can be performed inside the memory element regardless of what data the scrambler in the memory element performs scramble.

〔Example〕

Hereinafter, embodiments of the memory device according to the present invention will be described with reference to the drawings.

2 and 3 are block diagrams showing an embodiment of the present invention, and FIG. 3 is a timing chart for explaining the operation of the embodiment. In this embodiment, a portion of the memory element that operates as a normal memory is the same as a general memory element. That is, in the present embodiment, the second
As shown in the figure, a memory cell 11 and an address line for inputting an address for accessing the memory cell 11 are provided.
A write circuit 13 receives and decodes addresses from A0 to A9 and writes data stored in the buffer 12 into a memory cell, decodes an address from address lines A0 to A9, and A read circuit 14 for reading data stored at the address specified by A9 to A9, a mode controller 15 configured by a processor to control the operation mode of the memory element such as read / write, RAS only refresh, and a data output buffer 16 mags are provided. Reference numeral 5 denotes a memory tester provided outside the memory element.

In the present embodiment, the memory element 10 includes:
A control determining unit 18 including a pattern generator for generating a memory cell test pattern, a read-only memory 17 (ROM) operating as a test execution unit for executing a memory cell test based on the pattern, and a microprocessor, and a mode A read circuit 19 for receiving a mode command from the controller 15 and address information from the address lines A0 to A9.

The ROM 17 stores a microprogram. The microprogram includes a program for generating a test pattern and executing a test of the memory cell 11 based on the test pattern.

In this embodiment, the activation of this program is used for accessing the memory element.
TROBE), ▲ ▼ (COLUMN ADRESS STROBE) and ▲
Perform using ▼ (WRITE ENABLE). Conventional C.
BR refresh cycle ▲ ▼ before ▲
▼ ▲, ▲ in refresh cycle mode
By adding ▲ ▼ to the operation of ▼, ▲
If ▼ is High, the CBR refresh mode is set, and if Low, the test mode of the present invention is set.
As shown in FIG. 3, a time interval _{equal to} or longer than a predetermined period T _{CSR is} set from the time when ▼ falls from H to L,
When ▲ ▼ falls from H to L and ▲ ▼ is L, the mode controller 15 determines that the mode is the test mode, sends a test mode signal to the read circuit 19, and the program in the ROM 17 is read under the control of the read circuit 19. Memory cell 1
A pattern test of 0 is performed.
The pattern is selected according to the signal states of the address lines A1 to A9 of the memory element. For example, A1
= H, A2 = L, A3 = L,... A9 = L, a memory test pattern of MARCH is selected, and A1 = L, A2 = H, A3 = L,. Selected.

That is, the read circuit 19 receives the addresses of the address lines A1 to A9.
Determines the read position of the ROM 17, that is, the storage position of the execution program of MARCH or MASEST, and reads from the corresponding position to start the program of MARCH or MASEST. ROM17
From the memory cell, the read / write command and the data in the memory cell are output. Or, a write instruction is performed. At the time of a read command, a command is issued from the ROM 17 to the control / judgment unit 18 so as to compare the data read from the memory cell 11 with the data sent from the ROM 17.
The comparison is performed by the determination unit 18 and the result is output to the data output buffer 16. For example, if the two data are coincident and pass, the signal output is in a high state, and if the two data are inconsistent and FAIL, the signal is output in a low state. .

In the present embodiment, the address line A0 is used as a clock input terminal for operating a pattern program.

Therefore, according to the present embodiment, a pattern test of a memory element can be performed without knowing information about a scrambler.

〔The invention's effect〕

As described above, according to the present invention, it is possible to perform a test for a pattern-dependent error in a memory cell of a memory element without knowing information about a scrambler provided in the memory element, The test pattern can be selected, and there is an effect that it is not necessary to provide a special signal line for selection because an address line is used for selection.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart for explaining the operation of the embodiment. DESCRIPTION OF SYMBOLS 1 ... Memory cell 2 ... Pattern generator 3 ... Test execution means 4 ... Memory element

Claims (1)

(57) [Claims] A memory device having a plurality of pattern generators for generating a pattern for a memory cell test; and a ROM based on a signal state of an address line of the memory device.
1. A memory device comprising: a read unit that selects a corresponding pattern generator from the above and generates a memory test pattern; and a test execution unit that executes a test of a memory cell according to the memory test pattern.