JPH0311435B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high speed pattern generator for testing LSI (Large Scale Integrated Circuits).

Conventionally, there are two types of pattern generators used in LSI test equipment: random pattern generators and algorithmic pattern generators. The former random pattern generator is used in LSIs centered on microcomputers, and the latter algorithmic pattern generator is used in memory systems (RAM, ROM, etc.).
Each is used for testing and evaluation of LSI. A system block diagram of this random pattern generator is shown in FIG. 1, and a system block diagram of the algorithmic pattern generator is shown in FIG. 1 and 2, 1 is a pattern generator control unit, 2 is a control memory where a control program is stored, 3 is a data memory where pattern data is stored, and 4 is an address where the memory address is stored. A register 5 is an address generator that generates an address pattern, and 6 is a data generator that generates a data pattern.

What these pattern generators have in common is that, first, program data transferred from the system control unit, for example, the CPU (central processing unit) of the test equipment via the bus 7, is stored in the control memory 2 and data memory 3 before pattern generation. Second, the control memory 2 and data memory 3 are integrated together and accessed from a common address register 4; and third, as shown in the operating time chart of FIG. Data access to predetermined addresses in memories 2 and 3 and determination of the next execution address are performed within one cycle of the system clock T ₀ , T ₁ , . . . , and one pattern of data is normally generated during this one cycle. It is.

In the pattern generator described above, since the next execution address is accessed after data processing, these series of operations cannot be processed simultaneously. This is because there are three types of reference addresses that can be considered as the next execution address: a repetition of the current address, the current address +1, and a branch destination address, and it is not possible to determine which type of address it is before data processing. Therefore, there is a disadvantage that it is impossible to speed up the processing operation of the pattern generator. In this way, with the increase in density and speed of LSI, LSI test equipment has become faster and more sophisticated.
In particular, despite the strong demand for higher speed and higher functionality of pattern generators, which are the heart of LSI test equipment, higher speed and higher functionality are contradictory for pattern generators, and it is difficult to combine both characteristics. It is becoming extremely difficult to meet this requirement.

The present invention was made in view of the above circumstances, and
By utilizing software processing such as a processor and adding multiple new control memories, memory access operations and read data processing operations can be executed simultaneously, reducing the apparent memory access time. It is an object of the present invention to provide a high-speed pattern generator that can approach zero and achieve high speed while maintaining high functionality.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. The high-speed pattern generator shown in FIG. 4 is roughly divided into two parts, one of which is a control part A that has a control memory as its center.
The other one is a data memory section B that generates test patterns. In the figure, reference numerals 11 and 12 are control memories, and control program data for determining the address scanning order of the data memory 13, which will be described later, is stored in the control memories 11 and 12. Further, 13 is a data memory, and when a random pattern generator is assumed as this embodiment, pattern data to be generated is stored in this data memory 13 by transfer from the CPU. Further, 14 and 15 are buffer registers provided corresponding to the control memories 11 and 12, respectively, 16 is a data stack memory for a subroutine that stores output data from the first buffer register 14, and 17 is a data stack memory for storing output data from the first buffer register 14. A data multiplexer 19 selects and derives one data from among the program data stored in the buffer registers 14 and 15 and the data stack memory 16 according to a control signal from the pattern generator control section 18. 20 is a jump address register that stores a jump address derived from this current data register 19; 24 is a start address register that stores a start address; 22 is a current data register that stores execution data from the data multiplexer 17 or the CPU; an address register storing a predetermined address for reading predetermined data from the control memories 11 and 12; 23 a +1 circuit for incrementing the address of the address register 22; 24 an address stack memory storing a subroutine return address; 25, a jump address register 20, a start address register 21, and an address stack memory 2 are controlled by control signals from the pattern generator control section 18.
This is an address multiplexer that selects one address data from among the 4 and +1 circuits 23.

According to the above pattern generator, an address to be executed is given to the data memory 13 in accordance with program data stored in the two control memories 11 and 12. The data memory 13 is configured to generate data at an address corresponding to a given address as pattern data. The present invention is characterized by the two types of control memories 11 and 12 of the control unit A, the program data stored therein, the stack memory 16 for subroutines, and their operating procedures. That is, the first control memory 11 stores the program data P ₁ at the address “+1” specified by the address register 22.
.about.P.sub.o ₊₁ is stored in the second control memory 12, and program data _J.sub.0 to _J.sub.o of branch destinations designated by the program of the current data register 19 are stored, respectively. FIG. 5 shows the state of the data stored in these memories 11 and 12. Note that the branch destination data and the like stored in the first and second control memories 11 and 12 are created by simulating the original data with a control unit (such as a CPU) of the test and evaluation device. In addition, in this pattern generator, the control section of the test evaluation device stores predetermined data in the control memory 1 prior to pattern generation.
1, 12 and data memory 13, the program data at the start address is stored in the current data register 19, and the start address of the control memories 11, 12 is specified by the start address register 21.

Next, a case will be described in which a pattern is generated by operating this apparatus according to the address procedure shown in FIG. 6. As described above, prior to pattern generation, the start address of the control memories 11 and 12 (in this case, address "0") is stored in the start address register 21, and this start address is set in the address register 22 through the address multiplexer 25. be done. Address “0” set in this address register 22
By specifying the start address "0" of the control memories 11 and 12 at the time of the first system clock of the _T0 period, the contents of each control memory 11 and 12 are read out and the corresponding buffer registers 14 and 12 are read out. 15. That is,
As shown in FIG.
The data P ₁ at address “0” of the first control memory 11 is stored in the second buffer register 15, and the data J ₀ at address “0” of the second control memory 12 is stored in the second buffer register 15. At the same time as this operation, the control unit 18 outputs the start address data preset in the current data register 19.
Upon receiving P ₀ , predetermined data processing is executed. By processing this data _P0 , the next execution address "1" is determined at the end of the _T0 period. Therefore, this control unit 18 sends a control signal to the address multiplexer 25, whereby the address multiplexer 25 selects and outputs the output address "1" from the +1 circuit 23 at the beginning of the _T1 period. . Address “1” data from this address multiplexer 25 is set in the address register 22,
The address register 22 performs a read operation of the "1" address of the control memories 11 and 12 during the _T1 period. At the same time, during this _T1 period, the control section 18 receives the content _P1 of the first buffer register 14, which has already been set, into the current data register 19 through the data multiplexer 17, and executes the processing of this data _P1 . The above T ₁ period is used as the access time for reading address “1” of the control memories 11 and 12, so at the beginning of the T ₂ period, the data at address “1” of the control memories 11 and 12 is
P ₂ and J ₁ are set in the corresponding buffer registers 14 and 15. In the control section 18, the data
As a result of _P1 processing, a branch has occurred, so the control unit 18
controls the data multiplexer 17 to output the previous T ₁
Second buffer register 1 set in period
The branch destination data _J1 of No. 5 is taken in and predetermined data processing is executed using this as processing data. At the same time, during this _T2 period, the control unit 18 derives the jump address "J" from the current data register 19 and sets it in the jump address register 20, and also controls the address multiplexer 25 to derive the jump address "J", The address register 22 is set to access the contents of this jump address "J" from the control memories 11 and 12.

As mentioned above, the program execution proceeds as shown in FIG. 6, but if the same address is repeated multiple times, there is no need to set new data in the current data register 19, and address scanning is performed. is in a hold state. After executing the program data set in the current data register 19, the next execution address is determined, and unless the same address is repeated, the data in the buffer registers 14, 15, etc. is set in the current data register 19 through the data multiplexer 17. be done.

FIG. 7 shows an example of subroutine operation. In this example, a subroutine branch occurs at address n+1.
At this time, the return address n+2 is stored in the address stack memory 24, and the program data P _o+2 is stored in the data stack memory 16.
and branches to address S like a normal branch instruction. At the subroutine final address S+2, either the program data at the start address S of the subroutine (set in the second buffer register 15) or the start data in the data stack memory 16 is selected as the next execution program data. Selected based on return conditions. Here, the first data in the data stack memory 16 means the program data at the return address. of course,
At this time, the address multiplexer 25
The first data in the address stack memory 24 is selected according to the instruction, and this data is set in the address register 22. The reason why the address and data stack memories 24 and 16 have a stack structure is to allow multiple subroutines. In other words, this is to enable multiple subroutines to be processed simultaneously.

As mentioned above, in this pattern generator, within one cycle of the system clock, the access operation of reading the contents from the control memories 11 and 12 at a predetermined address and the data processing of the data read in the previous cycle are performed. The processing operations are executed simultaneously. Therefore, the minimum time for the operating speed of the test device is determined by the larger of the program data processing time or the data read time. Furthermore, the address output from the address multiplexer 25 is also used to specify the address of the data memory 13, and as a result, the data at address "0" is used in the _T1 period, and the data at the "1" address is used in the _T2 period. ,
During the _T3 period, the data at the branch destination address "J" is read from the data memory 13 and sent out from the data memory 13 as pattern data.

In the above embodiment, since two types of reference addresses are used, two types of control memories are provided, but the number of control memories can be increased according to the number of types of reference addresses.

According to the pattern generator, the access operation to the control memories 11 and 12 and the processing operation of the data read from these memories 11 and 12 can be simultaneously processed in parallel within one cycle of the system clock, so that the apparent memory The access time can be reduced to zero, and the speed can be significantly increased compared to the conventional method. Moreover, by creating program data to be applied to the control memories 11 and 12 or rewriting data to the data memory 13 through software processing by the control unit of the test device,
It can maintain very advanced test pattern generation functions. Furthermore, since the stack memories 16 and 24 are used to store data and addresses for subroutines, it is possible to generate pattern data using multiple subroutine programs.

As explained above, according to the present invention, the data memory section that generates pattern data and the control memory for program processing are separated, and by utilizing the software processing of the system processor and adding a plurality of new control memories, By making it possible to simultaneously process memory access operations and data processing operations read from memory in parallel, the apparent memory access time approaches zero, achieving high speed while maintaining high functionality. It is possible to provide a high-speed pattern generator that can realize

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional random pattern generator, Figure 2 is a block diagram of a conventional algorithmic pattern generator, and Figure 3 explains the operation of the pattern generator in Figures 1 and 2. 4 is a block configuration diagram of a high-speed pattern generator according to an embodiment of the present invention; FIG. 5 is a diagram for explaining the relationship between the control memory of FIG. 4 and its stored data; 6 is a diagram for explaining the operation of the pattern generator in FIG. 4, and FIG. 7 is a diagram for explaining the operation of the pattern generator in FIG. 4.
FIG. 3 is a diagram for explaining a subroutine operation of the pattern generator shown in the figure. 11, 12...control memory, 13...
Data memory, 14, 15... Buffer register, 16... Data stack memory, 17... Data multiplexer, 18... Pattern generator control section, 19... Current data register, 20...
... jump address register, 21 ... start address register, 22 ... address register,
23...+1 circuit, 24...address stack memory.

Claims (1)

[Claims] 1. LSI for testing and evaluating large-scale integrated circuits (LSI)
In a high-speed pattern generator that generates a test pattern in a test device, a data memory in which pattern data is stored and from which this pattern data is read by addressing, and an address scan order for the data memory created by a processor of the test device are determined. a control memory which stores predetermined program control data to be executed and which is provided in plurality according to the type of reference address; a buffer register which temporarily stores data from each of the above control memories; and a reference address for subroutines. A stack memory for storing data for subroutines provided according to a pattern generator that specifies and executes a read control operation of the pattern data, and also selects a predetermined address from the reference addresses and executes a processing operation of accessing the control memory and stack memory in response to this address; 1. A high-speed pattern generator, comprising a control section, and configured to perform readout operation of pattern data from the data memory and access operation of the control memory and stack memory in the same way.