JPS5917039Y2 - ROM checker - Google Patents

Description

[Detailed explanation of the idea] This invention relates to an improvement of a ROM checker.

The ROM checker reads the data of the ROM under test based on the specified address, and writes the read data to R.
The data is transferred to the AM and stored therein, and then the ROM under test is inspected by comparing the data in the RAM and the data in the master ROM.

Conventionally, in this type of ROM checker, the address for reading data from the ROM under test can only be specified sequentially, and cannot be specified randomly.

For this reason, it may be possible to create a program to randomly specify the data read address from the ROM under test, but doing so would require a separate program to be set, which would increase the burden on the software. There is a growing problem.

This idea was devised to eliminate these drawbacks, and it is possible to test the ROM under test by randomly specifying addresses, without increasing the burden on the software, and with a simple configuration. The purpose is to provide a ROM checker.

An embodiment of this invention will be described below with reference to the drawings.

Reference numeral 1 denotes a CPU (central processing unit 1-), and this CPU 1 is comprised of an arithmetic circuit, an input/traction recorder, a memo control circuit, and the like.

A system RAM/ROM 4 and a master ROM 5 are connected to the CPU 1 via a data bus 2 and an address bus 3, respectively.

Also, 6 is RAM, 7 is tested @ROM, and these are the above C
It is connected to the PU 1 via the data bus 8, bus driver 9, and the data bus 2, and also connected to the address bus 10, the multiplexer 11, and the address bus 3.
are connected via.

A level determination circuit 12 is also connected to the data bus 8.

An I10 port 14 is also connected to the CPU 1 via a data bus 13.

The CPU 1 is the R of the system ROM/R-AM4.
Based on the program set in the OM, the RAM of the system ROM/RAM4, the master ROM5
, RAM 6, ROM under test 7 and I10 port 14, respectively.

Note that the system ROM/RAM4 RAM is the system RO.
Based on the ROM of the M/RAM 4, it is used for temporarily saving and storing data necessary for the operation of the CPU 1.

A read signal r and a write signal W are output from the CPU 1, and the read signal r is output from the system ROM/RA.
The write signal W is supplied to the lead terminal of M4, the lead terminal of the mask ROM 5, and one input terminal of the two-manufactured AND gate 15, and the write signal W is supplied to the system ROM/
It is designed to be supplied to the write terminal of RAM4.

The I10 port 14 is controlled by the CPU 1 and outputs a bus select signal bs, a dynamic memory access start signal ds, and a counter select signal CS at predetermined timings. The start signal ds is supplied to one input terminal of the flip-flop 17, and the counter select signal C is supplied to one input terminal of the flip-flop 17.
S is supplied to the counter select terminal of the multiplexer 11.

The flip-flop 17 supplies the cassette output to the other input terminal of the AND gate 16 and to one input terminal of a two-manufactured AND gate 18, 19, and 20, respectively.

Further, the flip-flop 17 supplies a reset output to the other input terminal of the AND gate 15 and also supplies it to the I10 port 14 as the dynamic memory access end signal de.

Reference numeral 21 denotes an oscillator that outputs clock pulses, and the clock pulses from this oscillator 21 are supplied to the other input terminal of the AND gate 20.

The oscillator 21 is configured such that the frequency of the generated clock pulse can be varied by adjusting the volume or the like.

Then, the output of the AND gate 15 is supplied to the two-man type OR gate 22, and the output of the AND gate 16 is supplied to the enable terminal of the bus driver 9 and the multiplexer 1.
1 bus select terminal.

The output of the AND gate 20 is connected to the node write control circuit 2.
I am trying to supply it to 3.

The read/write) control circuit 23 is ant game 1-2.
In response to the 0 output, a count signal is supplied to the counter 24, and a control signal synchronized with the count signal is supplied to the other input terminals of the anti-games H8 and 19, respectively.

The output of the AND gate 18 is supplied to the other input terminal of the OR gate 22, and the output of the OR gate 22 is supplied to the R
It is designed to be supplied to the lead terminals of AM6 and ROM7 under test, respectively.

The output of the AND gate 19 is supplied to the write terminal of the RAM 6.

The RAM 6 is designed so that when signals are input to the write terminal and the read terminal at the same time, priority is given to data write processing.

The counter 24 performs a sequential counting operation and sends out, for example, a 4-bit parallel count output.The count signal is sent to the input terminal 11 of the contact operation board 25.
．． ■2. ■3. I4, and when a full run is made, a reset operation is performed and a reset signal is output from the access end terminal to the reset terminal of the flip-flop 17.

The contact operation board 25 has a first group of output terminals 0.
1,02゜03.04 and second group output terminal 05,
06, 07°08 are provided, and the input terminals 11 to 4 are connected to the output terminals 01 to 04, respectively, to take out the count output A of the sequential method, and the input terminals 1 to 4 are connected to the output terminals 08 to 05, for example. They are connected to each other to take out a random count output B.

The count output A is supplied to a first counter address terminal of the multiplexer 11, and the count output B is supplied to a second counter address terminal of the multiplexer 11.

The level judgment circuit 12 judges the level of the data output from the ROM under test 7 to the data bus line 8, and when the level of the data does not satisfy a specified value, a level error is sent to the I10 port 14. signal 1
e is output.

The I10 port 14 transmits the contents to the CPU 1 when the level error signal 1e is input.

Further, 27 is a power supply for the ROM under test which supplies a power supply voltage to the ROM under test 7, and this power supply 27 is connected to the I10 port I.
The output voltage is changed by a control signal from 14.

For example, the ROM 7 under test operates at 5.0 por 1 or more,
If a power source that allows ±10% variation is used, the power supply 27 will adjust the output voltage to 5.5pol l-, 5, Opol l-, 4,5 according to the control signal from the I10 port 1-14.
It is possible to switch between three bolt levels.

In such a configuration, the CPU 1 first controls the 10 port 14 and supplies the ROM under test power supply 27 with a control signal that provides an output voltage of 5.0 volts, for example.

Next, the CPU 1 controls the I10 port 14 to supply a counter select signal CS to the multiplexer 11 to select which of the count outputs A and B is to be manually input to the multiplexer 11.

For example, select count output A.

Subsequently, the CPU 1 controls the I10 port 14 to supply the flip-flop 17 with a dynamic memory access start signal ds.

Then, the flip-flop 17 operates to set, and the set output is supplied to each of the games 1 to 16, 18, 19, and 20.

In this way, the clock pulse from the oscillator 21 is supplied to the read/write control circuit 23, and from this control circuit 23, a count signal corresponding to the clock pulse is supplied to the counter 24, and a control signal synchronized with the count signal is sent to the counter 24. 18 and 19 respectively.

Also, at this time, the CPU 1 controls the I10 port 14 to output the bus select signal bs.

This bus select signal is supplied to the bus select terminal of the multiplexer 11 via the AND gate 16 and also to the enable terminal of the bus driver 9.

In this way, the 77 retiplexer 11 prohibits the input of the address designation signal from the CPU 1, and also treats the count output A as an address designation signal based on the counter select signal C8.

Also, the bus driver 9 cuts off the communication between the data bus 2 and the data bus 8, and disconnects the CPU 1, RAM 6, and ROM under test 7.
Data exchange between the two is prohibited.

Furthermore, a control signal is outputted from the read/write control circuit 23 via the computer 18.19, so that the RAM 5 starts the write operation and the R under test
OM7 starts reading operation and the ROM under test
7 data is stored in RAM6.

At this time, data is read from the ROM 7 under test by specifying an address by the multiplexer 11, but the address is determined not by the CPU 1 but by a count signal from a counter.

Since the input of count output A, which performs counting operation in a sequential manner, is currently selected, addressing is performed based on a fixed order.

Further, the access time at this time is determined by the counting speed of the counter, that is, the oscillation frequency of the oscillator 21.

Furthermore, at this time, the level determination circuit 12 checks the level of the data output from the ROM under test 7 to the data bus 8, and if the level is not at the specified level, the I
A level error signal 1e is output to the 10 port 14.

By manually applying the level error signal 1e to I10 ports 1-14, the CPU 1 can know that there is an abnormality in the data level of the ROM 7 under test.

When the counter 24 reaches full count, a reset signal is output from the access end terminal of the counter 24 and the flip-flop is activated.

When the flip-flop 17 is reset, the dynamic memory access end signal de is supplied from the flip-flop 17 to the I10 port 14.

At the same time, the human input signal to the address bus select terminal of the multiplexer 11 and the enable terminal of the bus driver 9 falls, and the multiplexer 11 and the bus driver 9 become enabled.

As a result, data buses 2 and 8 are connected, and address buses 3 and 10 are connected, so that the RAM 6 can be controlled by the CPU 1.

Therefore, the read signal r from CPU1 is read from master ROM5.
Data is read out from within the RAM 6 based on address designation by the CPU and compared.

Whether the data read from the ROM under test 7 is normal or not is determined by the data in the mask ROM 5 and the ROM under test.
7 is inspected by comparing it with the transferred data in RAM 6.

After this test is completed, if there is no abnormality in the data read from the ROM 7 under test, the CPU 1 will now turn on the I/O.
A counter select signal CS which controls the 10 port 14 and selects the count output B is supplied to the counter select terminal of the multiplexer 11.

In this way, the address for reading data from the ROM 7 under test is now designated by the random count output B.

Data is then randomly read from the ROM 7 under test and transferred to the RAM 6. When this transfer is completed, data buses 2 and 8 and address buses 3 and 10 are connected again, respectively, and the CPU 1 transfers the data to the mask ROM 5. The data is compared with the data in RAM6 and the data in ROM7 under test is
is inspected.

In this way, at first the data of the ROM under test 7 is sequentially read and tested, and then the ROM 7 under test is read out in a sequential manner.
Since the data reading is performed randomly and the test is performed, the test @ROM 7 can be tested for multiple purposes, and the test function can be made more versatile.

In addition, when testing the ROM 7 under test, it is possible to check the level when reading data and change the power supply voltage level to the ROM 7 under test, so it is possible to perform more multi-purpose testing and further improve the testing function. .

Also, reading data from the tested @ROM7 and RAM
Address specification for data storage in 6 is done independently of the CPU 1 using the counter 24 and contact operation board 25, so a separate program is set in the system ROM/RAM 4 for random address specification. There is no need to do this, and the burden on the software 1 does not increase.

Moreover, only one counter is required, and the configuration is simple, as various random states can be changed by simply changing the connections of the contacts on the contact operation board 25.

Furthermore, since the access time to the ROM 7 under test can be changed by changing the frequency of the clock pulse output from the oscillator 21, even if the ROM 7 under test has a different access time, it can be sufficiently coped with. The inspection function can be further improved.

Furthermore, in this case, while the data under test, @ROM7, is being transferred to RAM6, CPU1 and RAM6
, since it is electrically isolated from the ROM7 under test.
The PU 1 can operate the system ROM/RAM 4 and the master ROM 5 to perform other tasks.

As detailed above, this invention provides a ROM checker that can check the data of the ROM under test by specifying random addresses, does not increase the burden on the software, and has a simple configuration. It is possible.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of this invention. 1...CPU (Central Processing Unit), 4...System ROM/RAM, 5...Master ROM, 6...
RAM, 7... ROM under test, 11... Multiplexer, 24... Counter, 25... Contact operation board.

Claims (1)

[Scope of utility model registration request] a central processing unit; a mask ROM connected to the central processing unit via a data bus and an address bus; a RAM and a ROM under test connected to the central processing unit via a data bus and an address bus; A counter that is controlled by a processing unit and counts a count signal of a predetermined frequency and sends out a parallel count output, a contact operation board that changes the count output of this counter to a random count output, and is inserted in the address bus. Under the control of the central processing unit, the R
a multiplexer for switching between addressing the RAM and addressing the RAM and the ROM under test based on the count output inputted through the contact operation board; and the central processing unit controls the multiplexer. The RAM and the ROM under test are addressed by the count output, data in the ROM under test is read out and stored in the RAM, and then the RAM and mask ROM are addressed by the address designation signal to read the data from the ROM under test and read the data from the ROM under test. R is characterized by performing data comparison.
OM checker