JPH01276488A - Refresh control system - Google Patents

Abstract

PURPOSE:To attain smooth refresh while priority is given to a direct memory (DM) access by giving the priority to a DM access signal, which competes with a refresh requesting signal, and executing the held refresh requesting signal after the execution. CONSTITUTION:A refresh prohibiting signal P1 is outputted from a refresh prohibiting pulse generating circuit 12 in correspondence to a DM signal P2 and an AND gate 14 is closed. Then, a refresh signal P3 to be latched by an FF15 is interrupted. When the DM access is finished, the signal P3 to be latched by the FF15 is supplied through the gate 14 to an FF16 and the refresh is executed. As a result, while the priority is given to the DM access, the refresh is smoothly executed without transmitting the refresh requesting signal again during a refresh cycle time.

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention relates to a dynamic memory (hereinafter referred to as D-RAM).
In particular, the D-RAM is used in control systems for high-speed printers, robots, data collectors, etc., in which the D-RAM is configured to be directly accessible to devices other than the central processing unit (hereinafter referred to as CPU).
This invention relates to a refresh control method for RA)I.

``Prior Art'' Conventionally, memory used in high-speed printers and other control systems has a high integration density and low power consumption.
-RAM is widely used, but since D-RAM adopts a structure that uses the stray capacitance of the gate to store charge, the charge disappears over time due to leakage current, etc. In a control system incorporating a D-RAM, a so-called refresh process is required in which clock pulses are periodically applied within a predetermined period of time to recharge the battery.

In order to perform such refresh processing, generally a refresh request signal is forcibly sent to a refresh control circuit at predetermined intervals, and the control circuit sends a RAM control signal necessary for refresh to the D-RAM side and refreshes. However, the refresh cycle is performed at extremely short time intervals of about 4 to 18 isec.
Moreover, since the clock system for the refresh request signal is configured as a separate system from the clock system for normal access commands, memory access and refresh operations inevitably tend to conflict with each other.

For this reason, when such contention occurs, memory access requests are made to wait and a refresh operation is performed during that time.
This inevitably leads to a problem in that the operating speed of the memory decreases.

In order to eliminate this drawback, there is a method that performs the refresh operation in one machine cycle immediately after the CPU accesses the memory (Japanese Patent Laid-Open No. 59-88892, hereinafter referred to as the first prior art), and a method that performs the refresh operation in one machine cycle immediately after the CPU accesses the memory, and a method that performs the refresh operation in one machine cycle immediately after the CPU accesses the memory. A refresh method (Japanese Unexamined Patent Application Publication No. 61-211) in which the memory access timing is determined based on the memory access timing based on the memory access timing, and the refresh is performed using the free time in the memory access period from the memory access to the memory access in the next bus cycle.
No. 2209 (hereinafter referred to as the second prior art), the access command and the refresh request signal are generated using a single clock source, and the generated access command is given a necessary idle time, and the refresh request signal is generated using a single clock source. A refresh method that performs refresh by generating an interrupt of a refresh request signal during the time (Japanese Patent Laid-Open No. 81-242
No. 397 (hereinafter referred to as the "Third Prior Art"), etc.), but in both cases, the memory access timing and refresh timing are controlled based on the reference timing cycle obtained from the CPU, etc., to avoid conflicts between the two as much as possible. The summary is as follows.

"Problem to be Solved by the Invention" However, all of these conventional techniques assume that access to the D-RAM is performed via the CPU or under the control of the CPU; No method has been taken to avoid conflicts when directly accessing the device (hereinafter referred to as ON access).

Therefore, like a page printer, the D-RAM can be used as an image R.
In some devices, the image data is transferred to the image RAM independently of the operation of the image RAM by the 1MA controller, and the image data is transferred to the image RAM independently of the CPU based on the control of the print engine. It is impossible to employ the above-mentioned refresh control method in a device that performs access.

For this reason, in such a device, when the access requests conflict, the access request from the DMA etc. is made to wait and a refresh operation is performed during that time. When using the access request signal as a control signal, or in a control system configured such that the access request signal is generated under the control of the print engine, it is extremely difficult to make the access request signal wait. If this occurs, priority should be given to the 0M access, and the refresh operation should be performed after the access to 0 is completed.

However, since the open access is performed with a device other than the CPU, a special judgment circuit must be provided.
It is not possible for the side to determine whether the access has been completed, and oscillating a refresh request signal after performing such a determination procedure will delay the refresh operation, and in the worst case, it may not be necessary. There is a risk that the stored memory contents may change beyond the refresh cycle time.

In view of the drawbacks of the prior art, the present invention has been proposed to solve the following problems: El-RA)!
The object of the present invention is to provide a refresh control method that can give priority to Dl'l access even when access is performed with a device other than the CPU, and can smoothly perform a refresh operation within a predetermined refresh cycle time. shall be.

"Means for Solving the Problems" In order to achieve such technical problems, the present invention enables direct access to devices other than the CPU - RAM and glue refresh control system, each of which operates asynchronously and periodically. The device has an access cycle and a refresh cycle, and when the access request signal and the refresh request signal conflict, the 0M access is executed with priority, and the refresh request signal is held during the access. , the refresh operation is automatically performed after the 0M access ends.

Here, "the refresh operation is automatically performed" means that the refresh operation is performed immediately after the 0M access ends, without the CPU determining whether the access has ended.

By releasing the hold on the refresh request signal after the refresh operation is completed, the control described above can be performed repeatedly.

"Effect" According to this technical means, when a DM access request signal that is difficult to wait or has a high priority competes with a refresh request signal in a device other than the CPU, the 0
Since the M access is executed with priority, other devices are controlled simultaneously or in parallel with the M access, or the control system is configured such that the request signal is oscillated under the control of the print engine side. The present refresh control method can also be used smoothly without reducing processing capacity.

Furthermore, when there is a conflict with the leaf access, the tree technical means gives priority to the leaf access, but since the refresh request signal is held during the access, the refresh operation is automatically performed almost at the same time as the 0M access ends. This makes it possible to perform refresh operations smoothly during the required refresh cycle time while giving priority to 0M access.

Furthermore, the fact that the refresh operation is automatically performed after the 0M access ends means that there is no need for the CPU to judge that the access has ended, and there is no need to send the refresh request signal again, which simplifies the circuit configuration. and CP
This leads to a reduction in the burden on t1.

It has various effects such as

"Embodiments" Hereinafter, preferred embodiments of the present invention will be described in detail by way of example with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, and relative arrangements of the components described in this example are not intended to limit the scope of this invention, but are merely illustrative examples. It's nothing more than that.

FIG. 1 is a block diagram showing the circuit configuration of a refresh control section according to an embodiment of the present invention.

In the figure, 11 is a buffer, 12 is a refresh inhibit pulse generation circuit, 13 is an input inverter, 14 is an AND gate, and 15 and 1B are flip-flops that are reset based on a refresh end signal.

Next, the operation of this embodiment will be explained based on the time chart of FIG. 2.

In order for a device other than the CPU to access the D-RAM, the 1M access request signal pt is oscillated at a predetermined cycle and is input to the buffer 11, and the signal P1' output from the buffer is sent to the refresh inhibit pulse generation circuit 12. is input.

In the generating circuit 12, the pulse It@t of the request signal Pi is
A pulse signal having a pulse width t7 approximately equal to the sum of 5 and the pulse @te of the refresh operation signal is generated, and the cycle interval of this signal is set to the DM access request signal P1.
and its fall (end) time.

or outputs a fresh prohibition signal P2. The refresh inhibit signal P2 outputted from the generating circuit 12 is inverted by the input inverter 13 and input to the AND gate 14.

On the other hand, the refresh request signal P3, which is periodically oscillating asynchronously with the DM access request signal P1, is input to the other input terminal □ of the anti-game 14 while being held P3' by the flip-flop 15. At this time, since the refresh prohibition signal P2 is inverted by the input negation inverter 13 and input to the AND gate 14, the refresh request signal P4 is free only when the prohibition signal is inactive (Lo). , is input to the flip-flop 16, and the refresh operation signal P5 is output from the flip-flop 16. Then, at the same time as the refresh operation ends, both flip-flops 15
．． 18, the set signal RF is transmitted and each of the signals P3
．． The hold state of P4 is released, and the above operation is repeated thereafter.

Therefore, according to this embodiment, the refresh prohibition signal P
2 is not issued, in other words, when there is no conflict between the access request signal PI and the refresh request signal P3, a refresh operation is performed based on the refresh request signal P3, and when both signals P1 and P3 conflict. In this case, the refresh request signal P3 remains held by the flip-flop because the inverted refresh prohibition signal P2 is input to the analog game) 14.
Waits on the input side of the AND gate 14, and in synchronization with this when the memory access is completed, the refresh request signal P4 is output from the AND gate 14, and the refresh request signal P4 becomes La. A refresh operation can be performed automatically at the same time as access ends.

FIG. 3 is a block diagram showing the circuit configuration of a print controller using the refresh control unit 10. To briefly explain the configuration, 1 is a CPU that controls the entire controller system based on a predetermined program, and 2 is a CPU that controls the entire controller system based on a predetermined program. D
-RAM memory areas 2a, 2b @In an image memory device configured by being divided into two, the -RAM memory area 2a,
While the access with the low HA address signal or the refresh signal is being performed in 2b, the other area is configured to be accessible by CPU t, and thereby, regardless of the refresh or 0M access cycle, CPU t and either of the above are accessed. - memory areas 2a and 2b can be accessed. Note that 9 in the figure is a gate circuit for specifying the area.

3a and 3b are a CPU address bus IA, a DMA address bus 2A, and a refresh address bus 3A;
This is an address selector for selectively connecting the pair of memory areas 2a and 2b.

Reference numeral 4 denotes a refresh address counter, which inputs address signals whose addresses are sequentially updated based on the refresh end signal to the address selectors 3a and 3b via the bus 3A. 5 is a DMA address counter,
Address signals whose addresses are sequentially updated based on signals from the controller 8 are inputted to the address selectors 8a and 3b (ll) via the bus 2A.

A refresh timer 6 transmits a refresh request signal P3 at a predetermined period to the refresh control unit 10 via the CPIJ1.

According to such a controller, the IIMA request signal output from the DMA controller 8 and the refresh request signal P3 from the refresh timer 6 are transmitted to the refresh control unit 1o via the CPU1, and the refresh control unit 10
If there is no conflict between the two request signals, the request signals are directly output to the address selectors 3a and 3b via the switching circuit 7, and if the two request signals conflict, the DMA access request signal is prioritized and output to the TIMA and memory area. At the same time as the access to 2a and 2b is completed, the above-mentioned refresh request signal is output to the address selectors 3a and 3b, respectively, via the switching circuit 7, and based on the signal, the CPU address bus IA,
Dynamic memory areas 2a and 2b corresponding to the DMA address bus 2A and refresh address bus 3A
and a predetermined access operation is performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of a refresh control section according to an embodiment of the present invention, and FIG. 2 is a time chart showing its operation. FIG. 3 is a block diagram showing a circuit configuration of a print controller using the refresh control section.

Claims (1)

[Claims] 1) D-R that can be directly accessed with devices other than the CPU
In the AM refresh control method, when a direct memory access request signal and a refresh request signal of the device, which oscillate asynchronously and periodically, conflict with each other, the direct memory access request is executed with priority, and the A refresh control method characterized in that a refresh request signal is held and a refresh operation is automatically performed after the direct memory access is completed.