JPH01290192A - Refresh control system for d-ram - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by selectively determining priority with being matched to a device in an access requesting signal oscillating side when the refresh operation of a CPU and a memory access request compete. CONSTITUTION:When an access requesting signal P1 and a refresh requesting signal P3 of the CPU compete, the refresh operation is executed with the priority. In such a case, since the access of the CPU is executed on the basis of program control, it is easy to delay the access requesting signal P1 and to interrupt the signal to the idle time of the refresh. On the other hand, since the dynamic memory access operation of the device is a kind of a high speed transferring work to be executed by a hardware, to which the CPU is not related, on the basis of exclusive direct access control, etc., the memory access operation can be enough executed in the necessary cycle of the refresh. Thus, the circuit constitution can be simplified.

Description

[Detailed Description of the Invention] 1. Field of Industrial Application The present invention relates to dynamic memory (hereinafter referred to as D-RAM).
In particular, the present invention relates to a D-RAM refresh control method in a device in which a D-RAM refresh request signal and access request signals for a CPU and a device other than CPU are respectively oscillated asynchronously.

``Prior Art'' Conventionally, memory used in high-speed printers and other control systems has a high integration density and low power consumption.
-RAM is widely used, but since low RAM adopts a structure in which charge is accumulated using the stray capacitance of the gate, the charge disappears over time due to leakage current or the like.

For this reason, in a control system incorporating the D-RAM, a so-called refresh process is required in which clock pulses are periodically applied within a predetermined period of time to recharge the charge.

In order to perform such refresh processing, a refresh request signal is generally forcibly sent to the D-RAM side at predetermined intervals to perform refresh, but refresh cycles are performed at extremely short time intervals. Moreover, since the clock system for the refresh request signal is configured in a separate system from the clock system for normal access commands, the memory access operation of the CPU and other devices inevitably conflicts with the refresh operation. Easy to do.

"W18 that the invention attempts to solve" For this reason, when such a conflict occurs, memory access requests are made to wait and refresh operations are performed during that time, but it is true that memory access with D-RAM is performed via the CPU. Or, in the case of installation under the control of the CPU,
Waiting the memory access request is easy in terms of both software and hardware.1 For example, it is possible to use a video memory device such as a page printer consisting of a D-RAM and transfer image data to the video memory. D.
- In the case of a device in which the RAM directly accesses a device other than the CPU (hereinafter referred to as 0M access), it may be extremely difficult to wait for the access request.

That is, in the device, the DM access request signal is not controlled by software under program control from the CPU, but is controlled by hardware based on a DMA controller, etc., so there is no degree of freedom; Waiting a signal not only inevitably complicates the circuit configuration, but also particularly when the request signal is used as a control signal for another device or when the memory access request signal is controlled by the print engine. In a control system configured to generate oscillations, it may not be possible to wait the access request signal.

In view of the shortcomings of the prior art, the present invention provides that when a refresh operation and a memory access request conflict, one of the
Rather than uniformly selecting the operation of
The access operations of the CPU and the access operations of devices other than the CPU can be performed at favorable times, and this refresh is particularly effective in systems where access operations of the CPU and devices other than the CPU frequently occur together, such as the control system of a high-speed printer. The purpose is to provide a control method.

"Means to solve problems" As mentioned above, the refresh request signal.

In a device in which the access request signals of the CPU and devices other than the CPU are oscillated asynchronously, the refresh cycle is performed at extremely short time intervals of about 4 to 18 m5ec, as described above, so that the CPU access There are many cases where a request signal and a refresh request signal, and a device access request signal and a refresh request signal conflict. However, between the CPU and other devices - typically via an I1MA controller
REA port/WRI of the device and D-RAM on the PU side
Since the configuration is such that TE processing is left to the discretion of the user, there is no need to consider the conflict between the two, and only the conflict between the former two needs to be considered.

That is, the feature of the present invention is that in a device in which a refresh request signal and an access request signal of a device other than the CPIJ and the CPU are respectively oscillated asynchronously, when a refresh operation and a memory access request conflict,
Rather than uniformly selecting one of the two operations, the priority order is selectively determined according to the device on the access request signal oscillation side. The access operation is performed at the most favorable time.

Next, the features of the present invention will be explained in detail in order.

First, the access operation of the CPU is performed based on program control, such as writing data from a font memory or the like from READ L to D-RAM based on an address signal output from the CPU. Therefore, the execution time of the - instruction inevitably becomes longer and exceeds the required refresh cycle time.

Therefore, the first feature of the present invention is to execute the refresh operation with priority when there is a conflict between the access request signal of the CPU and the refresh request signal.

In this case, since the CPU access is performed based on program control, it is easy to delay the access request signal and interrupt the idle refresh time.

On the other hand, the [+-RAM access operation of the device is as follows.

Since this is a type of high-speed transcription work performed by hardware that does not involve the CPU, based on a dedicated DMA controller, etc., it can be completed within the required refresh cycle.

Therefore, a second feature of the present invention is that when there is a conflict between the D-RAM access request signal and the refresh request signal of the device, the access operation of the device is executed with priority; If the refresh operation is performed at the same time as the access operation ends, there is no possibility that the same problem will occur in the refresh process.

Moreover, the D-R of the device is performed by hardware.
Since priority is given to the AIII access operation, hardware that performs wait etc. is not required, the circuit configuration is simplified, and the request signal can be used as a control signal for other devices or for external devices such as the print engine side. The present invention can also be applied to a control system configured to oscillate the memory access request signal based on control, and is extremely versatile.

"Embodiments" Hereinafter, preferred embodiments of the present invention will be described in detail by way of example with reference to the drawings. However, the 4 described in this example
1! Dimensions, materials, shapes, relative positions of component parts, etc., unless otherwise specified.

This is not intended to limit the scope of the invention, but is merely an illustrative example.

FIG. 1 is a block diagram showing the circuit configuration of a refresh control section according to an embodiment of the present invention.

In the figure, 11 is a buffer, 12 is a refresh inhibit pulse generation circuit, 13 is an input inverter, 14 is an AND gate, 15 and I6 are both flip-flow 2 pins that are reset based on the refresh end signal, and 18 is a request request. This is a determination circuit that invalidates the CPU access request signal when the signal is output.

Next, the operation of this embodiment will be explained based on the time chart of FIG. 2.

DM access request signal P1 from a device other than CPυ
is input to the refresh inhibit pulse generating circuit 12 via the buffer 11 at a predetermined cycle, the pulse width t5 of the request signal PI and the pulse portion of the refresh operation signal are approximately equal to the sum of the pulse width t5 of the refresh operation signal in the generating circuit 12. Equal pulse @
D) A refresh prohibition signal p that generates a pulse signal having a time of t7 and makes the cycle interval of the signal coincide with D)1 access request signal P1 and its fall (end) timing.
Output 2. The refresh inhibit signal P2 outputted from the generating circuit 12 is inverted by the input inverter 13 and input to the AND gate 14.

On the other hand, the refresh request signal P3, which periodically oscillates asynchronously with the DH access request signal PI, is input to the other input terminal of the AND gate 14 while being held P3' by the flip-flop 15. At this time, since the refresh prohibition signal P2 is inverted by the input negation inverter 13 and input to the AND gate 14, the refresh permission signal P4 is input to the flip-flop only when the prohibition signal P2 is inactive (La). P1
6, and the refresh operation signal P5 is output from the flip-flop 16. Then, at the same time as the refresh operation ends, both flip-flops 15.1
8, a reset signal RF is transmitted to release the hold state of each signal P4, and the above operations are repeated thereafter.

On the other hand, the held refresh request signal P3
' is also output to the determination circuit 18, and while the request signal P3' is being output, the CPU access request signal p8 is invalidated or waited in the determination circuit 18, and the request signal P3 is inactive (La). Note that the determination circuit 18, which performs the CPU access operation after the CPU is reached, may be provided within the CPt1.

According to this embodiment, the open access request signal P
Even if there is a conflict between the open access request signal P!1 and the CPU access request signal P8, the open access request signal P! The OR circuit 17 may be provided on the input side of the determination circuit 18 so that the 13M access request signal p1 is inputted together with the refresh request signal Pl' so that the determination circuit 18 is executed with priority.

Therefore, according to this embodiment, as shown in the main routine diagram of FIG. 3(a), the DM access request signal pt is not issued (STEP 10), and the CPU access request signal P8 is also not issued. In (STEP 20), if the refresh request signal p3 is issued, (STEP 20)
EP 30) As is well known, while updating the address by the refresh address counter 4, the corresponding D is updated via the refresh address bus 3A and selectors 3a and 3b.
-Perform refresh operation of RAM 2a and 2b, (
STI! P31) On the other hand, if the DM access request signal Pi is issued,
Moving to the subroutine diagram of FIG. 3(b), it is determined here whether there is a conflict between the DM access request signal P1 and the refresh request signal P3, and if the refresh request signal P3 is not issued (STEP II), Corresponding access operations are performed with the D-RAMs 2a and 2b (ST
With EP 12), after the DM access execution is completed, the process returns to the main routine of FIG. 3(a). (STEP) On the other hand, if the two signals PI and P3 conflict, the refresh request signal P3 is held by the flip-flop 15 and the refresh request signal P3 is held by the AND gate 14 because the inverted refresh prohibition signal P2° is input to the AND gate 14. A 0M access is made to the external device while the device is on standby on the input side (STEP 13), and when the ON access is completed, the refresh prohibition signal P is synchronized with this.
2 becomes LO-, the refresh permission signal P4 is output from the AND gate 14, and as a result, the refresh operation can be performed automatically at the same time as D) 1 access is completed (STEP 14), and after the completion of the refresh operation, The process returns to the main routine shown in FIG. 3(a). (ST
EP 15) and after the transition to the main routine (STE
P20) If the CPU access request signal P8 is being output, the process moves to the subroutine diagram of FIG. 3(C), where it is determined whether there is a conflict between the CPU access request signal P8 and the refresh request signal P3°. , if the refresh request signal P3° is not issued (STEP 21),
The CPU access operation is performed between the D-RAMs 2a and 2b (STEP 22), and after the CPU access is completed, the process returns to the main routine of 3C4(a). (S
TEP On the other hand, if the two signals P8 and P3° conflict, the 1 judgment circuit 18 holds the CPυ access request (STEP 22), completes the refresh operation (STEP 23), and then starts the CPU access operation. conduct.

(STEP 24) FIG. 4 is a two-dimensional blow diagram showing the circuit configuration of a print controller using the refresh control section 10.
To briefly explain *, 1 is a CPo that controls the entire controller system based on a predetermined program;
Reference numeral 2 denotes an image memory device constructed by dividing a D-RAM memory area 2a and 2b into two, and the - memory area 2a or 2b is configured to perform DMA processing via a DMA address bus 2A.
While being accessed, the other area is configured to be accessible to CPU I via CPU address bus IA. As a result, while the DMA controller 8 is accessing the - memory area 2a of the memory areas 2a and 2b, the CPU 1 can access the other memory area 2b, and DMA access and CPU access are performed in parallel. I can do things. Note that 9 in the figure is a gate circuit for specifying the area.

3a and 3b are a CPU address bus IA, a DMA address bus 2A, and a refresh address bus 3A;
This is an address selector for selectively connecting the pair of memory areas 2a and 2b.

Reference numeral 4 denotes a refresh address counter, which inputs address signals whose addresses are sequentially updated based on the refresh end signal to the address selectors 3a and 3b via the bus 3A. 5 is a DMA address counter,
Address signals whose addresses are sequentially updated based on signals from the controller 8 are inputted to the address selectors 3a and 3b via the bus 2A.

6 is a refresh timer which sends a refresh request signal p3 of a predetermined period via the CPU 1 to the refresh control unit l.
Send to O.

According to this controller 8, while switching the address selector 3a via the switching circuit 7, the DMA controller 8 sequentially writes -pages worth of image data into the memory areas 2a and 2b, and then prints the image data. It is read out serially based on a control signal from the engine side, but when reading from one memory area 2a is completed, the address selector 3a of that memory area can be switched to access the CPU 1.

On the other hand, regarding the refresh operation, as mentioned above, D
A DMA request signal output from the MA controller 8,
The refresh request signal P3 from the refresh timer G is sent to the refresh control unit IO via the CPU 1, and if there is no conflict between the two request signals within the control unit IO, the refresh request signal P3 from the refresh timer G is sent directly to the address selector 3 via the switching circuit 7.
a, 3b, and if both request signals conflict, D
While giving priority to the MA access request signal, the refresh request signal described above is outputted to the address selectors 3a and 3b via the switching circuit 7 at the same time as the access between the DMA and the memory areas 2a and 2b is completed, and based on the signal, D.M.A.
Address bus 2A and refresh address bus 3A
The corresponding dynamic memory areas 2a and 2b are selectively connected, and a predetermined access operation is performed.

On the other hand, if there is a conflict between the access request signal from CPU I and the refresh request signal P3, the determination circuit in CPU I or the determination circuit 18 in the control unit 10 determines whether the refresh is completed while giving priority to the refresh request signal P3. At the same time, the CPU 1 outputs an access request signal to the address selectors 3a, 3b, and based on this signal, the CPU address bus IA and the refresh address bus 3A are selectively connected to the corresponding dynamic memory areas 2a, 2b, and a predetermined access is performed. An action is taken.

"Effects" As described above, according to the present invention, when a refresh operation and an access request signal of a CPU or a device other than the CPU conflict, instead of selecting one of the operations as -V, the access request signal is By selectively determining the priority order according to the device on the signal oscillation side, D-RAM
The refresh operation, the CPU access, and the access operation of devices other than the CPU can be performed at the most favorable time.This allows smooth refresh operation without reducing the processing power of the device, and also increases the degree of freedom. A special delay or other control circuit for performing refresh processing on a small number of devices other than the CPU is not required, and the circuit configuration is simplified.

Further, in claim 3), the conflicting refresh request signal is held during the access operation of the device, and the refresh operation is performed at the same time as the access operation of the device ends, so that the access is not executed on the CPU side. There is no need to judge which number has ended, and there is no need to send a refresh request signal again, which further simplifies the circuit configuration and reduces the burden on the CPU.

Furthermore, in claim 2), a D-RAM memory device having a plurality of switchable memory areas is used, and the CPU and the CPU
Since the access request signals of devices other than U are transmitted in parallel, high-speed processing of the − layer is possible.

It has various effects such as

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of a refresh control section according to an embodiment of the present invention, and FIGS. 2 and 3 (a) and (b).
) and (c) are a time chart and a flow chart showing the effect. FIG. 4 is a block diagram showing the circuit configuration of a print controller using the refresh control section. Patent source: Kyocera Corporation Figure 1 Figure 2 → t5 ← P8. r-7,, i”-ffi, - Third cause (a) Third (b) Figure 3 (C)

Claims (1)

[Scope of Claims] 1) In a D-RAM refresh control method in a device in which a refresh request signal and an access request signal of a CPU and a device other than the CPU are respectively oscillated asynchronously, When the refresh request signals conflict, the access operation of the device is executed with priority, and on the other hand, when the access request signal of the CPU and the refresh request signal conflict, the refresh operation is executed with priority. 2) A refresh control method characterized by: 2) A D-RAM memory device having a plurality of switchable memory areas is used, and access request signals for a CPU and a device other than the CPU are transmitted in parallel.
Refresh control method described in 3) If the access request signal of a device other than the CPU conflicts with the refresh request signal, the access operation of the device is executed with priority while the refresh request signal is held, and the access operation of the device is The refresh control method according to claim 1, wherein the refresh operation is performed based on the held refresh request signal at the same time as the operation ends.