JP2681484B2 - Refresh control method - Google Patents

Description

The present invention relates to a dynamic memory (hereinafter referred to as a D-RAM).
In particular, the D-RAM used in a control system such as a high-speed printer, a robot, a data collector, etc., in which the D-RAM is directly accessible to a device other than a central processing unit (hereinafter referred to as CPU). RA
M refresh control method.

"Prior Art" Conventionally, a D-RAM having a high integration density and low power consumption is often used as a memory used in a control system such as a high-speed printer, but the D-RAM is a gate storage capacitor. Since the electric charge is accumulated by using the city, the electric charge disappears with time due to a leak current or the like. For this reason, in a control system incorporating the D-RAM, a so-called refresh process in which a clock pulse is periodically applied within a predetermined time to release electric charges is required.

In order to perform such refresh processing, generally, a refresh request signal is forcibly transmitted to the refresh control circuit at predetermined time intervals, and the D-RAM control signal necessary for refresh is transmitted from the control circuit to the D-RAM side. I am trying to refresh, but the refresh cycle is 4 ~
It is performed at an extremely short time interval of about 16 msec. In addition, the clock system for the refresh request signal is configured separately from the clock system for the normal access instruction, so the memory access and refresh operation are inevitable. Are easy to compete.

For this reason, when such a conflict occurs, the memory access request is waited and the refresh operation is performed during that time. However, such a processing method inevitably results in a system that frequently accesses the memory, such as a high-speed printer control system. There is a problem that the operation speed of the memory is lowered.

In order to solve such a drawback, the refresh operation is performed in one machine cycle immediately after the CPU accesses the memory (Japanese Patent Laid-Open No. 59-68892, hereinafter referred to as the first prior art), and the timing signal from the CPU is used. A refresh method in which the timing of the memory access is formed based on the above, while refreshing is performed by utilizing the open time of the memory access period from the memory access to the memory access in the next bus cycle (JP-A-61-22091, (Hereinafter referred to as the second prior art), and further, the access instruction and the refresh request signal are generated by using a single clock source, and the generated access instruction is given a required free time, and during the free time, A refresh method in which an interrupt of a refresh request signal is generated to perform refresh (Japanese Patent Laid-Open No. 61-242). No. 397, hereinafter referred to as third conventional technology), etc., but in both cases, control the memory access timing and the refresh timing based on the reference timing cycle obtained from the CPU, etc., and try to avoid conflict between the two as much as possible. That is the summary.

[Problems to be Solved by the Invention] However, all of the conventional techniques are based on the premise that the D-RAM is accessed via the CPU or under the control of the CPU, and the D-RAM is other than the CPU. There is no workaround for conflicts when directly accessing the device (hereinafter referred to as DM access).

Therefore, like the page printer, the D-RAM is replaced with the image RAM.
Used as a device for controlling the transfer of image data to the image RAM by a DMA controller independent of the operation of the CPU, and access to the image RAM independently of the CPU under the control of the print engine side. It is impossible to adopt the refresh control method in a device that performs the above.

Therefore, in such an apparatus, when the access requests compete with each other, the access request from the DMA or the like is made to wait and the refresh operation is performed in the meantime, but the access request signal from the DMA is transmitted to another device. It is extremely difficult to wait for the access request signal in a control system in which the access request signal is oscillated under the control of the print engine side. When it occurs, DM access is given priority and the refresh operation is
Must be done after DM access is completed.

However, since the DM access is performed with a device other than the CPU, the CPU side cannot judge that the access has been completed unless a special judgment circuit is provided.
If the refresh request signal is oscillated after the determination procedure is performed, the refresh operation time is delayed by that amount, and in the worst case, the stored memory contents change beyond the required refresh cycle time. There is a risk that

In view of the drawbacks of the prior art, the present invention prioritizes the DM access even when the D-RAM is accessed with a device other than the CPU, and smoothly performs the refresh operation within a predetermined refresh cycle time. The purpose is to provide a refresh control method that can be done.

[Means for Solving the Problem] In order to achieve the technical problem, the present invention provides a D-RAM that can be directly accessed with a device other than a CPU, and each of the devices oscillates asynchronously and periodically. In the refresh control method that prioritizes and executes the direct memory access request when the direct memory access request signal and the refresh request signal conflict, it is almost equal to the sum of the pulse width of the direct memory access request and the pulse width of the refresh operation signal. A refresh prohibition pulse generation circuit that periodically generates a pulse width is provided, and when the direct memory access request signal and the refresh request signal conflict, the direct memory access request is preferentially executed, and the refresh prohibition pulse generation circuit Direct message based on the output signal It is characterized in that the refresh request signal is held during the memory access so that the refresh operation is automatically performed after the end of the direct memory access.

Here, "the refresh operation is automatically performed" means that the refresh operation is performed immediately after the DM access is completed by using a flip-flop or the like, without the CPU determining that the access is completed. .

The control can be repeatedly performed by releasing the hold of the refresh request signal after the refresh operation is completed.

[Effect] According to such technical means, when a DM access request signal and a refresh request signal that are difficult to wait or have a high priority conflict with each other in a device other than the CPU, the DM access is preferentially executed. Therefore, when the other device is controlled at the same time as or in parallel with the access, or in the control system in which the request signal is oscillated under the control of the print engine side, the processing capability is lowered. This refresh control method can be used smoothly without incident.

Further, the present technical means, when competing with the DM access, preferentially executes the DM access, but since the refresh request signal is held during the access, the refresh operation is automatically performed almost simultaneously with the end of the DM access. As a result, the refresh operation can be smoothly performed during the required refresh cycle time while giving priority to the DM access.

In addition, since the refresh operation is automatically performed after the DM access is completed, it is not necessary for the CPU side to issue the refresh request signal again without judging that the access is completed. This simplifies the circuit configuration. And CPU
Will reduce the burden on

Further, in the present invention, when the refresh inhibit pulse generating circuit receives the direct memory access request signal, the refresh operation is performed in a section having a pulse width substantially equal to the sum of the pulse width of the direct memory access request and the pulse width of the refresh operation signal. By prohibiting, there is a very practical effect that the direct memory access request signal and the refresh request signal do not conflict with each other and the refresh operation hold time can be minimized.

Hereinafter, preferred embodiments of the present invention will be illustratively described in detail with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but are merely illustrative examples. It's just

FIG. 1 is a block diagram showing a circuit configuration of a refresh controller according to an embodiment of the present invention.

In the figure, 11 is a buffer, 12 is a refresh inhibition pulse generation circuit, 13 is an input negation inverter, 14 is an AND gate, 15
Numerals 16 and 16 are flip-flops which are reset based on the refresh end signal.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

Since the devices other than the CPU access the D-RAM, the DM access request signal P1 oscillated in a predetermined cycle is
Signal P input to buffer 11 and output from buffer
1'is input to the refresh inhibition pulse generation circuit 12.

In the generation circuit 12, a pulse signal having a pulse width t7 that is approximately equal to the sum of the pulse width t5 of the request signal P1 and the pulse width t6 of the refresh operation signal is generated, and the cycle interval of the signal is set to the DM access request signal P1. And a refresh prohibition signal P2 that coincides with the fall (end) timing of the signal. The refresh inhibit signal P2 output from the generation circuit 12 is inverted by the input negation inverter 13 to P2 '.
It is input to the AND gate 14.

On the other hand, the refresh request signal P3, which periodically oscillates asynchronously with the DM access request signal P1, is a flip-flop.
It is input to the other input terminal of the AND gate 14 while being held P3 'by 15. At this time, the refresh inhibition signal P2 is inverted P2 'by the input negation inverter 13 and is input to the AND gate 14. Therefore, the refresh request signal P4 is generated only when the inhibition signal is inactive (L ₀ ). It is input to the flip-flop 16, and the refresh operation signal P5 is output from the flip-flop 16. Upon completion of the refresh operation, a reset signal RF is transmitted to both flip-flops 15 and 16 to cancel the hold state of the signals P3 and P4, and the above operation is repeated.

Therefore, according to such an embodiment, the refresh inhibit signal
When P2 is not output, in other words, when the DM access request signal P1 and the refresh request signal P3 are not in conflict, the refresh operation is performed based on the refresh request signal P3, and both signals P1 and P3 are in conflict. In this case, since the inverted refresh inhibit signal P2 is input to the AND gate 14, the refresh request signal P3 is held by the flip-flop, waits on the input side of the AND gate 14, and the memory access ends. At that stage, the refresh inhibit signal P2 becomes L ₀ in synchronism with this, and the AND gate 14 outputs the refresh request signal P4, which allows the refresh operation to be automatically performed at the same time as the DM access is completed. .

FIG. 3 is a block diagram showing a circuit configuration of a print controller using the refresh control section 10. To briefly explain the configuration, 1 is a CPU for controlling the entire controller system based on a predetermined program, and 2 is a CPU. D-R
In the image memory device configured by dividing the AM memory area 2a, 2b into two, while accessing with the DMA address signal or the refresh signal in one of the memory areas 2a, 2b,
The other area is configured to be accessible by the CPU 1, so that the CPU 1 and any one of the memory areas 2a and 2b can be accessed regardless of the refresh or DM access cycle. Reference numeral 9 in the drawing is a gate circuit for designating the area.

3a and 3b are CPU address bus 1A, DMA address bus 2A,
And an address selector for selectively connecting the refresh address bus 3A and the pair of memory areas 2a, 2b.

Reference numeral 4 denotes a refresh address counter, which inputs address signals sequentially updated based on the refresh end signal to the address selectors 3a and 3b side via the bus 3A. Reference numeral 5 denotes a DMA address counter, which inputs an address signal whose address is sequentially updated based on a signal from the DMA controller 8 to the address selectors 3a and 3b side via the bus 2A.

A refresh timer 6 sends a refresh request signal P3 of a predetermined cycle to the refresh controller 10 via the CPU 1.

According to such a controller, the DMA request signal output from the DMA controller 8 and the refresh request signal P3 from the refresh timer 6 via the CPU 1 are transmitted to the refresh control unit 10, and the control unit 10 executes both When the request signals do not conflict with each other, the signals are output to the address selectors 3a and 3b through the switching circuit 7 as they are. When the request signals conflict with each other, the DMA access request signal is prioritized and the DMA and the memory areas 2a and 2b Simultaneously with the end of the access, the above-mentioned refresh request signal is output to the address selectors 3a and 3b via the switching circuit 7, and the CPU address bus 1A, the DMA address bus 2A and the refresh address bus 3A are supported based on the signals. Dynamic memory area 2a, 2b
And a predetermined access operation is performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a refresh controller according to an embodiment of the present invention, and FIG. 2 is a time chart diagram showing its operation. FIG. 3 is a block diagram showing a circuit configuration of a print controller using the refresh controller.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-50-102226 (JP, A) JP-A-50-135949 (JP, A)

Claims (1)

(57) [Claims] 1. A D-RAM capable of directly accessing a device other than a CPU, wherein the direct memory access request signal and the refresh request signal of the device, which are asynchronously oscillating periodically, conflict with each other In a refresh control method for prioritizing access requests, a refresh inhibit pulse generation circuit is provided for periodically generating a pulse width substantially equal to the sum of the pulse width of a direct memory access request and the pulse width of a refresh operation signal, When the direct memory access request signal and the refresh request signal conflict, the direct memory access request is preferentially executed, and the refresh request signal is held during the direct memory access based on the signal output from the refresh inhibit pulse generation circuit. Then Refresh control method being characterized in that to perform the direct memory access completion after automatically refresh operation.