JPH0619776A - Memory control system - Google Patents

Abstract

PURPOSE:To prevent the processing ability of a device from deterioration at the time of switching a clock frequency to a low speed. CONSTITUTION:A specifying means 60 specifies the speed of a clock to a high or low speed and a counting means 10 counts a clock number generating after a storage means 50 is started. A first decision means 41 decides a timing when reading data becomes effective based on a count value counted by the counting means 10 in a period since the storage means 50 is started till effective data is read out when the device is operated by a high-speed clock and a second decision means 42 decides a timing when reading data becomes effective based on a count value which is smaller than that at the time of operation by a high- speed clock when the device is operated by a low-speed clock. A selection means 40 selects the timing decided by the first or second decision means 41 or 42 based on the specification by the specifying means 60 and an information processor reads and processes data read from the storage means 50 based on the timing selected by the selection means 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system. In particular, the present invention relates to a memory control method capable of preventing a reduction in the processing capability of an information processing device when the operating frequency is switched from high speed to low speed.

In recent years, complementary metal oxide semiconductors (CMOS) with low power consumption have been widely used as circuit elements constituting workstations, handy terminals and the like. CMOS has a property that power consumption is low in a steady state and power consumption is high at the time of switching between conduction and interruption. In addition, a device that uses a battery as a power source or that uses a commercial alternating current (AC) power source and a battery together is widely used so that it can be carried and moved. In a device that uses both an AC power source and a battery, various low power consumption methods are used to keep the battery operating time long. One method is to switch the operating frequency of the information processing device. is there. That is, when operating with an AC power supply (hereinafter referred to as AC mode), it is not necessary to suppress power consumption, so that the device operates at a high-speed frequency (for example, 20 MHz) as long as the device allows, and when operating with a battery (hereinafter , Battery mode), a method of operating at a low frequency (for example, 16 MHz) is generally used in order to reduce the power consumption by reducing the switching frequency of conduction / cutoff of CMOS. However, since the information processing apparatus generally has a low processing capacity when operated at a low frequency, a memory control method capable of preventing the deterioration of the processing capacity is desired.

[0003]

2. Description of the Related Art FIG. 6 is a diagram showing an example of a memory interface, FIG. 7 is a timing diagram showing an example of memory control in an AC mode, and FIG. 8 is a timing diagram showing a memory control of a conventional example in a battery mode.

Throughout the drawings, the same reference numerals indicate the same or similar components. Memory control in the AC mode is performed as shown in FIG. 7 using the memory interface shown in FIG. Device (eg, microprocessor: MP
U) supplies the row address of the data to be accessed to the memory from the leading edge of the clock S0 to the address bus (MADR).
ES) and a * RAS (Row Address Strobe) signal, which indicates that the row address on MADRES is valid, is made LOW at the trailing edge of the clock S0 (where * represents a negative logic). Next, a column address is given to MADRES from the trailing edge of clock S1 to indicate that the column address on MADRES is valid * CAS (Column Address S
trobe) signal LOW at the trailing edge of clock S2. Also, when performing a memory read operation, set the * OE signal to L
OW. (When performing a memory write operation, * W
The E signal is set to LOW. ) * A predetermined time after the CAS signal becomes LOW, in this case, between the clocks S4 and S5, data is read from the memory onto the data bus (DATA). The device reads (or captures) this data on the trailing edge of clock S6, as well as * RAS and *.
The CAS signal is set to HIGH to complete the memory access.

FIG. 8 is a timing chart of the conventional memory control in the battery mode, showing a case where the clock is operated at a low frequency in order to reduce power consumption. Similar to the case of FIG. 7, data is read out from the memory onto DATA after a predetermined time has passed since the * CAS signal becomes LOW, in this case, between the clocks S3 and S4. The device uses this data as in the AC mode of FIG.
* RAS and * C as well as reading at the trailing edge of clock S6
The AS signal is set to HIGH to complete the memory access.

[0006]

Although the access control of the memory is performed in synchronization with the clock, according to the conventional method as described above, the memory control in the battery mode is performed similarly to the control in the AC mode. Therefore, if the operating frequency or the clock frequency is simply lowered in the battery mode, the memory access time is effectively lengthened, and the system performance is significantly lowered.

It is an object of the present invention to provide a memory control system capable of preventing a decrease in the processing capacity of an information processing device when the operating frequency is switched from high speed to low speed.

[0008]

FIG. 1 shows a block diagram of the principle of the present invention. Reference numeral 50 designates a storage means for reading out valid data after a predetermined time has passed since activation, and 60 designates a designation means for designating a clock speed at which the information processing device operates to a first speed or a second speed lower than the first speed. , 10 are storage means 50
When the information processing apparatus operates at the first clock speed, the counting means 41 for counting the number of clocks generated after the start of the memory is started during the period from the activation of the storage means 50 until the reading of valid data. A first deciding means for deciding a timing at which the data read from the storage means 50 becomes valid based on the count value counted by the counting means 10;
When the information processing device operates at the second clock speed,
The second deciding means 40 for deciding the timing at which the data read from the storage means 50 becomes valid based on the count value smaller than the value counted by the counting means 10 during the operation at the first speed is the designating means. It is a selection unit that selects the timing determined by the first determination unit 41 or the second determination unit 42 based on the designation of 10.

[0009]

According to the present invention, in the information processing apparatus having the storage means 50 for reading out valid data after a predetermined time has passed since the start-up, the designating means 60 sets the clock speed at which the information processing apparatus operates to the first speed, Alternatively, the second speed which is slower than that is designated, and the counting means 10 counts the number of clocks generated after the storage means 50 is activated. First determining means
Reference numeral 41 is read from the storage means 50 based on the count value counted by the counting means 10 during the period from the activation of the storage means 50 to the reading of valid data when the information processing device operates at the first clock speed. When the information processing device operates at the second clock speed, the second determining means 42 determines the timing at which the stored data becomes valid, and the second determining means 42 has a count value smaller than the value counted by the counting means 10 at the first speed. Based on, the timing at which the data read from the storage means 50 becomes valid is determined. The selecting means 40 is based on the designation of the designating means 10 and is based on the designation by the first determining means 41 or the second determining means 42.
The information processing device reads the data read from the storage means 50 based on the timing selected by the selection means 40 and performs processing. Therefore, the information processing device, when operating at the second clock speed, stores the data read from the storage means 50
From the time of operation at the first clock speed, the reading and processing are performed earlier in relation to the clock.

[0010]

2 is a block diagram of memory control according to an embodiment of the present invention, and FIG. 3 is a timing chart of memory control according to an embodiment of the present invention in a battery mode. Throughout the drawings, the same reference numerals indicate the same or similar components.

In view of the problems of the conventional example, the present invention prevents the deterioration of the processing capability of the information processing device by switching the operating frequency from high speed to low speed by performing memory control based on the following two methods. .

Method 1: Memory (Dynamic RAM: D
In the case of RAM), since the time from when the * CAS signal becomes valid until the data is read is constant, the number of waiting clocks until the data is read can be reduced during low-speed clock operation. For example, as shown in FIG. 7, when the clock is operating at high speed, the data is clock S5.
Although it is determined by S4, it is determined by S4 during the low speed operation shown in FIG. Therefore, as shown in FIG. 3, when the clock is operated at low speed, the timing (access time) for fetching data is set to 1
By making the clock faster and fetching in S4, the memory access time, and thus the cycle time, can be effectively shortened.

Therefore, according to the AC mode (during high-speed operation of the clock) or the battery mode (during low-speed operation of the clock), the clock for fetching the read data from the memory is switched to S5 or S4, respectively, to access the memory. Higher speed can be realized.

Method 2: Furthermore, in order to optionally switch the power supply from the AC power supply to the battery or vice versa while operating the information processing apparatus, the acquisition clock is dynamically changed (S5 and S4). Must be switched). At this time, if the fetch clock is changed during the operation of the memory access, for example, at the time of the read access, a malfunction such as fetching the undetermined data on the address bus (MADRES) may occur.

The present invention realizes a high speed memory access by switching the fetch clock while preventing this inconvenience by the method shown in FIG. FIG. 2 is a block diagram showing an embodiment of the present invention.

The microprocessor (MPU) 1a is a dynamic RAM via a common bus interface 9a.
The program stored in 5a (hereinafter referred to as DRAM) is read and the program is executed.

The direct memory access controller (DMAC) 2a is connected to the DMA sequencer 4a via the common bus interface 9a, and transfers data between the DRAM 5a and various input / output devices 20 without passing through the MPU 1a. Control to do it directly.

The DRAM sequencer 4a performs interface matching between the common bus interface 9a and the memory interface 45. That is, MPU1a or DMAC2a
Then, when there is an access request to the DRAM 5a via the common bus interface 9a, the signal on the memory interface 45 is controlled (for example, see FIG. 6) to read / write data from / to the DRAM 5a. For example, at the time of read access, read data from the DRAM 5a is directly supplied to the common bus interface 9a.
The M sequencer 4a guarantees that the read data is valid by outputting the DACK signal to the common bus interface 9a.

The bus master arbitration unit 3a uses the MPU 1a and the DMA.
When a plurality of accesses from the C2a or the like to the DRAM 5a occur at the same time and compete with each other, the preferential access (for example, the access from the DMAC2a) is permitted according to a predetermined priority order. That is, when accessing the DRAM 5a, the permitted MPU 1a or DMAC 2a becomes the bus master, and the address signal (ADDRESS) and address strobe signal (AS) are placed on the common bus interface 9a.
Is output to access the DRAM 5a. There is always only one device that can be the bus master and can access the DRAM 5a, and the right to operate the bus master is called the bus master right. MP
U1a and DMAC2a respectively output a bus master right request signal (BR) to the bus master arbitration unit 3a to acquire a permission signal (BG) from the bus master arbitration unit 3a, and the device which has acquired the bus master right responds with a BGACK signal. To do.

The access switching unit 4s is a DRAM sequencer
4a and performs the functions of Method 1 above. That is,
Based on an H / LSPD signal from a mode detection unit 6a, which will be described later, the timing for outputting the DACK signal indicating that the read data from the DRAM 5a is valid on the common bus interface 9a is switched. For example, the DACK signal is sent to the acquisition clock S5 or S4 in the above method 1.
The timing is controlled so that it becomes active with. In this way, depending on whether AC mode or battery mode, D
The RAM 5a can be switched between high speed access (see FIG. 7) and low speed access (see FIG. 3). Further, the clock frequency is controlled to, for example, 20 by controlling the clock generator 1c.
Switch between megahertz and 16 megahertz. FIG. 4 is a circuit diagram illustrating the access switching unit 4s. H / LSPD
When the signal is on (high-speed access), the clock S4 is input to the delay circuit DL via the AND circuit A1 and the OR circuit OR, delayed, latched by the latch circuit L, and turned on at the leading edge of the clock S5. Output DACK. Similarly, H / L
When SPD signal is off (low speed access), clock S4
Output a DACK that becomes active on the leading edge of.

The mode detector 6a includes an MPU 1a and a DMAC 2a.
The function of Method 2 is performed by ensuring a time during which no access to the DRAM 5a occurs from the above, and switching the access time during that time. That is, the signal AC / BAT indicating whether the power supply of the present apparatus is supplied from the AC or the battery is input from the power supply unit 7a to constantly monitor whether the power supply mode is the AC mode or the battery mode. A
When the mode is changed from the C mode to the battery mode or vice versa, the BR signal is output to the bus master arbitration unit 3a to request the bus mastership. When the bus mastership is acquired by receiving the BG signal, the DRAM 5a is currently
DR is guaranteed because no access is made
The AM sequencer 4a is instructed to change the H / LSPD signal to switch to high speed or low speed access. After that, the BGACK signal is negated and the bus mastership is relinquished.

The operation of the embodiment of the present invention will be described with reference to the flowchart of FIG. (1) The mode detection unit 6a constantly monitors the power supply unit 7a and inspects whether the power supply mode has changed from the AC mode to the battery mode or vice versa. (2) When a change in the power supply mode is detected, the mode detection unit 6a outputs a BR signal to the bus master arbitration unit 3a to request the bus mastership. (3) When the mode detector 6a receives the BG signal and acquires the bus mastership, it outputs the H / LSPD signal to the DRAM sequencer 4a by changing the ON / OFF state according to the change of the power supply mode. , Instruct to switch to high speed or low speed access. After that, the BGACK signal is negated and the bus mastership is relinquished. (4) When the H / LSPD signal is on, the access switching unit 4s of the DRAM sequencer 4a switches the access of the DRAM 5a to high speed access. That is, at the time of read access, for example, as shown in FIG. 7, the DACK signal is controlled to be output at the timing when the read data becomes valid at the clock S5. Further, the clock frequency is switched to, for example, 20 MHz by controlling the clock generator 1c. (5) Access switching unit 4s when H / LSPD signal is off
Switches the access of the DRAM 5a to the low speed access. That is, during read access, for example, as shown in FIG. 3, the DACK signal is controlled to be output at the timing when the read data becomes valid at the clock S4. Also,
The clock frequency is switched to, for example, 16 MHz by controlling the clock generator 1c.

In this way, the present invention provides a clock frequency and DRA depending on whether it is in AC mode or battery mode.
The memory access time of M5a is dynamically switched using a period in which no access to DRAM5a occurs. Therefore, in the battery mode, the power consumption of the device is reduced by operating the device with a low frequency clock and reducing the frequency of conduction / interruption of the CMOS circuit.
In addition, the performance of the device can be prevented from decreasing by making the access time of the memory relatively short and the cycle time short relative to the clock speed switched to the low speed. Most of the processing capability of the information processing device is determined by the memory access time and the cycle time. Therefore, even if the clock speed is reduced, the memory control is performed in this way so that the processing capability of the device is not degraded. Very few.

In the above embodiment, the number of data wait clocks from the * CAS signal is changed, but it is obvious that the timing of outputting the * RAS signal or * CAS signal may be changed. ， It may be optimally set according to the performance of the memory used and the clock cycle of the system.

Further, although the example of the read operation of the memory has been described in the above embodiment, the present invention is similarly applied to the write operation. That is, based on the clock
By operating the low-speed clock, by outputting the DACK signal earlier than during high-speed clock operation,
The memory access time, and hence the cycle time, can be shortened compared to the conventional example.

[0026]

As described above, according to the present invention,
In an information processing device that uses both an AC power source and a battery,
Since the clock frequency and the access time of the memory, and thus the cycle time, are dynamically and safely switched depending on whether the power supply is in the AC mode or the battery mode, the device can be operated at high speed in the AC mode, and In battery mode, minimize the deterioration of device performance,
There is an effect that the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram of memory control according to an embodiment of the present invention.

FIG. 3 is a timing diagram of memory control according to an embodiment of the present invention in a battery mode.

FIG. 4 is a circuit diagram illustrating an access switching unit.

FIG. 5 is a flowchart for explaining the operation of the embodiment of the present invention.

FIG. 6 is a diagram showing an example of a memory interface.

FIG. 7 is a timing diagram of an example of memory control in AC mode.

FIG. 8 is a timing diagram of a conventional memory control in a battery mode.

[Explanation of symbols]

10 Counting means 40 Judging means 41 First deciding means 42 Second deciding means 50 Storage means 60 Designating means 1a Microprocessor unit (MPU) 1c Clock generator 2a Direct memory access controller (DMA
C) 3a Bus master arbitration unit 4a DRAM sequencer 4s Access switching unit 5a Dynamic RAM (DRAM) 6a Mode detection unit 7a Power supply unit 9a Common bus interface 20 I / O device 45 Memory bus interface

Claims (3)

[Claims] 1. In an information processing apparatus having a storage means (50) for reading out valid data after a predetermined time has passed since it was started up, a clock speed at which the information processing apparatus operates is set to a first value.
(60) for specifying the second speed which is slower than the above, and a counting means (10) for counting the number of clocks generated after the storage means (50) is activated, and an information processing device. Is operating at the first clock speed, the storage means
Timing at which the data read from the storage means (50) becomes valid based on the count value counted by the counting means (10) in the period from the activation of (50) until the reading of valid data Based on a count value smaller than the value counted by the counting means (10) when the information processing device operates at the second clock speed when the information processing device operates at the second clock speed. The second deciding means (42) for deciding the timing at which the data read from the storage means (50) becomes valid, and the first deciding means (based on the designation by the designating means (10). 41) or a selection means (40) for selecting the timing determined by the second determination means (42), and the information processing device selects the data read from the storage means (50). Based on the timing selected by the means (40), the reading and processing are performed. A memory control method characterized by: 2. The information processing apparatus further comprises an acquisition means (6) for acquiring a memory cycle of the storage means (50).
0) is provided, the specifying means (60) specifies a clock speed, and the selecting means (40) selects a timing in the period acquired by the acquiring means (60). Memory control method. 3. The memory according to claim 1, wherein the designating unit (60) designates a clock speed according to whether the power supplied to the information processing device is a commercial AC power supply or a battery. control method.