JPH08278943A - Shared bus control system - Google Patents

Abstract

PURPOSE: To prevent a process from being delayed by limiting the common bus occupation time of a processor. CONSTITUTION: A timer means 12 outputs a timer signal pulse 23 at each constant period. A counter means 13 which is reset with the timer signal 23 cumulates and calculates the time for which a common bus in-use signal 27 is ON and outputs common bus cumulative use time data 24. A comparing means 14 compares the common bus cumulative use time data 24 with a previously set limit value and outputs a request limit signal 25 when the limit value is exceeded. A limiting means 15 receives an other-module access command signal 21 from the processor 11 when the request limit signal 25 is off to output a shared bus use request signal 22 to a common bus 10 immediately, and after a conflict with another module is arbitrated on the shared bus side, a shared bus use acknowledgement signal 26 is sent; and the processor 11 outputs a shared bus in-use signal 27. When the request limit signal 25 is on, the limiting means 15 does not output the shared bus use request signal 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared bus control system for a data processing device, and more particularly to a shared bus control system for a data processing device in which a plurality of processors are connected to a shared bus.

[0002]

2. Description of the Related Art The hardware of a numerical control device (hereinafter referred to as CNC) is composed of a plurality of modules having various control functions and a shared bus for connecting the modules to each other. A module is a block that shares various control functions required by the CNC such as execution of a machining program, control of a machine sequence, and display operation. A dedicated processor is built in each module, and each module handles data processing. The modules are connected to a shared bus, through which data is exchanged between the modules. Thus, the CNC has a so-called multiprocessor configuration.

FIG. 6 is a diagram showing a schematic structure of a conventional CNC. The CNC control module 100 is a module that performs basic functions of the CNC such as execution of a machining program. The PMC control module 200 is a module that processes input / output signals and performs sequence control of a machine tool.
The MMC control module 300 can display, input, etc.
It is a module that manages the man-machine interface between the operator and the CNC.

The hardware components of each module are as follows. CNC control module 1
Taking 00 as an example, the processor 101 is a microprocessor that processes data. The local bus 105 is
The address bus and data bus of the processor. The local RAM 102 is a random readable / writable memory, and stores programs executed by the processor and processing data. The local bus is connected to the shared bus 10 via the buffer 103. Bus controller 10
A controller 4 receives an access request from the processor 101 to another module and controls the common bus. Control signals 106 are processor control signals for the common bus.

Although such a configuration is basically common to all modules, each module also has its own constituent elements. The PMC control module has an I / O interface 20 for connecting to an external I / O unit 90.
8 is built in. The MMC control module also has a display / operation interface 308 for connecting to the display / operation unit 91.

Although each module is basically independent and processes data in parallel, it is never related to each other and exchanges data with each other through the shared bus 10. As an example of such data exchange, CNC I / O processing will be described below. The signals of various switches and lamps on the operation panel of the machine tool, and the signals of various sensors and actuators attached to various parts of the machine body are connected to the I / O unit 90 and transmitted to the PMC control module 200. The processor 201 accesses this through the I / O interface 208 and performs processing according to the sequence control program. In this sequence processing, interface information with the processor 101 that performs CNC control is necessary as data. Therefore, the processor 101 of the CNC control module uses the local RAM 2 of the PMC control module as shown in the path 412 of FIG.
The interface information is transferred to a certain area 02.
This information transfer is repeated at regular intervals.

[0007]

However, if the shared bus is occupied by another processor and cannot be used immediately, a delay occurs in information transfer that should be performed at a constant cycle. As a result, for example, if the actuator of the machine tool controlled by the CNC misses the timing at which it should operate and operates with a delay, in the worst case, it may even lead to damage of the machine.

In other words, the CNC is a real-time processing system, and if the necessary processing is not completed within the time predetermined at the time of designing, the operation of the entire system will be seriously hindered. Here, the I / O processing has been described as an example, but similar real-time processing is also required for servo control and communication control in DNC operation.

The problem with the shared bus as described above is as follows.
This may occur in the case where the processor 301 of the MMC control module accesses the other module very frequently, as shown in the path 431 or the path 432. In order to prevent the problem of time delay due to access contention, access from the processor 301 to other modules can only be restricted to some extent.

Conventionally, as such a limiting means, in the control program of the processor 301, there is no way but to consider by software so as not to access other modules too often. That is, at the time of program development, how much the program accesses other modules per unit time (that is, how much common bus is occupied) is estimated, and this affects the operation of the entire CNC system. Evaluate whether there is a possibility and if there is inconvenience, reduce the frequency of access,
It is the work of inserting waiting time with software and adjusting. There is a problem that such a work is troublesome and the performance of the completed program is deteriorated when waiting time is put.

The program executed by the MMC control module is for controlling display and man-machine interface, and is used for customizing the CNC to realize an optimum display operation method for each type of machine tool. To be done. In some cases, commercially available software may be installed as it is. From the standpoint of commercially available software, simply reading a file on the CNC side actually results in continuous occupation of the shared bus. Even a few milliseconds can be fatal for a CNC that is performing real-time processing at the same cycle. However, it is almost impossible to expect the software created by a third party who is not familiar with such properties with the measures such as the evaluation and adjustment of the shared bus occupancy ratio as described above.

The present invention has been made in view of the above circumstances, and determines the shared bus occupancy rate by a specific processor.
The purpose is to provide a means for automatically adjusting regardless of software measures, and to solve the problem of processing delay due to access conflict of shared bus in real-time processing that generally has no time margin. To do.

[0013]

In order to solve the above-mentioned problems, the present invention cumulatively calculates the time when a processor uses a shared bus and a timer means which outputs a timer signal at a constant cycle. A resetting counter means, a comparison means for comparing the cumulative calculation result with a preset limit value, and outputting a request limit signal when the cumulative calculation result exceeds the limit value, and the request limit A limiting means for receiving the signal and holding the shared bus use request from the processor is provided.

[0014]

The counter means cumulatively calculates the shared bus use time within the period of the timer signal generated by the timer means.
The comparing means notifies the limiting means as a request limiting signal that the cumulative use time calculated by the counter means has exceeded the limit value. The limiting means receives the request limiting signal and holds the other module access command from the processor.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a shared bus control system of the present invention. The figure shows the configuration of a bus controller that requests the use of the shared bus 10 based on the shared bus request from the processor 11.

The timer means 12 outputs a pulsed timer signal 23 at preset constant intervals. The counter means 13 cumulatively calculates the time when the shared bus busy signal 27 is on. The counter means 13 is reset by the timer signal 23.
Therefore, the output of the counter means 13 becomes the time when the processor used the shared bus after the generation of the timer signal, that is, the shared bus accumulated use time data 24.

The comparison means 14 compares the shared bus accumulated use time data 24 with a preset limit value, and outputs a request limit signal 25 when the limit value is exceeded. When the request limiting signal 25 is off, the limiting means 15 receives the other module access command signal 21 from the processor 11 and immediately outputs the shared bus use request signal 22 to the shared bus. When the shared bus use request signal 22 is output, the shared bus side arbitrates competition with other modules and then the shared bus use permission signal 26 is sent. In response to the shared bus use permission signal 26, the processor outputs the shared bus busy signal 27, and the counter means accumulates the time.

However, when the request limiting signal 25 is on,
The request of the processor is held by the limiting means 15, and the shared bus use request signal 22 is not output. Next, the overall operation of the shared bus control system of the present invention will be described with reference to the state transition diagram of FIG. [S0: Initial State] The counter means 13 is in a reset state, and is in this state after the power is turned on. When the timer signal 23 turns off, the process proceeds to state S1. [S1: Normal state] The reset of the counter means 13 is released, and the shared bus use time of the processor 11 is cumulatively calculated. In this state S1, the request limit signal 25 is in the off state, and the other module access command signal 21 from the processor 11 is output as it is to the shared bus as the shared bus use request signal 22. Therefore, the processor 11 can immediately use the shared bus as long as the shared bus 10 is free. When the timer signal 23 is turned on, the state returns to state S0. However, if the counter value exceeds the limit value before the timer signal is turned on, the state transitions to state S2. [S2: Limit state] The shared bus use time cumulative value 24 has already exceeded the limit value, and the request limit signal 25 is in the on state. At this time, the shared bus request command signal 21 from the processor is suspended and the shared bus use request signal 22 is not output. When the timer signal 23 is turned on, the state transitions to state S0.

Next, specific examples using the present invention will be described. FIG. 3 is a circuit configuration diagram of a bus controller according to the shared bus control system of the present invention. This bus controller is particularly effective when applied to the MMC control module in the configuration of the conventional numerical controller shown in FIG.

First, the procedure when the processor uses the shared bus will be described. When the processor 11 accesses another module via the shared bus,
First, other module access command signal 21 is turned on (1)
To This signal is output as the shared bus use request signal 22 via the selector 35. The request limiting signal 25 connected to the selection input S of the selector 35 is off (0) in the normal state. On the shared bus side, the shared bus use permission signal 26 is returned after arbitrating the competition with other modules. When the use of the shared bus is permitted, the processor 11
Outputs a shared bus busy signal 27 which is a strobe signal for actual access.

The timer 32 divides the 1 MHz clock output signal generated by the clock oscillator 31 by 2000,
A timer signal 23 having a pulse width of 1 μS is output at a cycle of 2 mS.

The counter 33 is a synchronous counter that operates with the same clock signal and counts clocks while the shared bus busy signal 27 is on. The timer signal 23 is connected to the reset input RES of the counter, and the count value is reset to zero every 2 mS.
Since the clock is 1 MHz, when the output of the counter is, for example, a decimal number 20, it means that the shared bus use time is 20 μS in total.

The count output of the counter 33 is the comparator 34.
Of the limit value register 38, which is connected to the B input of the. The limit value register 38 is
It is set in advance by the processor 11, and its value is, for example, 100 (that is, 100 μS equivalent). When the B input exceeds the A input, the comparator output turns on. This is the request limit signal 25.

The delay circuit 36 delays the signal for a fixed time Td according to a delay time register 37 set in advance by the processor. 2 here
It is assumed that a delay of 00 μS is set. The gate 39c has NOT logic and is connected to the reset terminal RES of the delay circuit. Therefore, when the other module access command signal 21 is off, the delay circuit 36 is initialized and the output is off.

The selector 35 is a 2-input selection circuit. When the request limiting signal 25 is off, the other module access command signal 21 is selected, and when it is on, the delay circuit output 28 is selected, which is the shared bus. The usage request signal 22 is driven.

The operation of the above circuit is shown in the time chart of FIG. Although the timer signal 23 is output in a cycle of 2 mS, the figure shows two cycles, and the first half shows a case where access from the processor to other modules is relatively small, and the second half shows conversely a large case.

In the first half, the other module access command signals 21 are sporadically output from the processor, and the shared bus use request signal 22 is output accordingly.
Following each request, the shared bus use permission signal 26 shown in FIG.
Is returned to the processor, and the shared bus busy signal 27 is turned on. Therefore, the shared bus accumulated use time data 24, which is the output of the counter 33, gradually counts up as shown in the figure. When 2 mS has elapsed and the timer signal 23 is generated, the counter 33 shown in FIG. 3 is reset. During this time, the count value of the counter 33 does not reach the limit value, so the request limit signal 25 also remains off.

On the other hand, in the latter half of 2 mS, the shared bus access of the processor is frequently performed, and the shared bus accumulated use time data 24 output from the counter 33 is rapidly counted up accordingly. When the value eventually exceeds the limit value of 100, the request limit signal 25 is turned on, and the count enable input EN of the counter 33 changes to NOT.
Since it is turned off by the gate 39a and the AND gate 39b, the counter 33 does not count any more.
However, since the output of the counter has already exceeded the limit value, the request limit signal 25 does not turn off until the counter is reset by the timer signal 23.

FIG. 5 shows the signal waveforms before and after this (from time t1 to t2) in an easy-to-understand manner by expanding the time axis. As shown in FIG. 5, when the request limiting signal 25 is turned on, the shared bus use request signal 22 is not immediately output even if the processor attempts to access another module, but is temporarily suspended. Then, after the time Td set in the delay time register, that is, 200 μS has elapsed,
The shared bus use request signal 22 is output.

As described above, in the present embodiment, the processor 11 is used up to a total of 100 μS in the timer period of 2 mS.
Can use the shared bus freely, but beyond that, 20
It can only be used once at 0 μS. Therefore, in the meantime, other processors can use the bus.

In the above description, the delay time is set to 200 μS, but it is set to 1.9 mS (timer period
It is also possible to set the limit value register setting value) or more or delete the delay circuit itself. In this case, as described in the schematic configuration of the present invention in FIG. 1, the operation for suspending the other module access command signal is performed until the next timer signal is generated.

Further, in the above description, the shared bus control method of the present invention is applied to only a specific module in the data processing device, but it is also possible to apply this to all modules. In that case, the limit value and the delay time may be determined in consideration of the characteristics of each module.

Further, in the above description, the limit value and the delay time can be set by software by the limit value register 37 and the delay time register 38, but they can be simplified and fixed. However, it goes without saying that the software-configurable method as in the present embodiment allows the shared bus usage time of the processor to be finely managed according to the configuration and scale of the entire data processing device.

[0034]

As described above, according to the present invention, the usage time of the shared bus by a specific processor is accumulated and the usage request to the shared bus is limited accordingly. It becomes possible to adjust automatically regardless of the above measures. Therefore, in real-time processing with no time margin, the problem of processing delay due to access conflict on the shared bus is eliminated, and the reliability of the data processing device is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a shared bus control system of the present invention.

FIG. 2 is a state transition diagram showing a state transition of shared bus control according to the present invention.

FIG. 3 is a circuit configuration diagram of a bus controller according to a shared bus control system of the present invention.

FIG. 4 is a time chart showing the operation of the bus controller according to the shared bus control system of the present invention.

FIG. 5 is an enlarged view of the time chart of FIG. 4 showing the operation of the bus controller according to the shared bus control system of the present invention.

FIG. 6 is a diagram showing a schematic configuration of a conventional numerical control device.

[Explanation of symbols]

 10 shared bus 11 processor 12 timer means 13 counter means 14 comparing means 15 limiting means 21 other module access command signal 22 shared bus use request signal 23 timer signal 24 shared bus accumulated use time data 25 request limit signal 26 shared bus use enable signal 27 Shared bus busy signal

Claims (5)

[Claims] 1. In a shared bus control system of a data processing device in which a plurality of processors are connected to a shared bus, a timer means for outputting a timer signal at a constant cycle, and a processor cumulatively calculates the time when the shared bus is used. Comparing means for comparing the cumulative calculation result with a preset limit value, and outputting a request limiting signal when the cumulative calculation result exceeds the limit value. A shared bus control system comprising: a limiting unit that receives the request limiting signal and holds a shared bus use request from a processor. 2. The shared bus control system according to claim 1, wherein the limiting means releases the hold after a preset delay time has elapsed. 3. The shared bus control system according to claim 2, wherein the delay time can be set by a processor. 4. The shared bus control system according to claim 1, wherein the limit value can be set by a processor. 5. The shared bus control system according to claim 1, wherein the data processing device is a numerical control device.