JPS592584Y2 - Microprogram expansion test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a microprogram-based test mechanism in a microprogram-controlled data processing device, and particularly to a device for expanding the number of points to be tested.

In a conventional microprogram-controlled data processing device, a test using a microprogram is performed using a control storage unit 1 that stores a microprogram, as shown in FIG.
The microinstruction read from microinstruction register 2
The three bits of the test field 2a are supplied to the multiplexer 3.

The eight input terminals 4□ to 48 of the multiplexer 3 are given respective states of the eight test points, and one of the input terminals 4□ to 48 is selected depending on the state of the 3 bits in the test field 2a of the microinstruction. output terminal 5
will be output to and tested.

Since the address of the microinstruction to be read next is determined by the state of “1” or “0” of the output terminal 5, that is, the test result, the output of the output terminal 5 is the address generation circuit 6 for the control storage unit 1. fed into one pit.

When the number of points to be tested increases, as shown in FIG. A selection signal for selecting and supplying its state to the output terminal 9 is applied from the D1 field 2a of the microinstruction register.

A field 2b for selecting either multiplexer 3 or 8 is provided in microinstruction register 2, and multiplexer 3 or 8 is selected depending on whether 1 bit of field 2b is "1" or "0". .

That is, the output of field 2b is applied to gate G1, and its inverted output is applied to gate G2. Gates G1 and G2 are respectively supplied with the outputs of multiplexers 3 and 8, and gates G1. The output of G2 is supplied to address generation circuit 6 through OR gate G3.

Since the number of test points has been expanded in this way, the gate G1. G
2. As the number of logic circuits such as G3 increases, it takes longer for the output of the multiplexer to reach the address generation circuit 6.

When the time to create an address becomes longer in this way,
It becomes impossible to complete the process from reading a microinstruction to completing address creation within one machine cycle.

Therefore, it is necessary to lengthen the machine cycle or increase the bit width of the microinstruction, and to use a multiplexer with a large number of input terminals.

The former will reduce the processing speed of the microprogram control processor, and the latter will reduce the capacity of the control storage unit,
This increases the capacity of various registers, making them expensive.

The purpose of this invention is to provide a microprogram expansion test device that can easily increase the number of microtest points while minimizing the increase in machine cycle time and microinstruction bit width.

According to this invention, a multiplexer is provided which inputs the states of a plurality of extended microprogram test points, and a test field of a microinstruction is applied to the multiplexer to select one state of the extended test points. , this selected state is maintained under the control of microinstructions.

A subsequent microinstruction supplies the held output to one input terminal of a multiplexer to which the state of the test target point before expansion is given.

In this way, the number of tests for the expanded test target points is reduced, and two machine cycles are required for the test.

However, this extension does not require an increase in the length of one machine cycle, nor does it require a significant increase in the bit width of the microinstruction.

For example, there are quite a few points that do not need to be tested at high speed, such as micro-test points for operations related to manual commands and micro-diagnosis, and such test points may be used as extended test points.

Also, although the test takes two microsteps, since another job is often executed in parallel with the microtest, the processing capacity hardly decreases.

FIG. 3 shows an example of a microprogram expansion test device according to this invention, in which a microinstruction register 10 holding microinstructions read from a control storage unit has microfields 11-15.

The states of each of the 16 test points before expansion are 8 each at the input terminals 15□ to 1 of the first multiplexers 40 and 50.
58 and 16□ to 168, respectively.

One of the eight outputs of the multiplexer 40 is selected by the 3-bit select signal of the microfield 14 and outputted to the output line 401, and is output to the multiplexer 401.

The 8 inputs of Lexa 50 are 3 of Microfield 15.
One is selected by the bit select signal and output line 5
Output to 01.

The micro field 11 consists of 3 bits, and its 3 bit output control signal lines 111, 112, and 113 determine the type of micro instruction and control the generation of control signals for other fields.

In particular, the control signal line 111 broadly divides the types of microinstructions into two types: when the state of the control signal line 111 is "0", the mode is a logical operation mode, and when the state is "1", the mode is a test diagnosis mode.

In this invention, second multiplexers 21 to 24 are provided, each receiving the state of the extended test target point.

One of the eight inputs of each of these second multiplexers 21 to 24 is selected depending on the state of the control signal line 121.122.123 of the upper three bits of the microfield 12, and the output lines 211, 221.231
．． 241 are connected to respective separate inputs of multiplexer 29, respectively.

A select signal for the multiplexer 29 is applied from control signal lines 112 and 113 and a control signal line 124 for the least significant bit of the microfield 12.

Input lines 251.261.271. of multiplexer 29.
Reference numeral 281 is a reserve for adding a multiplexer and connecting its output line when the number of extended micro test target points increases.

In this way, by setting the microinstruction, one of the states of the 32 test points of the second multiplexers 21 to 24 is set.
It is possible to select one and output it to the output line 291 of the multiplexer 29.

This selected output is held in a holding circuit.

Therefore, the output line 291 is supplied to the set priority flip-flop 60 as a holding circuit.

In addition, the states of the control signal lines 131 to 133 of the 3-pin I of the micro field 13 are decoded by the decoder 30 enabled in the test diagnosis mode by the output of the control signal line 111, and output from one output line 302. occurs, this causes the flip-flop 60 to switch its input line 2
Read the state of 91 and hold that state.

The output line 601 of this holding circuit is connected to one input line 163 of one of the first multiplexers, for example multiplexer 50, to which the state of the point to be tested before expansion is applied.

Therefore, with one microinstruction, one of the extended test points can be
One state is held at the output of the holding circuit 60, and a subsequent microinstruction selects and outputs the held output from the input terminal 163, thereby changing the state of one of the extended test points to the multiplexer 50. Output line 501
can be obtained.

Depending on the state of this output, the address of the address generation circuit explained in FIG. 1 is changed and the address of the microinstruction is determined.

In addition, the control lines 112 from the microfields 11 to 13
．． 113.121 to 124.131 to 133 can also be used for other control commands different from those described above depending on the microcommand of the microfield 11 that determines the type of microinstruction.

As mentioned above, according to this invention, testing for extended test target points requires two machine cycles, but a logic circuit is inserted in series with the human power of the address generation circuit to select the target points. Therefore, the machine cycle length can be kept to a minimum, and the number of test points can be easily expanded without the need to particularly increase the microinstruction bit width.

[Brief explanation of the drawing]

FIG. 1 is a route map showing a conventional microprogram test device, FIG. 2 is a route map showing its test expansion, and FIG. 3 is a route map showing an example of the microprogram expansion test device according to this invention. In FIG. 3, 10: microinstruction register, 21-
24: a second multiplexer to which the state of the extended test target point is given; 50: a first multiplexer to which the state of the test target point before expansion is given; 60: holding circuit.

Claims (1)

[Claims for Utility Model Registration] A: an address generation circuit; B: a control memory unit accessed by an address signal output from the address generation circuit to read micro instructions; and C: a micro instruction read from the control memory unit. a microinstruction register for storing instructions; D a first multiplexer for selecting one of a plurality of test target points before expansion by the microinstruction stored in the microinstruction register; and E a plurality of expanded microprogram test targets. a second multiplexer that takes the point as input, selects one of the microprogram test target points specified and expanded by the microinstruction stored in the microinstruction register, and outputs its state; a holding circuit that holds the output of the multiplexer under the control of a microinstruction stored in the microinstruction register and supplies the held output to the first multiplexer as one of the points to be tested before expansion; A microprogram expansion test device comprising: means for applying the output of the above to the address generation circuit to change the address applied to the control storage unit.