JPS62290944A - Evaluation system for microprogram - Google Patents

Abstract

PURPOSE:To easily know an unevaluated microprogram by writing previously the parity error data to the parity bit part of a microprogram command and reading out a microprogram containing a parity bit by a service processor after the end of evaluation to decide presence or absence of a parity error. CONSTITUTION:When a microprogram is carried out, a foul parity is written to the parity bit field of the microprogram. A service processor 10 reads out the contents of a microprogram memory circuit 1 via a data signal line 100 after an evaluation program is run. Then it is checked whether the parity bit of the microprogram is correct or not. The microprogram containing a normal parity bit is equal to the one that is not executed yet. While the microprogram containing a foul parity bit is equal to the one that is executed once or more. In such a way, an unevaluated microprogram can be known.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a microprogram evaluation method, and particularly to the evaluation of a microprogram having a parity bit.

(Prior Art) Conventionally, this type of device has been evaluated simply by executing an evaluation program, so evaluation at the machine language level has progressed. However, no progress has been made in evaluating whether or not all routines have been passed at the microprogram level.

(Problems to be Solved by the Invention) The conventional evaluation method described above is performed only by executing an evaluation program at the machine language level, and has a drawback in that there are cases where branching of a microprogram cannot be evaluated.

Therefore, there is a drawback that bugs in microprograms that have never been evaluated may be discovered after the device is shipped.

The purpose of the present invention is to execute a microprogram from a service processor in evaluation mode, read a microprogram command to generate a parity error, write parity error data to the parity bit part of the microprogram command, and then terminate the evaluation. A microprogram evaluation system configured to eliminate the above drawbacks and easily find bugs in the microprogram by later reading the microprogram with the parity bit by a service processor and determining the presence or absence of a parity error. The purpose is to provide a method.

(Measures to Solve Problems) The microprogram evaluation method according to the present invention is configured to include a service processor and a microprogram control device connected to the service processor. It is equipped with a microprogram storage circuit, an address register, a microprogram command register, a flip-flop, a parity error generation circuit, and an AND gate.

The microprogram storage circuit has a word structure with parity pits and is used to store microprograms.

The address register is for storing the address of the microprogram stored in the microphone ejection program storage circuit.

The microprogram command register is for storing the output of the microprogram storage circuit.

The fritsub is used to set the microprogram measurement mode from the service processor.

The parity error generation circuit generates a parity error of the microprogram command by reading the contents of the microprogram storage circuit into the microprogram command register during microprogram evaluation, and stores the parity error data in the parity bit part of the microprogram command. It is for writing.

The AND gate is used to read the contents of the microprogram storage circuit by the service processor after the completion of the microprogram plan and use it to determine the presence or absence of a parity error.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the microprogram evaluation method according to the present invention. In FIG. 1, 1 is a microprogram storage circuit, 2 is an address register, 3 is a microprogram command register,
4 is a flip-flop, 5 is a parity error generation circuit,
6 is an AND game), 10 is a service processor, and 11 is a microprogram control device.

In FIG. 1, a microprogram control device 11 includes a microprogram storage circuit 1, an address register 2 of the microprogram storage circuit 1, a microprogram command register 3 for holding the output of the microprogram storage circuit 1, and a microprogram storage circuit 1. A flip-flop 4 is used to set the evaluation mode from the service processor 10 during program execution, and a parity error generation circuit 5 is used to generate a parity error in the microprogram of the microcommand register 3.
and an AND gate 6 for validating the write pulse of the microprogram storage circuit 1 by the output of the seven lip flop 4 in order to rewrite the parity pit field of the microprogram storage circuit 1.

FIG. 2 is a timing diagram of each signal for explaining the operation of FIG. 1.

Next, the operation will be explained with reference to FIGS. 1 and 2.

The microprogram address a is set in the address register 2 in the third phase of the first machine cycle, and the microprogram storage circuit 1 is set in the first phase of the second machine cycle.
The contents of are read out and the microprogram command A is set in the microprogram command register 3.

In the second phase of the second machine cycle, the parity error data of the microprogram command A stored in the microprogram command register 3 is written to the parity pit field of the microprogram storage circuit 1 through the parity error generation circuit 5. It will be done. The next address b of microprogram command A is set in address register 2 in the third phase of the second machine cycle.

When the microprogram is executed in this manner, invalid parity is written in the parity pit field of the executed microprogram.

After the evaluation program runs, the service processor 10 connects the microprogram storage circuit 1 to the microprogram storage circuit 1 via the data signal line 100.
The contents of the microprogram are read and classified whether the parity pit of the microprogram is correct or not.

A microprogram with a normal parity pit is a microprogram that has never been executed. Conversely, a microprogram with an invalid parity pit is a microprogram that has been executed more than once. By classifying in this way, you can find out which microprograms have not been evaluated.

(Effects of the Invention) As explained above, the present invention executes a microprogram from a service processor in evaluation mode, reads a microprogram command, generates a parity error, and writes a parity error in the parity pit part of the microprogram command. The microprogram is evaluated using the parity pits of the microprogram by writing data in advance and reading the microprogram with parity pits by the service processor after the evaluation is completed to determine whether there is a parity error. Since it is possible to determine whether or not the evaluation has been completed, there is an effect that it is possible to easily know which microprograms have not been evaluated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the microprogram evaluation method according to the present invention. FIG. 2 is a timing diagram showing operation signals in each part of FIG. 1. 1...Microprogram storage circuit 2...Address register 3...Microprogram command register 4...
Flip-flop 5...Parity error generation circuit 6...AND gate 10...Service processor 11...Microprogram control device 100...Signal line

Claims (1)

[Claims] A microprogram evaluation method comprising a service processor and a microprogram control device connected to the service processor, wherein the microprogram control device has a word structure with a parity bit and executes the microprogram. a microprogram storage circuit for storing, an address register for storing the address of the microprogram stored in the microprogram storage circuit, and a microprogram command register for storing the output of the microprogram storage circuit; a flip-flop for setting a microprogram evaluation mode from the service processor; and a flip-flop for generating a parity error in the microprogram command by reading the contents of the microprogram storage circuit into the microprogram command register during evaluation of the microprogram. , a parity error generation circuit for writing the parity error data into the parity bit portion of the microprogram command; and a parity error generating circuit for reading the contents of the microprogram storage circuit by the service processor after the microprogram evaluation is completed to detect the parity error. A microprogram evaluation method comprising an AND gate for use in determining the presence or absence of a microprogram.