JPS5794856A - Control storage device - Google Patents

Control storage device

Info

Publication number
JPS5794856A
JPS5794856A JP55171601A JP17160180A JPS5794856A JP S5794856 A JPS5794856 A JP S5794856A JP 55171601 A JP55171601 A JP 55171601A JP 17160180 A JP17160180 A JP 17160180A JP S5794856 A JPS5794856 A JP S5794856A
Authority
JP
Japan
Prior art keywords
gate
circuit
mode
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55171601A
Other languages
Japanese (ja)
Other versions
JPS6053893B2 (en
Inventor
Hiroyuki Izumisawa
Takeo Kakuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55171601A priority Critical patent/JPS6053893B2/en
Publication of JPS5794856A publication Critical patent/JPS5794856A/en
Publication of JPS6053893B2 publication Critical patent/JPS6053893B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Abstract

PURPOSE:To increase the reliability of a control storage device, by providing a debug mode in addition to a normal operation mode and using a parity field for storage of the trace bit of another purpose. CONSTITUTION:In the case of a debug mode, a mode designation input line 14 is set at ''1''. The passing of signals through gates 7-4, 7-3 and 7-8 of a parity circuit 7 to which ''1'' is supplied is inhibited, and the circuit 7 is set disable at its output side. On the other hand, the signal ''1'' is supplied to the 2nd selection circuit via an AND gate. An line indicating an intial write state is connected to the other input of the AND gate. Thus the output of the AND gate is set at ''1'' in the case of a debug mode and when no initial writing is carried out. Then the 2nd selection circuit selects the output of a trace bit generating circuit as the input of a parity field writing line.
JP55171601A 1980-12-05 1980-12-05 control storage Expired JPS6053893B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55171601A JPS6053893B2 (en) 1980-12-05 1980-12-05 control storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55171601A JPS6053893B2 (en) 1980-12-05 1980-12-05 control storage

Publications (2)

Publication Number Publication Date
JPS5794856A true JPS5794856A (en) 1982-06-12
JPS6053893B2 JPS6053893B2 (en) 1985-11-27

Family

ID=15926184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55171601A Expired JPS6053893B2 (en) 1980-12-05 1980-12-05 control storage

Country Status (1)

Country Link
JP (1) JPS6053893B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62290944A (en) * 1986-06-10 1987-12-17 Nec Corp Evaluation system for microprogram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62290944A (en) * 1986-06-10 1987-12-17 Nec Corp Evaluation system for microprogram

Also Published As

Publication number Publication date
JPS6053893B2 (en) 1985-11-27

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