JPS6053893B2 - control storage - Google Patents

Description

[Detailed description of the invention] The present invention relates to control storage devices.

A microprogram-controlled information processing device successively reads microinstructions from a control storage circuit into a microinstruction read register, decodes the instructions, and performs processing accordingly.

In this case, which memory address in the control storage circuit the microinstruction to be executed next is read out depends on the type of instruction currently being executed, which can be roughly divided into the following three types. Increment type instruction This is the most common instruction, and the next microinstruction to be executed is read from the next memory address where the currently executed increment type instruction is stored.

That is, if a piece of firmware is made up of only microinstructions of this type, when the firmware is executed, each microinstruction will be read out and executed one after another in the order of their memory addresses. ”(B)
Unconditional branch instruction This instruction reads and executes the next microinstruction to be executed from the memory address specified by the currently executing instruction.

For example, if there is a series of instructions of the said increment type to perform a certain process, store this unconditional branch instruction at its last memory address, and in this instruction, the first instruction of the said series of increment type If you specify that a branch should be made to the memory address of , this will result in firmware that repeats the certain process an infinite number of times. (C) Conditional branch instruction This instruction reads the next microinstruction from the memory address specified by this instruction (i.e., branches to that microinstruction) if a certain condition specified by this instruction is satisfied; If not, the next microinstruction is read from the next memory address where this instruction is stored.

That is, this is a type of command that performs the same operation as (B) above when the conditions specified by this command are satisfied, and performs the same operation as (4) when the conditions are not satisfied. Now, if we assume that a certain firmware is made up of only the above types of instructions (4) and (B), when this firmware is executed, the order of the microinstructions that are read out one after another will be determined by this firmware. Because the information is uniquely defined, completely independent of the information to be processed, no complicated problems regarding the program bus occur (such a program can only perform one specific process and has no flexibility at all). (Once you enter this repeating loop, you will never be able to get out of it.) On the other hand, actual firmware contains many (C) type microinstructions, and Depending on the information to be processed, different program buses (buses with different orders for reading microinstructions from the control memory circuit) are selected, and as a result many different and complex processes are automatically performed depending on the information to be processed. be done.

Firmware becomes complicated. Accordingly, the number of microinstructions of type (C) also increases, and therefore the number of possible program buses that such firmware can take becomes enormous. For example, if a new information processing device and the ζ firmware used in it are created,
Conventionally, there has been no known appropriate means for systematically examining and debugging such a huge number of program buses.

Therefore, cases often occur where a bug happens to occur in a program bus that did not pass during the limited test period, and the bus is executed after actual operation, resulting in malfunction and serious failure. SUMMARY OF THE INVENTION It is an object of the present invention to provide a control storage device that solves these problems of conventional devices.

The apparatus of the present invention provides a readable and writable control memory circuit for storing each microinstruction of a microprogram and having a check bit storage position for storing check bits for each microinstruction in a microprogram controlled information processing apparatus. and a micro-instruction read register (for storing the micro-instruction read from the storage circuit and the check bit for the micro-instruction when executing the micro-instruction); an error check circuit that detects an error and generates a check bit of the microinstruction to be stored in the check bit storage location when writing the microinstruction to the control storage circuit; and a microinstruction that is read into the read register. a trace information generation circuit that generates predetermined trace information in response to the decoding execution result of the code; and a trace information generation circuit that activates the operation of the error check circuit in response to the designation of the normal operation mode, and activates the operation of the error check circuit in response to the designation of the debug mode. The operation of the error check circuit is suppressed, and each time a microinstruction is executed, the trace information generated in response to the decoding and execution result of the microinstruction is stored in a check bit storage location for the microinstruction in the control storage circuit. The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The control storage circuit (hereinafter referred to as RAM) 1 consists of a memory that can be read and written at high speed, and each address of this memory consists of an instruction field C and a parity bit field P, as shown in FIG.

The instruction field C is divided into an upper instruction field C1 and a lower instruction field C2, and the parity bit field P is divided into an upper parity bit field P1 that stores parity bits for the upper instruction field C1, and an upper parity bit field P1 that stores parity bits for the upper instruction field C1, and a lower instruction field C2. It is divided into a lower parity bit P2 that stores the parity bit for C2. This P is the check bit storage position. Now, the operation of the present control storage device having this storage circuit 1 in the normal operation mode is as follows. First, when starting up the system, do you read the firmware from external memory (such as a disk) and use it as a preprocessor? In this case, a writing instruction signal is supplied from the outside via the initial writing instruction line 2, and this line is set to ゜゛1.
” becomes.

As a result, the first selection circuit 3 stores the microinstruction transferred from the external memory via the initial write data line 4 into the microinstruction read register 5. This microinstruction read register 5 also has exactly the same fields as shown in FIG. 2, but the microinstructions from the external memory are stored in the instruction field C of this register 5.

This stored microinstruction information is supplied to a parity circuit (error check circuit) 7 via an instruction field output line 6. The parity circuit 7 is detailed in the third
As shown in the figure, it has an upper parity generation circuit 7-1 and a lower parity generation circuit 7-2, and the contents of the upper instruction field of the register 5 are sent to the circuit 7-1, and the contents of the lower instruction field are sent to the circuit 7-1. The circuit 7-2 is supplied with a predetermined parity for each field (for example, if the sum of "1" of the instruction field is an even number, the output is "0", and if the sum is an odd number, the output is゜゜1゛) is outputted as an output through the upper parity write gate 7-3 and the lower parity write gate 7-4, respectively, and the second selection circuit 8 and the parity field write line 9 shown in FIG. The parity data to be written to the fields P1 and P2 of the predecessor ?AMl is supplied through the input line 1. In the normal operation mode, the mode designation input line 14 becomes 0.0.

Since this is supplied to the gates 7-3 and 7-4 via the inverter 7-9, these gates always allow the signal to pass in the normal operating mode. Also,
In this case, "0" on the line 14 supplies "0" to the second selection circuit 8 via the AND gate 15. As a result, the second selection circuit 8 selects the outputs of the gates 7-3 and 7-4 of the parity circuit 7 (second
The AND gate 1 is a control signal for the selection circuit 8.
When the output of the circuit 5 is 6"0", the circuit 8 selects the output of the parity circuit 7 as described above.

In the case of ゜゜1゛, trace bit generation circuit 1 described later
7 side output). As a result, the outputs of gates 7-3 and 7-4 are respectively the fields P of RAMl.
1 and to supply the data to be written to field P2. Now, at the time of system startup, each microinstruction of the firmware read out from the external memory in this way is stored in the instruction field C of the microinstruction read register 5, as described above, and then stored in the instruction field C of the microinstruction read register 5, and then the The data for the parity field is transferred to the RAM via the parity field write line 9.
At the same time, the microinstruction itself is written from the register 5 via the initial write data bus 10 to the instruction field of RAM1 at the same memory address as the parity data.

In this way, each microinstruction of the firmware assigned two parity bits is stored one after another in RAMl. Next, the parity bit thus assigned is used in the normal operation mode as follows.

That is, when the microprogram starts executing,
Each microinstruction of the firmware is read out from R, AMl to the microinstruction read register 5, and then sent to the decoder 11.
The data in the upper instruction field C1 of the microinstruction read into the register 5 is sent to the upper parity generation circuit 7-1, and the data in the lower instruction field is sent to the lower parity generation circuit 7-1. 2, and generate parity bits corresponding to these data at the output sides of the circuits 7-1 and 7-2j. Each parity bit generated in this way is
j is supplied as one input of the upper exclusive OR circuit 7-5 and the lower exclusive OR circuit 7-6, respectively.

On the other hand, the upper and lower parity bits read from the parity field P of RAMl via the parity read line 12 to the parity field of the register 5 are sent via the parity field output line 13 to the upper exclusive logic j. Sum circuit 7-5 and lower exclusive OR circuit 7
-6 are respectively supplied as the other input. If the parity for the upper or lower instruction field generated from the microinstruction data read into the microinstruction read register 5 is different from the value of the parity bit of the corresponding field originally assigned to that microinstruction, the OR The output of the circuit 7-7 becomes "1", which is taken out via the error signal output gate 7-8 as information indicating an operational error.As described above, this control memory device has its control memory circuit ( RAM)
1 has a field for a parity bit, and is also equipped with a parity circuit 7.

In the normal operating mode, this allows parity to be added to each microinstruction when writing it to RAMl, and parity checking of the read microinstruction when reading microinstructions from RAMl. It functions to check whether an error has occurred. However, these functions are similar to those already known. A feature of the device of the present invention is that it has a debug mode in addition to the above-mentioned normal operation mode, and in this mode, the parity field is used to store trace bits for a completely different purpose, unlike the conventional device described above. The point is that it solves the problems that exist. This will be explained in detail below. In the case of debug mode, enter the mode specification '1. 2Mτso:? =÷+2:2i The passage of signals through the gates 7-4, 7-3 and 7-8 of the circuit 7 is prohibited, and the parity circuit 7 is disabled on its output side.

On the other hand, this mode designation signal "゜1" is supplied to the second selection circuit 8 via an AND gate 15.The initial write instruction line 2 is connected to one input of the AND gate 15 via an inverter 16. As a result, when the debug mode is in effect and the initial write is not in progress, the output of the AND gate 15 becomes ゜゜1゛, and the second selection circuit 8 inputs the parity field 3 as an input to the write line 9. The output of the trace bit generation circuit 17 is selected instead of the output of the parity circuit 7. FIG. 4 is a diagram illustrating the invention of the trace bit generation circuit in detail.

4. Data from the P1 field and P2 field of the micro-instruction read register 5 is passed through the parity field output line 13 to the upper read bit input line 17-1 and the lower read bit input line 1 of the trace bit generation circuit 17.
7-2, and upper bit OR circuit 17-
3 and one input of each of the lower bit OR circuits 17-4. The two OR circuits 11-3 and 17-
The other input of 4 is provided via encoder upper bit output line 17-6 and encoder lower bit output line 17-7 of trace encoder 11-5.
On the other hand, the trace encoder 17-5 has an increment type input instruction input 17-8,
Unconditional branch instruction instruction input 17-9, conditional branch instruction instruction input 17-10, and branch condition instruction input 17
It has four inputs of -11. Each of these inputs is connected to an appropriate output of the decoder 11 or an appropriate flip-flop responsive to the execution result, and is connected to an appropriate output of the decoder 11 or an appropriate flip-flop responsive to the execution result, if the microinstruction read into the microinstruction read register 5 is, for example, an increment type instruction. input 17-8, 17-9 if it is an unconditional branch instruction, 17-10 and 17-11 if it is a conditional branch instruction and the branch condition is satisfied, and If it is a conditional branch instruction and the branch condition is not satisfied, only 17-10 becomes "1" and the others become 0. The output signals output to the encoder upper bit output line 17-6 and encoder lower bit output line 17-7 are as shown in Table 1.
For example, increment type command instruction input 17-8
If only the encoder input is “゜1” and all other inputs are “゜0”, “1” is output to both the encoder upper bit output line 17-6 and the encoder lower bit output line 17-7, respectively.
゛ is output.

For example, the conditional branch instruction instruction input 17-10 is 66
r'' and the branch condition instruction input 17-11 is ゜"0", '60'' is sent to the encoder upper bit output line 17-6, ゜゜1゛ is sent to the encoder lower bit output line 17-7, and, for example, if the condition Branch command instruction input 17
-10 is 6゜1゛ and branch condition instruction input 17-1
If 1 is also "1", "1" is output to the encoder upper bit output line 17-6 and 6 DEG 01 is output to the encoder lower bit output line 17-7. The signals outputted in this way are respectively the upper bit OR circuits 17-
3 and the lower bit OR circuit 17-4, the data read out from the parity field of the microinstruction read register 5 is 0R'ed, and then sent to the RA via the second selection circuit 8 and the parity field write line 9.
It is supplied as data for parity and yield of Ml. Now, with the above configuration, the operation in debug mode is as follows.

First, during the initial writing of firmware in the debug mode, the mode designation input line 14 becomes ゜゜1゛, but during the initial writing, the instruction line 2 also becomes ゜゜1゛, which is applied to the AND gate 15 via the inverter 16. Therefore, the output voltage of the AND gate 15 becomes "0", and therefore the second selection circuit 8 inputs the upper parity write gate 7-3 and the lower parity write gate 7- of the parity circuit 7 as inputs to the parity field write line 9.
Select output 4.

However, since "1" from the mode designation input line 14 is supplied to these gates via the inverter 7-9, the signal passage is prohibited.For this reason, in the debug mode, the data is stored in RAM1 by initial writing. The parity field 1 of all microinstructions in the firmware that has been written is set to ゜゜0゛.Now, during the test period, the firmware stored by initial writing is temporarily set to the above-mentioned debug mode. A test run is performed by flowing various test data with the parity check function suppressed.When the firmware is executed in debug mode, it operates as follows.First, a certain microinstruction is read into the microinstruction read register 5. When the instruction is read, it is decoded by the decoder 11, and the instruction is executed according to the decoding result.

Along with this, the decoder 11 and the arithmetic circuit (not shown) determine whether this microinstruction is an increment type instruction, an unconditional branch instruction, a conditional branch instruction, and the branch condition is satisfied, or a conditional branch instruction. and the branch condition is not satisfied, generates an output signal accordingly and supplies it to each input of the trace encoder 17-5 in the trace bit generation circuit 17. . As a result, due to the operation of the trace bit generation circuit 17 described above,
If the current instruction is an increment type instruction, the parity field is
Data such as "゜1゛" and "゜゜1" are respectively written into the upper parity field P1 and the lower parity field P2 of , is written to the parity field of the memory address of RAMl where the microinstruction currently being read out to the register 5 is stored.Similarly, if the current instruction is an unconditional branch instruction, 6'r' and 66 are placed in the upper and lower parity fields of the memory address of RAMl where this microinstruction is stored.
Store r3. That is, the parity field of the memory address of RAM1 where an increment type instruction or an unconditional branch instruction that has been executed at least once or more since the initial write described above is stored does not necessarily contain "゜1". The parity field of the microinstruction in which "1"1" is stored and has never been executed will always contain "60""01.

If the current instruction is a conditional branch instruction and the condition is satisfied and a branch is instructed, the conditional branch instruction is executed by the operation of the circuit including the trace bit generation circuit 17 and the control memory write/read controller. It operates as if 0R "゜1" to the P1 field of the stored memory address (actually, the "゜1゛ is OR circuit 1
7-3, and this is written into the P1 field of the memory address).

Also, if the current instruction is a conditional branch instruction and the condition is not satisfied and no branch is specified, the P2 field of the memory address where the conditional branch instruction is stored is set to ゜゜1 in the same way as described above. The operation is equivalent to 0R of ゛.

As a result of the above operations, if the conditional branch instruction has not been executed at all since the initial write, the P1 and P2 fields of the memory address where the instruction is stored will contain 6゜0゛10゛, and if all If the instruction is executed without satisfying the branch condition, the value is “0゛゜゜1
゛, conversely, if the branch condition is satisfied and the instruction is executed in all cases, then 6゜11゜'', and furthermore, in some cases, the branch condition is not satisfied and the instruction is executed. If the instruction is executed under all (both) conditions, the fields "1" and "6F" are stored, respectively, such that the instruction is executed under all (both) conditions, such that in other cases, the branch condition is satisfied and the instruction is executed. Now, the operation of the trace mode described above is used as follows during the test period.First,
Set to trace mode, perform initial writing of firmware, run test run of this firmware by flowing test data, and then dump all contents of RAMl. As shown in FIG. 5, part of the contents of RAM1 dumped in this way is a memory address in RAM1 where a certain microinstruction was stored (
ADRS), this microinstruction itself, and the contents of the P1 and P2 fields that indicate the execution state of the microinstruction (in the case of trace mode, this field is not a parity field but the upper and lower trace bit fields). becomes). This Pl
, P2 field, it can be seen at a glance that microinstructions that were not executed at all during this test period have 66016'5 stored there.
Also, for conditional branch instructions that are not executed under all conditions (both conditions where the branch condition is satisfied and those where the branch condition is not satisfied), Since either one is stored, it can be seen at a glance as well.

Therefore, when this situation occurs, it is possible that these microinstructions were not executed because the test data used was incomplete, or that there is a problem with the firmware itself. Based on this data, it is very easy to systematically trace and analyze whether the problem is due to a malfunction in the hardware or whether it is due to a malfunction somewhere in the hardware. By doing this, as mentioned at the beginning, a bus containing a certain microinstruction may be overlooked without being tested during the test period, and if there is a bug in this bus, the bus may not be executed after actual operation begins. It is possible to eliminate problems such as those that could cause serious problems. Of course, the use of the trace mode is limited to the test period except in special cases, but in the present invention, the trace bit field in RAM1 using this trace mode utilizes the parity bit field in the normal operation mode. Therefore, the addition of this trace mode does not impose a large burden on equipment.

In the above embodiment, the upper and lower trace bits are used for each microinstruction to distinguish and indicate the operating conditions of the conditional branch instruction. The circuit can be simplified by storing "1" for executed instructions and "0" for instructions that have never been executed.

Alternatively, the number of trace bits for each microinstruction can be further increased, so that, for example, when a three-way branch instruction occurs, each branch corresponding to three branch conditions can be distinguished and displayed using different bits.

As described above, by using the present invention, it is possible to set a trace mode that utilizes the parity bit field in the normal operation mode, thereby making it possible to systematically trace and analyze program buses that are not executed. It is possible to eliminate serious failures caused by overlooked bugs included in the program bus that occur after the program is put into operation.

This has the effect of improving the reliability of the device.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is for explaining the structure of each field of one memory address in the control storage circuit used in the embodiment. , FIG. 3, and FIG. 4 are diagrams showing the parity circuit and trace bit generation circuit used in the above embodiment, and FIG.
Read the figure q
FIG. 3 is a diagram for explaining the contents of a control storage circuit. In the figure, 1... control storage circuit, 2...
...Initial writing instruction line, 3...First selection circuit, 4...Initial write data line, 5...
... Microinstruction read register, 7 ... Parity circuit, 8 ... Second selection circuit, 6, 9, 1
2, 13, 14, 17-1, 17-2, 17-6, 17
-7...Line, 10...Initial write data bus, 11...Decoder, 15...
・AND gate, 16...Inverter, 17・
...Trace bit generation circuit, 7-1...
Upper parity generation circuit, 7-2... Lower parity generation circuit, 7-3... Upper parity write gate, 7-4... Lower parity write gate,
7-5... Upper exclusive OR circuit, 7-6...
...Lower exclusive OR circuit, 7-7...OR circuit, 7-8...Error signal output gate, 7
-9... Inverter, 17-3... Upper bit OR circuit, 17-4... Lower bit OR circuit, 17-5... Trace encoder.

Claims (1)

[Claims] 1 In a microprogram-controlled information processing device,
a readable and writable control memory circuit having check bit storage locations for storing each microinstruction of a microprogram and check bits for each of the microinstructions; a microinstruction read register that stores the microinstruction and the check bit for the microinstruction; and a microinstruction read register that stores the microinstruction and the check bit for the microinstruction; an error check circuit that generates a check bit for the microinstruction to be stored in the check bit storage location; and trace information that generates predetermined trace information in response to the result of decoding and executing the microinstruction read into the read register. a generation circuit, which activates the operation of the error check circuit in response to the designation of the normal operation mode, inhibits the operation of the error check circuit in response to the designation of the debug mode, and activates the operation of the error check circuit in response to the designation of the normal operation mode, and suppresses the operation of the error check circuit in response to the designation of the debug mode; A control storage device comprising control means for controlling the trace information generated in response to a decoding execution result to be stored in a check bit storage location for the microinstruction in the control storage circuit.