JPS5829056A - Control storage device - Google Patents

Abstract

PURPOSE:To easily perform the trace of cause for a failure, by the constitution that a trace information storage circuit possible for write and readout is provided and a signal representing the state of execution of each microinstruction is outputted. CONSTITUTION:When an address is applied to a control storage circuit 2, a microinstruction is read out and stored in a microinstruction readout register 7. The microinstruction stored in this register 7 is interpreted at a decoder 8 for execution. The output of the decoder 8 is inputted to an address control circuit 10 and the output of the circuit 10 is applied to an address line 1 and stored in an address register 9. On the other hand, the write is made in a trace information storage circuit 5 for the output to the line 1. The circuit 5 becomes in readout state by applying ''1'' from a readout mode signal line 13 and the data of all addresses is read out and inputted to an output device 11 via an AND gate 3. Through this operation, the state of execution of microinstruction of the respective microprogram can be known.

Description

[Detailed description of the invention] The present invention relates to a control storage device in a physical equipment.

A microprogram-controlled information processing device operates by reading out microinstructions one after another from a control storage circuit, decoding them, and performing processing accordingly.

The address in the control storage circuit from which the microinstruction to be executed next in this operation is read depends on the type of instruction currently being executed.

For example, if the currently executing instruction is an increment type instruction, the microinstruction to be executed next is successively issued from the next address where this increment type instruction is stored.

In addition, in the case of an unconditional branch instruction, the instruction that is currently being executed continues to be executed from the address specified, and in the case of a conditional branch instruction, the instruction (if a certain condition is satisfied, The next microinstruction is read from the address, and if it is not satisfied, the next microinstruction is read from the next address where this command is stored.

Now, in such a processing device, assuming that a certain firmware is made up only of the above-mentioned increment type instructions and unconditional branch instructions, when this firmware is executed, the first order of the microinstructions issued one after another is is uniquely determined completely independent of the information processed by this firmware, so no complicated problems regarding program paths occur.

In other words, since it can only perform one fixed process, there is no flexibility at all. And once you enter this repeating loop, you can never get out of this loop.

In contrast, real firmware contains many conditional branch instructions that select different program paths (paths that read microinstructions from control storage in different orders) depending on the information being processed. As a result, many different and complex processes are automatically performed depending on the information to be processed. As actual firmware becomes more complex, the number of conditional branch instructions increases accordingly, and the number of possible program paths that such firmware can take also becomes enormous.

However, when a new information processing device and the firmware used in it are newly created, there is no known appropriate means to systematically examine and debug such a huge number of program paths. . As a result, there was a bug in the program path that did not pass during the limited test period, and this path was executed after actual operation started, causing malfunctions and leading to serious failures. .

An object of the present invention is to easily identify the cause of an abnormality by knowing the execution status of each microinstruction.
An object of the present invention is to provide a control storage device capable of preventing serious failures caused by, for example, overlooking a buggy program path during a test period.

In order to achieve the above object, the control memory device according to the present invention uses a control memory circuit exclusively for start-up, in which each micro-instruction is stored in each memory register to indicate that each micro-instruction is successively issued from each address of the control memory circuit. Trace information 6 that can be stored in synchronization with the output operation
It is provided with a self-storage circuit and means for outputting the contents of the trace information storage circuit, and is configured to output a signal indicating the execution state of each microinstruction of the microprogram.

According to the above configuration, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, reference numeral 2 denotes a control memory circuit dedicated to continuous output that stores each microinstruction of the microprogram, 7 a microinstruction continuous output register that stores the output of the control memory circuit 2, and 8
9 is a decoder that decodes the microinstruction stored in the microinstruction reading register 7; 9 is an address register that stores the current address of the microinstruction successively issued from the control storage circuit 2; and IO is the next readout from the control storage path 2. 5 is a control circuit that determines the correct address based on part of the microinstruction stored in the microinstruction read register 7, the output of the decoder 8, and the current address stored in the address register 9; A trace information storage circuit that can be read and written at the same address in synchronization with the output of the memory circuit 2; 3 is a trace information storage circuit for validating the output data only when reading from the trace 11v information storage circuit 5; And gate, 1゜I#i and gate 3
Output device +1.71 for outputting read data validated by outside the device, trace information storage circuit 5K“O
This shows a selection circuit for selecting which of I and al- is to be stored.

Each micro-instruction has a 32-bit structure, the 'do control memory circuit 2 has 32 bits x 256 bits, and the trace information memory circuit 5 has a pupil size of 32 bits x 256 bits.

Also, the address consists of 8 bits.

When an address is supplied to the control storage circuit 2 via the address line 1 and output is performed, the microinstruction at that address is read out and stored in the microinstruction output register 7.

The microinstruction stored in the microinstruction read register 7 is decoded and executed by the decoder 8. The output of the decoder 8 includes a signal how to determine the next address to be executed. This is inputted to the address control circuit 10, which outputs the address from the address register 9 plus 1 based on other condition signals (not shown), or outputs the address from the address register 9 plus one, or selects one of the microinstructions stored in the microinstruction successive register 7. Determines whether to output the specified address.

The output of the address control circuit 10 is supplied to the address line 1 and simultaneously stored in the address register 9.

On the other hand, the trace information storage circuit 5 has been initialized in advance, and 10m has been written to all addresses. As the signal changes from a06 to 111, the address becomes 1+
1 and outputs up to FF, addresses the trace information storage circuit 5 via the address line 1, and sets the read mode signal line 13 to 10'' to put the trace information storage circuit 5 in the write state, and selects the selection circuit 4. This is realized by setting the selection signal 12 to Mol and supplying the write data 106 to the trace information storage circuit 5. Note that this operation ends when the most significant bit is generated when the address is incremented by 1 in the address control circuit 10. Control @jδ by carry.

When the micro command is executed normally, the address increment mode signal line 15 is "0", the selection 1d number 12 is 11', and the read mode signal line 1 is "0".
3 is supplied with "11", and in synchronization with the reading from the control storage circuit 2, the trace information storage circuit 5 sets the mIM selected by the selection circuit 4 to 1 bit designated by the address supplied from the address line 1. is written.

Thereafter, 111 is written in the trace information self-memory circuit 5 at the address where the microinstruction is stored at the beginning of the execution of the microinstruction, indicating that the microinstruction has been executed.

At E-xM, h during microprogram processing, address increment/tomo-toy number lines 15 to 111
By supplying A? As mentioned above, the trace information storage circuit 5 is supplied with addresses from 00 to FF, and the trace information storage circuit 5 enters the read state by supplying the read mode signal line 111 from the read mode signal line 13.1. Data of all addresses is read and AND gate 3
makes the read signal 6 valid and outputs it to the output device 11 through 14 lines.

This operation makes it possible to know the execution status of each microinstruction in each microprogram.

FIG. 2 is a diagram showing the correspondence between the control storage circuit 2 and the trace information storage circuit 5, focusing on the addresses of each microinstruction.

In this example, the addresses are from 00 to 06, and the rest are omitted. Trace Information 11 In the past, when data like this example was output from the dependent circuit 5, it was found that only instructions 3 and 4 were not executed.

This is explained by the functional flow of each microinstruction, for example, as shown in FIG.

In this case, instruction 2 is a conditional branch instruction and branches to instruction 3 or instruction 5 depending on a certain condition, but in this example, it is not possible to know that the microprogram was not processed under the conditions that would cause the branch to instruction 3. can.

Therefore, if such a situation occurs, it is likely that these micro-branches were not executed because the test data used was incomplete, or that there is a problem with the firmware itself. Based on this data, it is easy to systematically track and analyze whether the problem is caused by a malfunction in some part of the hardware.

Due to the above configuration, a path containing a certain microinstruction as mentioned earlier may be overlooked without being tested during the test period, and furthermore, there may be a bug in this path and this path may be executed after actual operation begins. It is possible to eliminate problems such as those that occur when the system is used and cause serious problems.

As explained and explained in detail above, the present invention enables systematic tracking and analysis of program paths that are not executed, and as a result, bugs contained in overlooked program paths that occur after they are put into operation can be eliminated. It is possible to eliminate serious problems caused by this.

Therefore, the reliability of the device can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the control storage circuit device according to the present invention, FIG. 2 is an explanatory diagram of an example of output data of the trace information storage circuit in FIG. 1, and FIG. FIG. 2 is a flowchart of each instruction; FIG. 1...Address line 2...Continuation exclusive control storage circuit 3...AND gate 4...Selection circuit 5...Trace information storage circuit 6...Trace information output line 7...Microinstruction Read register 8,...decoder 9...address register 1
0... Address control circuit 11... Output device "d 12... Retired partner number 13
...Reading mode signal line 14...Output line 15...Hair address increment mode signal line Patent applicant Nippon Kuki Co., Ltd.

Claims (1)

[Claims] In a control memory device using a read-only control memory circuit, a trace information memory circuit capable of continuous writing that stores information that each microinstruction is successively issued from each address of the control memory circuit in synchronization with each read operation. and means for outputting the contents of the trace information storage circuit, and is configured to output a signal indicating the execution state of each microinstruction of the microprogram.