JPH02110637A - Program debugging supporting device - Google Patents

Abstract

PURPOSE:To recognize the contents of a program immediately after executing the program and to improve debugging efficiency by previously storing next instructions accordant with the existence of a branch in addresses corresponding to a conditional branch instruction and detecting, recording, and displaying the addresses in debugging time. CONSTITUTION:The address of one next instruction to be executed when the conditional branch instruction branches and the address of the other next instruction to be executed when the conditional branch instruction does not branch are previously written to the addresses of a memory 10 of a recording part 6 corresponding to the addresses on the program of the conditional branch instruction. When the program to be debugged is to be executed, branch information read out from the memory 10 is compared with an instruction fetch address signal to be executed next by an instruction fetch address signal in comparators 11 and 12. Further, it is decided whether the conditional branch instruction branches or not, the execution record is stored in memories 15 and 16 according to the decided result, and the record is displayed on a data display part. Thus, the contents of the program can be recognized immediately after the program is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program debugging support device, and more particularly to a program debugging support device that supports software development of a microprocessor by supporting program debugging by recording program execution. Regarding.

Conventionally, in this type of program debugging support device, address information when a microprocessor fetches an instruction and the fetched instruction code are recorded in the order in which they occur.
The recorded contents were displayed after the microprocessor executed.

In debugging a program, it is important to know which steps have not yet been executed or whether a conditional branch instruction included in the program has branched.

Conventional program debugging support devices like this record the instruction codes and addresses that the microprocessor executes in the order in which they occur, so in order to know whether all the addresses and branch instructions that occurred were actually executed, The recorded contents must be checked by the operator himself, or the recorded contents must be edited by another device such as a computer, and the contents cannot be known immediately after recording the execution of the program. There are drawbacks.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to know the contents immediately after recording the execution of a program, and debug the program efficiently. The purpose is to provide a program debugging support device that can.

A program debugging support device according to the present invention is a program debugging support device that records the execution of a program including a conditional branch instruction when the program is debugged, and the program debugging support device records the execution of a program including a conditional branch instruction. The addresses include a first address indicating the address of the next instruction to be executed when the conditional branch instruction branches, and a second address indicating the address of the next instruction to be executed when the conditional branch instruction does not branch. a storage means for pre-storing a second address; and a storage means for storing the first address in advance from the corresponding address of the storage means according to the address supplied when debugging the program.
and a detection means for detecting whether or not the conditional branch instruction has branched based on the second address; and a recording means for recording execution information of the conditional branch instruction according to a detection result of the detection means; The present invention is characterized by further comprising a display means for displaying the execution information recorded in the recording means.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. , a data display section 5, and a recording section 6 are connected, and the control section 1 controls these sections via a bus signal line 100.

That is, address information and data sent from the microprocessor in the control section 1 and data input to the microprocessor are transferred via the bus signal line 100 to control each section.

A control program is stored in the program memory section 2, and when the microprocessor in the control section 1 reads the control program from the program memory section 2 via the bus signal line 100, the control program is executed. Ru.

The operation panel 3 is provided with a plurality of switches for instructing recording operations and control operations by the microprocessor in the control section 1. The instruction information input by these switches is transferred to the microprocessor via the bus signal line 100. Further, a recording operation instruction is sent to the recording unit 6 as a recording control signal via a recording control signal line 102.The four-data input unit 4 externally receives branch address information regarding the debugged program that is the target of debugging support. input from an input device such as a floppy disk device. The branch address information input by the data input section 4 is transferred to the microprocessor in the control section 1 via the bus signal line 100.

The data display section 5 displays data transferred from the microprocessor in the control section 1 via the bus signal line 100. That is, by the microprocessor reading the data recorded in the recording section 6 via the bus signal line 100, the data can be displayed on the data display section 5.

The recording unit 6 records data to be recorded that is input from the outside via a digital signal t1ioi, such as an instruction fetch address signal when the program to be debugged is executed. When recording this instruction fetch address signal, the branch address information transferred from the data input section 4 to the microprocessor in the control section 1 is referred to.

FIG. 2 is a block diagram showing the configuration of the recording section 6 of FIG. 1. In FIG.
7 via the address signal line 112 to the address specified by the data signal line 113.
Data on the bus signal line 100 input via the address is written, or data is read from the address.

Here, each address of the memory 10 has a field a.

Data divided into three parts b and c are stored, and the data of field a is sent to the comparator 11 via the signal line 114.
．． 12, and the data in field b is sent to the signal line 11.
The field C data is sent to the comparator 11 via the signal line 116.

When the data in field a indicates that the data in fields b and c are valid, the comparator 11 receives an external instruction fetch address signal input via the digital signal input line 101 and the signal line. 115, and when the comparison result indicates a match, a match signal is sent to the memory control circuit 1 via a match signal line 117.
Output to 3.

When the data in field a indicates that the data in fields b and c are valid, the comparator 12 receives an external instruction fetch address signal input via the digital signal input line 101 and the signal line. 116, and when the comparison result indicates a match, a match signal is sent to the memory control circuit 14 via a match signal line 118.
Output to.

When the recording control signal inputted via the recording control signal line 102 indicates that the recording operation is disabled, the memory control circuit 13
The read/write operation for the memory 15 is controlled in accordance with the read/write control signal on the bus signal line 100 input via the read/write control signal line 119, that is, the read/write control signal from the microprocessor in the control unit 1.

Therefore, when the microprocessor instructs the memory 15 to read, the memory control circuit 13 instructs the memory 15 to perform a read operation via the control signal line 121.

When the microprocessor instructs the memory 15 to write, the memory control circuit 13 sends an initial value to the memory 15 via the write data line 120 and also sends an initial value to the memory 15 via the control signal line 121. Instructs write operation.

Furthermore, when the recording control signal inputted through the recording control signal line 102 indicates that recording is possible, the memory control circuit 13 responds to the coincidence signal from the comparator 11 inputted through the coincidence signal line 117. read/write operations to the memory 15 are controlled.

That is, when the comparator 11 detects a match between the instruction fetch address signal from the outside and the data in field b from the memory 10, the memory control circuit 13 sends a value different from the initial value to the memory 15 via the write data line 120. In addition to sending out the value, it also instructs the memory 15 to perform a write operation via the control signal a121.

When comparator 11 does not detect a match between the external instruction fetch address signal and the data in field b from memory 10, memory control circuit 13 does not instruct memory 15 to perform read or write operations.

When the recording control signal inputted through the recording control signal line 102 indicates that the recording operation is disabled, the memory control circuit 14 performs the following operations.
The read/write operation for the memory 16 is controlled in accordance with the read/write control signal on the bus signal line 100 inputted via the read/write control signal line 119, that is, the read/write control signal from the microprocessor in the control unit 1.

Therefore, when the microprocessor instructs the memory 16 to read, the memory control circuit 14 instructs the memory 16 to read through the control signal line 123, and the microprocessor instructs the memory 16 to write. , the memory control circuit 14 sends the initial value to the memory 16 via the write data line 122 and also sends the initial value to the memory 16 via the control signal line 123.
Instructs write operation to.

Furthermore, when the recording control signal inputted through the recording control signal line 102 indicates that recording is possible, the memory control circuit 14 responds to the coincidence signal from the comparator 12 inputted through the coincidence signal line 118. read/write operations to the memory 16 are controlled.

That is, when the comparator 12 detects a match between the instruction fetch address signal from the outside and the data in field C from the memory 10, the memory control circuit 14 sends a value different from the initial value to the memory 16 via the write data line 122. It sends the value and also instructs the memory 16 to perform a write operation via the control signal line 123.

When comparator 12 does not detect a match between the external instruction fetch address signal and the data in field C from memory 10, memory control circuit 14 does not instruct memory 16 to perform read or write operations.

The memory 15.16 performs a write operation or a read operation in response to an instruction from the memory control circuit 13.14 at an address specified by address information from the selector circuit 17 input via the address signal line 112. The data read from the data signal line 124
The signal is sent onto the bus signal line 100 via the bus signal line 100.

When the recording control signal inputted via the recording control signal line 102 indicates that the recording operation is disabled, the selector circuit 17 selects the bus signal line 10 inputted via the address signal line 111.
0, that is, the address information from the microprocessor in the control section 1, is selected and sent onto the address signal line 112.

Further, when the recording control signal inputted through the recording control signal line 102 indicates that recording is possible, the command fetch address signal from the outside held in the latch 18 is selected and sent onto the address signal line 112. do.

The latch 18 receives an external instruction fetch address signal input via the digital signal input line 101,
This instruction fetch address signal is temporarily held.

FIG. 3 is a diagram showing data stored in advance in the memory 10 of FIG. 2. In FIG. The data in field C is the address value of the next instruction to be executed if the conditional branch instruction does not branch, and the data in field C is the address value of the next instruction to be executed if the conditional branch instruction branches.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

In a program debugging method, it is common practice to increase the degree of evaluation by using a wide variety and large amount of test data to be used for program debugging.

However, with this method, it is not possible to easily determine whether each part of the program has been debugged.

Programs are generally created using a large number of various conditional branch instructions, and these conditional branch instructions check the data and processing results provided from outside when the program is executed. In debugging a program, it is necessary to confirm program execution both when these conditional branch instructions branch and when they do not branch.

To determine whether a conditional branch instruction has branched, trace the instruction fetch address during program execution, and compare the program address of the conditional branch instruction and the two instructions to be executed next to this instruction, that is, the next instruction if no branch is taken. This can be determined by checking the address of the instruction that will be executed next and the address of the instruction that will be executed next when branching.

Therefore, for each conditional branch instruction related to the debugged program to be debugged, the address value on the program, the address value of the next instruction to be executed if no branch is taken, and the next instruction to be executed if a branch is taken. The address values of the instructions are prepared in advance, and these address values are inputted from the data input section 4.

The microprocessor in the control unit 1 uses these address values transferred from the data input unit 4 to determine the address value of the next instruction to be executed if no branch is taken, and the address of the next instruction to be executed if the branch is made. The values and a valid flag indicating that these address values are valid are compiled into one word of data (hereinafter referred to as branch information) (see FIG. 3).

The microprocessor then writes this branch information onto memory 10 via bus signal line 100.

At this time, the same address as the program address of the conditional branch instruction corresponding to this branch information is set as the write address of the memory 10.

The microprocessor compiles each branch information from the address information of all the conditional branch instructions and writes it into the memory 10, and then instructs the memory control circuits 13.14 to write to the memory 15.16, and writes the information to the memory 15.16.
4. When performing actual debugging, the instruction fetch address signal of a device (not shown) that executes the program to be debugged is input to the digital signal input line 10.
1 and operates a switch on the operation panel 3 to output a recording control signal enabling recording operation to the recording section 6 via the recording control signal line 102.

From now on, each time each instruction of the program to be debugged is fetched, the instruction fetch address signal is input to the latch 18 via the digital signal input line 101 and held, and the instruction fetch address held in the latch 18 is The contents of the memory 10 using the signal as an address are read out.

When the fetched instruction is a conditional branch instruction, branch information is read from memory 10.

At this time, since the instruction fetch address signal of the instruction to be executed next to the conditional branch instruction is input to the recording unit 6 via the digital signal input line 101, this instruction fetch address signal and the instruction fetch address signal read from the memory 10 A comparator 1112 compares the branch information with the branch information.

When the comparator 11 detects a match, that is, when there is no branch, the memory control circuit 13 instructs the memory 15 to perform a write operation, and the memory 15 is written.

When a match is detected in the comparator 12, that is, when a branch is detected, the memory control circuit 14 controls the memory 16.
A write operation is instructed to the memory 16, and writing to the memory 16 is performed.

Therefore, an execution record when the conditional branch instruction did not branch remains in the memory 15, and an execution record when the conditional branch instruction branched remains in the memory 16.

To display the contents of the memories 15, 16, the contents of the memories 15, 16 are read by the microprocessor in the control section 1, and the contents are sent from the microprocessor to the data display section 5 for display.

Thereby, when the debugging of the program to be debugged is completed, the execution record of the conditional branch instruction is displayed on the data display section 5, and the progress of debugging can be immediately determined.

In this way, the address of the next instruction to be executed when the conditional branch instruction branches and the conditional branch instruction Branch information consisting of the address of the next instruction to be executed when the branch is not executed is written in advance, and the branch information is read from the memory 10 by the instruction fetch address signal when the program to be debugged is executed. , and the instruction fetch address signal to be executed next. Comparators 11.12
to determine whether the conditional branch instruction has branched or not, record the execution record in the memory 15.16 according to the determination result, and display the contents recorded in the memory 15.16 in the data display section. 5, the contents of the program can be immediately known immediately after the execution of the program is recorded. This allows programs to be debugged efficiently.

As explained above, according to the present invention, the address of the next instruction to be executed when branching in the conditional branch instruction is set to the corresponding address corresponding to the address of the conditional branch instruction included in the program. A first address indicating the conditional branch instruction and a second address indicating the address of the next instruction to be executed when the conditional branch instruction does not branch are stored in advance. The first file stored in advance
and a second address, detects whether or not the conditional branch instruction branches based on the first and second addresses, and records execution information of the conditional branch instruction according to the detection result. By displaying the execution information recorded in the recording means on the display means, the contents of the program can be immediately known immediately after recording the execution of the program, and the program can be debugged efficiently. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the recording section in FIG. 1, and FIG. 3 shows the data stored in advance in the memory in FIG. FIG. Explanation of symbols of main parts 1... Control section 4... Data input section 5... Data display section 6... Recording section 10.15.16. ...Memory 11.12...Comparator 13.14...Memory control circuit 17...
・Selector circuit 18...Latch

Claims (1)

[Claims] (1) A program debugging support device that records the execution of a program that includes a conditional branch instruction when debugging the program, wherein the program debugging support device records the execution of the program when the program includes a conditional branch instruction, and the conditional branch instruction branches to a corresponding address corresponding to the address of the conditional branch instruction. storage means for storing in advance a first address indicating the address of the next instruction to be executed when the conditional branch instruction is executed; and a second address indicating the address of the next instruction to be executed when the conditional branch instruction does not branch; , detection means for detecting whether or not the conditional branch instruction branches based on the first and second addresses read from the corresponding address of the storage means according to the address supplied when debugging the program; Program debugging characterized by comprising: a recording means for recording execution information of the conditional branch instruction according to a detection result of the detection means; and a display means for displaying the execution information recorded in the recording means. Support equipment.