JPS6375848A - Debugging log recording system - Google Patents

Abstract

PURPOSE:To facilitate debugging work by providing a debugging log storage memory which has an area corresponding to the address by which a processor accesses a storage device and writing access information in this memory in accordance with access to the storage device. CONSTITUTION:When a processor 21 accesses a storage device 22, this access address is stored in a buffer register 12 through an address bus (a). The upper digit part of the access address is compared with the value preliminarily stored in an upper digit register 6 by a comparing part 7, and a coincidence detection signal is outputted from the comparing part 7 if they coincide with each other. The signal indicating the access state is sent from the processor 21 through an access signal line (d). A trace signal is sent from a trace register 9. A trace control part 10 writes access information in a debugging log storage part 42 when the coincidence detection signal, the access signal, and the trace signal are made active.

Description

[Detailed Description of the Invention] [Summary] A debug history recording method for a data processing device having a processor that controls data processing operations based on a program, which records which part of a storage device in the data processing device has been accessed by the processor. In order to easily know, a memory for debug history storage having an area corresponding to the address when accessing the storage device is provided, and access information is written in the memory in response to access to the storage device. This makes it easier to debug programs stored in the storage device.

[Industrial application field]

The present invention relates to a debug history recording method for a data processing device having a processor that controls data processing operations based on software.

Generally, in devices that control data processing operations based on software, a debug device is important for debugging the software.

In addition, in recent years, in order to respond to the increase in the amount of software and the shortening of software development period, there has been a demand for a program tracing method that has more functions and is easier to debug.

Note that the trace method refers to a method in which actual progress steps are sequentially traced and stored in a memory or the like in order to investigate the behavior of various programs.

[Conventional technology]

FIG. 4 shows a block diagram illustrating a conventional example.

The block diagram shown in FIG. 4 includes a data processing device 20 that includes a processor 21 and a storage device 22, and a debug device 30 that traces the processing steps of software used during data processing in the data processing device 20. There is.

Note that the debug device 30 of this example controls writing of trace information (execution address, instruction code, data address, etc.) to the data storage section 41 in the debug storage device 4 when the processor 21 accesses the storage device 22. a trace control unit 2; a pointer 3 that specifies a write position to the data storage unit 41 in the debugging storage device 4, such as an execution address when the storage device 22 is accessed; and a storage device accessed by execution of an instruction by the processor 21. The debugging storage device 4 is configured to include a debugging storage device 4 for writing and holding trace information of 22 pieces.

In the conventional software tracing method as shown in FIG. 4, when the processor 21 executes an instruction, the address location of the debug storage device 4 specified by the pointer 3 is accessed by the execution address and the instruction code at that time. , data address, etc. is written by the trace control unit 2.

Next, the pointer 3 is incremented, and the trace information is sequentially written into the debugging storage device 4 to the specified position.

[Problem that the invention seeks to solve]

In the software tracing method described above, it is difficult to detect which instructions on the program stored in the storage device 22 have been executed and which parts of the data on the storage device 22 have been read/written. , it is necessary to sequentially check the trace information stored on the debugging storage device 4 and the program list.

Therefore, there is a problem in that it takes a lot of time to debug the software.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG. 1 is composed of the data processing device 20 described in FIG. 4 and a debug device 30' described below.

The debug device 30' of the present invention includes a debug fat layer storage means (debug history storage section) 42 having a storage area corresponding to the address of the storage device 22 in the data processing device 20, and a high-order digit part of the address of the storage device 22. The upper digit storage means (upper digit register) 6 to be stored is compared with the upper digit part of the address of the storage device 22 sent from the processor 21 and the contents stored in the upper digit storage means (upper digit register) 6. , a comparison unit 7 that sends out a matching signal when they match.
Then, data is set according to a predetermined command from the processor 21.

Trace storage means (trace register) 9 to be reset
When the match signal from the comparison unit 7, the control signal (d) from the processor 21 is turned on, and the predetermined data is set in the trace storage means (trace register) 9, the debug history storage means (debug history storage section) 42 It is configured to include a trace control unit 10 and the like that control tracing to.

[Effect]

In order to easily know which part of the storage device 22 in the data processing device 20 has been accessed by the processor 21.

A debug history storage means (debug history storage section) 42 having an area corresponding to an address when accessing the storage device 22 is provided in the debug storage device 4, and the debug history storage means (debug history storage section) 42 stores information. Device 2
By writing access information (information as to whether the access is a read instruction or a write instruction) in response to access No. 2, debugging of the program stored in the storage device 22 becomes easier.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a diagram explaining access information in an embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

FIG. 2 is a diagram showing an embodiment of the debug device 30' according to the present invention, and its configuration includes the functional blocks 4, 6.7, 9, 10.42 explained in FIG. a buffer register 12 that temporarily holds the data, an address register 13 that specifies the address of the debug history storage section 42, and a debug control section 1 that controls the entire debug device 30'.
4, and multiplexers (hereinafter referred to as "chip") 15 to 17 that select one from a plurality of inputs.

Note that (a) indicates an address bus, (b) a data bus, (C) a trace signal line, and (d) an access signal line.

When the processor 21 accesses the storage device 22, the access address at that time is stored in the buffer register 12 via the address bus (a).

Of this access address, the high-order digit part is compared with the value stored in the high-order register 6 in advance in the comparison unit 7,
If they match, a match signal is sent out from the comparing section 7.

Furthermore, the processor 21 sends out a signal indicating the access state (read state or write state) via the access signal line (dl).

Also, the trace data is connected to the trace signal line (C), MPX
When set to trace register 9 via I6, a trace signal is sent out from trace register 9.

The trace control unit 10 controls the above-mentioned three signals (coincidence signal,
When the access signal (access signal, trace signal) becomes active, the 2-bit access information shown in FIG. 3 (“00” is not accessed, “01” is "01" indicates a write (read), and "01" indicates a write (write).

Note that the address entry to the upper digit register 6 is performed in advance by the debug control unit 14. Also, the debug control unit 14 sets the trace data to the trace register 9.
However, if you want to trace only the access operations of a part of the program, set trace register 9 during the program.
This is achieved by incorporating a reset command.

Next, the reset and read operations of the debug history storage section 42 will be explained.

As a reset operation, the debug control unit 14 sets an address in the address register 13 via the data bus (bl) and writes "OO". By repeating this operation, all addresses are reset.

Similarly, the read operation is executed by the debug control section 14 specifying an arbitrary address in the debug history storage section 42 using the address register 13 and reading out the access information.

Since the access state of the processor 21 is recorded as described above, it is possible to see at a glance which instructions have been executed in the program space on the storage device 22, and which data have been read/written in the data space. becomes.

In addition, since the trace operation is performed only when the upper digit of the access address matches the setting value set in the upper digit register 6, the debug history storage section 42 can be made as large as necessary for tracing. Capacity can be reduced.

Furthermore, by incorporating the set and reset instructions for the trace register 9 into the program, it becomes possible to trace only the access operations of a part of the program.

〔Effect of the invention〕

According to the present invention as described above, there is an effect that software debugging work can be executed more easily and in a shorter time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining access information in an embodiment of the present invention, and FIG. 4 is a conventional block diagram. A block diagram illustrating an example is shown, respectively. In the figure, 2.10 is a trace control unit, 3 is a pointer, 4 is a debugging storage device, 6 is a high-order register, 7 is a comparison unit, 9 is a trace register, 13 is an address register, 14 is a tech control unit, 15 ~17 is l'lPX. 20 is a data processing device, 21 is a processor, 22 is a storage device, 30.30' is a debug device, 41
42 indicates a data storage section, and 42 indicates a debug history storage section.

Claims (1)

[Scope of Claims] Connected to a data processing device (20) having a processor (21) and a storage device (22) storing programs and the like used by the processor (21); A debugging device (30') that traces the software in the storage device (22) that is accessed by the processor (21) based on an instruction, stores information in the debugging device (30') that corresponds to the address of the storage device (22). a debug history storage means (42) having a storage area for storing data; a high-order digit storage means (6) for storing the high-order digit part of the address of the storage device (22); , and a trace storage means (9) for resetting, wherein predetermined data is set in the trace storage means (9) and the upper address of the address of the storage device (22) accessed by the processor (21). writing access information indicating the access state of the storage device (22) to the debug history storage means (42) when the digit portion matches data stored in advance in the upper digit storage means (6); Features a debug history recording method.