JPH0221340A - Debugging system for firmware - Google Patents

Abstract

PURPOSE:To easily and effectively debug the firmware by performing the collation between the data bus signal read out of a register part and the data bus signal produced by a control part. CONSTITUTION:A control part 1 latches the data bus signal produced based on a program stored in a program memory 2 via a latch part 31. This latched data is stored directly into a register part 34 and can also be read immediately out of the part 1. Then the data bus signal produced by the part 1 is directly read out of the part 34 for collation. Thus the firmware can be debugged easily and with higher accuracy.

Description

[Detailed Description of the Invention] [Summary] Regarding a firmware debugging method that detects the correctness of a program and hardware settings through a control unit that controls various operations based on a microprogrammed program. The purpose is to provide a firmware debugging method that allows data to be directly read by the control unit and debugged efficiently and easily. A latch section that outputs the ticked data as an address, a memory section that takes in the latch data output from the latch section as an address and writes the data included in the signal on the data bus, and a control section between the memory section and the control section. It includes a bidirectional buffer section that exchanges data via a data bus, and a register section that stores latch data output from the latch section. It is configured to compare the data bus signal issued from the 'l11 section.

[Industrial application field]

The present invention relates to a firmware debugging method that detects whether a program and hardware settings are correct through a control unit that controls various operations based on a microprogrammed program.

Debugging a programmed program is usually done by
This is often done using prototype equipment that is equivalent to what is actually used in the field.

Particularly, when there are many opportunities to control various devices by a control unit using a program as in recent years, it is desired that program debugging be made more efficient.

[Conventional technology]

FIG. 3 is a block diagram illustrating a conventional example, and FIG. 4 is a diagram illustrating the relationship between memory and CPU.

FIG. 4 shows the relationship between a control unit (hereinafter referred to as CPU) 1, a program memory (ROM) 2, and a memory 3 (i). Note that the program and the hardware that is controlled based on the program are also collectively referred to as firmware.

In FIG. 3, it is assumed that the memory 3(i) is a display data memory for writing a plurality of display data, for example, and is connected to the CPU 1 via a data bus (al).

Further, as shown in FIG. 4, this data bus (al) is connected to the memory 3 (i), and the program memory (
It is also connected to the ROM (ROM) 2, and the CPU reads programs via the data bus (al).

The configuration of such memory 3 (i) is based on a data bus (a
), and a latch circuit 311 that divides the data bus signal received by the buffer circuit 310 into four parts (by display type, for example) and latches them. ~3
14, and a writable and electrically erasable ROM (ROM) that uses the data bus signals latched in the latch circuits 311 to 314 as addresses and writes and stores data input via the data bus (al). (hereinafter referred to as E"FROM) 320~
324, and bidirectional buffer circuits 330 and 331 for exchanging signals and data in both directions between the CPUI and the memory unit 32.
It is equipped with a bidirectional buffer section 33 consisting of.

Based on the program read from the program memory (ROM) 2, the CPU 1 issues display signals for displaying lamps, etc. to the memory 3(i) via the data bus (al) as data bus signals.

This data bus signal is transmitted to four latch circuits 311 to 314.
It's hard to do. For example, the contents to be latched include four types of display signals individually in each latch circuit 311 to 314.
I'm going crazy.

The data latched by each latch circuit 311 to 314 is
Each EEPROM 320 to 324 forming the memory section 32
This is used as a read/write address for writing data from the CPU 1 to each of the EEFROMs 320 to 324 via the bidirectional buffer circuits 330 and 331.

Next, the CPU t reads the data written to each EEPROM 320 to 324 and determines whether the instructed content is the initial one based on the program read from the program memory 2, and performs control based on the program. This means debugging the firmware together with the hardware that will be used.

[Problem to be solved by the invention]

As mentioned above, when debugging firmware using a prototype device that is equivalent to the actual device, the program memory
Based on the program in (ROM) 2, part of the display signal is latched and converted to an address, and judgment can only be made based on the result of reading/writing data at that address, so even if a data error is detected, the latched address signal Is it a mistake?
It is difficult to determine whether this is an error when reading/writing each E'' FROM 320 to 324, and it will be extremely difficult to find firmware bugs from now on.

SUMMARY OF THE INVENTION An object of the present invention is to provide a firmware debugging method that allows a control unit to directly read data issued based on a program and allows efficient and easy debugging.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

1 in the block diagram of the principle of the present invention shown in FIG. 1 is a data bus (1) based on a microprogrammed program.
The data bus signal is issued via the data bus (a), and the stored data bus signal stored in the register unit 34 is issued via the data bus (
30(i) is a memory comprising the following functional blocks 31 to 34; It is a latch unit that latches the data bus signal issued via the data bus (al) connected to the control unit l and outputs the ticked data as an address. The data bus (
33 is a bidirectional buffer unit that exchanges data between the memory unit 32 and the control unit l; 34 is a memory unit that writes data included in the signal in the latch unit 31; This is a register section that stores the following information, and providing such means is a means for solving this problem.

[Effect]

The data bus signal issued by the control unit 1 based on the program in the program memory 2 is latched in the latch unit 31, the latch data is directly stored in the register unit 34, and the data bus signal issued by the control unit 1 is
By reading the data bus signal issued by the direct control unit 1 from the register unit 34 and checking it, firmware debugging can be performed more accurately and easily.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals refer to the same objects throughout the plan.

The present embodiment shown in FIG. 2 shows the configuration of a memory 30a (i) connected to a CPUI (shown in FIG. 4) via a data bus (a) capable of carrying 8-bit data.

In this embodiment of the memory 30a (i), the functional blocks 31 to 33 shown in FIG. 1 have the same contents as those explained in FIG. It is assumed that there are four register circuits 340 to 343 installed corresponding to circuits 311 to 314.

These four register circuits 340 to 343 are used to simultaneously store, for example, display signals latched in the respective latch circuits 311 to 314 when they are sent out as addresses in the memory section 32, and are made up of, for example, flip-flop circuits. .

The four register circuits 340 to 343 are connected to a data bus (al
The contents of the register circuits 340 to 343 can be read directly from the CPU 1, and the contents can be read/written to the memory section 32 via the bidirectional buffer section 33 under the control of the CPU I. It becomes possible.

Therefore, the CPU 1 latches the data bus signal issued via the data bus (al) and directly sends the data bus signal to the register circuits 340 to 340.
It becomes possible to directly compare two data bus signals, the read data bus signal and the data bus signal issued from the CPUI.

Further, it is also possible to compare write data to the memory section 32 and read data from the memory section 32. Therefore,
Firmware can be easily debugged, and debugging efficiency can be improved.

〔Effect of the invention〕

According to the present invention as described above, it is possible to improve the efficiency of firmware debugging.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a block diagram explaining the conventional example, and FIG. 4 is the relationship between memory and CPU. , respectively. In the figure, 1 is the CPU, 2 is the program memory, and 3 (i
), 30(i), 30a(i) are memory, 31 is a latch section, 32 is a memory section, 33 is a bidirectional buffer section, 34 is a register section, 310 is a buffer circuit, 311 to 314 are latch circuits,
320 to 324 are EEPROMs. 330.331 is a bidirectional buffer circuit, 340-343
are the register circuits and , respectively. Figure 4 explains the relationship between memory and CPU; Figure 1 is a block diagram explaining the invention in detail.

Claims (1)

[Claims] A latch unit (31) that latches a data bus signal issued via a data bus ((a)) connected to the control unit (1) and outputs the ticked data as an address.
a memory section (32) that takes in the latch data output from the latch section (31) as an address and writes data included in the signal in the data bus ((a)); and the memory section (32). a bidirectional buffer section (33) that exchanges data with the control section (1) via the data bus ((a)); and a register section that stores latch data output from the latch section (31). (34), the control unit (1) stores the data bus ((a)) based on a microprogrammed program stored in the program memory (2).
) is latched by the latch section (31), and the latched data is stored in the register section (34), and the control section (1) stores the data bus signal in the register section (34). The stored data bus signal is read through the data bus ((a)), and the read data bus signal and the control unit (
1) A firmware debugging method characterized by comparing the firmware with a data bus signal issued from.